add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/infiniband/hw/mlx5/cong.c
..
..
@@ -47,6 +47,7 @@
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47
 	"rp_byte_reset",
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 	"rp_threshold",
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 	"rp_ai_rate",
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+	"rp_max_rate",
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 	"rp_hai_rate",
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 	"rp_min_dec_fac",
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 	"rp_min_rate",
..
..
@@ -56,6 +57,7 @@
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 	"rp_rate_reduce_monitor_period",
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 	"rp_initial_alpha_value",
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 	"rp_gd",
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+	"np_min_time_between_cnps",
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 	"np_cnp_dscp",
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 	"np_cnp_prio_mode",
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 	"np_cnp_prio",
..
..
@@ -66,6 +68,7 @@
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 #define MLX5_IB_RP_TIME_RESET_ATTR			BIT(3)
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 #define MLX5_IB_RP_BYTE_RESET_ATTR			BIT(4)
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 #define MLX5_IB_RP_THRESHOLD_ATTR			BIT(5)
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+#define MLX5_IB_RP_MAX_RATE_ATTR			BIT(6)
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 #define MLX5_IB_RP_AI_RATE_ATTR				BIT(7)
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 #define MLX5_IB_RP_HAI_RATE_ATTR			BIT(8)
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 #define MLX5_IB_RP_MIN_DEC_FAC_ATTR			BIT(9)
..
..
@@ -77,6 +80,7 @@
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 #define MLX5_IB_RP_INITIAL_ALPHA_VALUE_ATTR		BIT(15)
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 #define MLX5_IB_RP_GD_ATTR				BIT(16)
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82
 
83
+#define MLX5_IB_NP_MIN_TIME_BETWEEN_CNPS_ATTR		BIT(2)
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 #define MLX5_IB_NP_CNP_DSCP_ATTR			BIT(3)
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 #define MLX5_IB_NP_CNP_PRIO_MODE_ATTR			BIT(4)
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86
 
..
..
@@ -111,6 +115,9 @@
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 	case MLX5_IB_DBG_CC_RP_AI_RATE:
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 		return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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 				rpg_ai_rate);
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+	case MLX5_IB_DBG_CC_RP_MAX_RATE:
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+		return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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+				rpg_max_rate);
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 	case MLX5_IB_DBG_CC_RP_HAI_RATE:
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 		return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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123
 				rpg_hai_rate);
..
..
@@ -138,6 +145,9 @@
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 	case MLX5_IB_DBG_CC_RP_GD:
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 		return MLX5_GET(cong_control_r_roce_ecn_rp, field,
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 				rpg_gd);
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+	case MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS:
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+		return MLX5_GET(cong_control_r_roce_ecn_np, field,
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+				min_time_between_cnps);
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 	case MLX5_IB_DBG_CC_NP_CNP_DSCP:
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 		return MLX5_GET(cong_control_r_roce_ecn_np, field,
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153
 				cnp_dscp);
..
..
@@ -186,6 +196,11 @@
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 		MLX5_SET(cong_control_r_roce_ecn_rp, field,
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 			 rpg_ai_rate, var);
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 		break;
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+	case MLX5_IB_DBG_CC_RP_MAX_RATE:
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+		*attr_mask |= MLX5_IB_RP_MAX_RATE_ATTR;
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+		MLX5_SET(cong_control_r_roce_ecn_rp, field,
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+			 rpg_max_rate, var);
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+		break;
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 	case MLX5_IB_DBG_CC_RP_HAI_RATE:
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 		*attr_mask |= MLX5_IB_RP_HAI_RATE_ATTR;
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 		MLX5_SET(cong_control_r_roce_ecn_rp, field,
..
..
@@ -231,6 +246,11 @@
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 		MLX5_SET(cong_control_r_roce_ecn_rp, field,
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 			 rpg_gd, var);
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 		break;
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+	case MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS:
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+		*attr_mask |= MLX5_IB_NP_MIN_TIME_BETWEEN_CNPS_ATTR;
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+		MLX5_SET(cong_control_r_roce_ecn_np, field,
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+			 min_time_between_cnps, var);
253
+		break;
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 	case MLX5_IB_DBG_CC_NP_CNP_DSCP:
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 		*attr_mask |= MLX5_IB_NP_CNP_DSCP_ATTR;
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 		MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_dscp, var);
..
..
@@ -270,7 +290,7 @@
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290
 
271
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 	node = mlx5_ib_param_to_node(offset);
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292
 
273
-	err = mlx5_cmd_query_cong_params(mdev, node, out, outlen);
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+	err = mlx5_cmd_query_cong_params(mdev, node, out);
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294
 	if (err)
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295
 		goto free;
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296
 
..
..
@@ -319,7 +339,7 @@
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 	MLX5_SET(field_select_r_roce_rp, field, field_select_r_roce_rp,
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340
 		 attr_mask);
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341
 
322
-	err = mlx5_cmd_modify_cong_params(mdev, in, inlen);
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+	err = mlx5_cmd_exec_in(dev->mdev, modify_cong_params, in);
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343
 	kvfree(in);
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 alloc_err:
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 	mlx5_ib_put_native_port_mdev(dev, port_num + 1);
..
..
@@ -389,19 +409,19 @@
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 	dev->port[port_num].dbg_cc_params = NULL;
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410
 }
391
411
 
392
-int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num)
412
+void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num)
393
413
 {
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414
 	struct mlx5_ib_dbg_cc_params *dbg_cc_params;
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415
 	struct mlx5_core_dev *mdev;
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416
 	int i;
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417
 
398
418
 	if (!mlx5_debugfs_root)
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-		goto out;
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+		return;
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420
 
401
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 	/* Takes a 1-based port number */
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 	mdev = mlx5_ib_get_native_port_mdev(dev, port_num + 1, NULL);
403
423
 	if (!mdev)
404
-		goto out;
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+		return;
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425
 
406
426
 	if (!MLX5_CAP_GEN(mdev, cc_query_allowed) ||
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427
 	    !MLX5_CAP_GEN(mdev, cc_modify_allowed))
..
..
@@ -415,8 +435,6 @@
415
435
 
416
436
 	dbg_cc_params->root = debugfs_create_dir("cc_params",
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 						 mdev->priv.dbg_root);
418
-	if (!dbg_cc_params->root)
419
-		goto err;
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438
 
421
439
 	for (i = 0; i < MLX5_IB_DBG_CC_MAX; i++) {
422
440
 		dbg_cc_params->params[i].offset = i;
..
..
@@ -427,14 +445,11 @@
427
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 					    0600, dbg_cc_params->root,
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446
 					    &dbg_cc_params->params[i],
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447
 					    &dbg_cc_fops);
430
-		if (!dbg_cc_params->params[i].dentry)
431
-			goto err;
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448
 	}
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449
 
434
450
 put_mdev:
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 	mlx5_ib_put_native_port_mdev(dev, port_num + 1);
436
-out:
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-	return 0;
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+	return;
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453
 
439
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 err:
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 	mlx5_ib_warn(dev, "cong debugfs failure\n");
..
..
@@ -445,5 +460,5 @@
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 	 * We don't want to fail driver if debugfs failed to initialize,
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 	 * so we are not forwarding error to the user.
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 	 */
448
-	return 0;
463
+	return;
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464
 }