add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/infiniband/hw/hfi1/chip.h
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@@ -1,7 +1,7 @@
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 #ifndef _CHIP_H
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 #define _CHIP_H
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 /*
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- * Copyright(c) 2015 - 2017 Intel Corporation.
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+ * Copyright(c) 2015 - 2020 Intel Corporation.
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  *
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  * This file is provided under a dual BSD/GPLv2 license.  When using or
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  * redistributing this file, you may do so under either license.
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@@ -52,9 +52,7 @@
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  */
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 /* sizes */
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-#define CCE_NUM_MSIX_VECTORS 256
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-#define CCE_NUM_INT_CSRS 12
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-#define CCE_NUM_INT_MAP_CSRS 96
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+#define BITS_PER_REGISTER (BITS_PER_BYTE * sizeof(u64))
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 #define NUM_INTERRUPT_SOURCES 768
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 #define RXE_NUM_CONTEXTS 160
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 #define RXE_PER_CONTEXT_SIZE 0x1000	/* 4k */
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@@ -161,34 +159,49 @@
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 	(CR_CREDIT_RETURN_DUE_TO_FORCE_MASK << \
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 	CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT)
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161
 
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-/* interrupt source numbers */
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-#define IS_GENERAL_ERR_START	  0
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-#define IS_SDMAENG_ERR_START	 16
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-#define IS_SENDCTXT_ERR_START	 32
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-#define IS_SDMA_START		192 /* includes SDmaProgress,SDmaIdle */
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+/* Specific IRQ sources */
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+#define CCE_ERR_INT		  0
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+#define RXE_ERR_INT		  1
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+#define MISC_ERR_INT		  2
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+#define PIO_ERR_INT		  4
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+#define SDMA_ERR_INT		  5
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+#define EGRESS_ERR_INT		  6
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+#define TXE_ERR_INT		  7
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+#define PBC_INT			240
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+#define GPIO_ASSERT_INT		241
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+#define QSFP1_INT		242
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+#define QSFP2_INT		243
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+#define TCRIT_INT		244
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+
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+/* interrupt source ranges */
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+#define IS_FIRST_SOURCE		CCE_ERR_INT
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+#define IS_GENERAL_ERR_START		  0
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+#define IS_SDMAENG_ERR_START		 16
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+#define IS_SENDCTXT_ERR_START		 32
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+#define IS_SDMA_START			192
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+#define IS_SDMA_PROGRESS_START		208
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+#define IS_SDMA_IDLE_START		224
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 #define IS_VARIOUS_START		240
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 #define IS_DC_START			248
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 #define IS_RCVAVAIL_START		256
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 #define IS_RCVURGENT_START		416
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 #define IS_SENDCREDIT_START		576
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 #define IS_RESERVED_START		736
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-#define IS_MAX_SOURCES		768
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+#define IS_LAST_SOURCE			767
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 /* derived interrupt source values */
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-#define IS_GENERAL_ERR_END		IS_SDMAENG_ERR_START
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-#define IS_SDMAENG_ERR_END		IS_SENDCTXT_ERR_START
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-#define IS_SENDCTXT_ERR_END		IS_SDMA_START
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-#define IS_SDMA_END			IS_VARIOUS_START
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-#define IS_VARIOUS_END		IS_DC_START
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-#define IS_DC_END			IS_RCVAVAIL_START
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-#define IS_RCVAVAIL_END		IS_RCVURGENT_START
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-#define IS_RCVURGENT_END		IS_SENDCREDIT_START
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-#define IS_SENDCREDIT_END		IS_RESERVED_START
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-#define IS_RESERVED_END		IS_MAX_SOURCES
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-
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-/* absolute interrupt numbers for QSFP1Int and QSFP2Int */
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-#define QSFP1_INT		242
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-#define QSFP2_INT		243
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+#define IS_GENERAL_ERR_END		7
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+#define IS_SDMAENG_ERR_END		31
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+#define IS_SENDCTXT_ERR_END		191
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+#define IS_SDMA_END                     207
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+#define IS_SDMA_PROGRESS_END            223
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+#define IS_SDMA_IDLE_END		239
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+#define IS_VARIOUS_END			244
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+#define IS_DC_END			255
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+#define IS_RCVAVAIL_END			415
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+#define IS_RCVURGENT_END		575
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+#define IS_SENDCREDIT_END		735
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+#define IS_RESERVED_END			IS_LAST_SOURCE
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 /* DCC_CFG_PORT_CONFIG logical link states */
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 #define LSTATE_DOWN    0x1
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@@ -345,6 +358,8 @@
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 #define MAX_EAGER_BUFFER       (256 * 1024)
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 #define MAX_EAGER_BUFFER_TOTAL (64 * (1 << 20)) /* max per ctxt 64MB */
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 #define MAX_EXPECTED_BUFFER    (2048 * 1024)
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+#define HFI1_MIN_HDRQ_EGRBUF_CNT 32
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+#define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
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 /*
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  * Receive expected base and count and eager base and count increment -
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@@ -686,6 +701,10 @@
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 	return read_csr(dd, RCV_ARRAY_CNT);
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 }
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+u8 encode_rcv_header_entry_size(u8 size);
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+int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt);
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+void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt);
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+
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 u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,
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 	       u32 dw_len);
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@@ -791,6 +810,7 @@
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 u32 hdrqempty(struct hfi1_ctxtdata *rcd);
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 int is_ax(struct hfi1_devdata *dd);
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 int is_bx(struct hfi1_devdata *dd);
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+bool is_urg_masked(struct hfi1_ctxtdata *rcd);
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 u32 read_physical_state(struct hfi1_devdata *dd);
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 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate);
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 const char *opa_lstate_name(u32 lstate);
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@@ -844,6 +864,10 @@
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 /* Per device counter indexes */
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 enum {
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 	C_RCV_OVF = 0,
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+	C_RX_LEN_ERR,
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+	C_RX_SHORT_ERR,
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+	C_RX_ICRC_ERR,
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+	C_RX_EBP,
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 	C_RX_TID_FULL,
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 	C_RX_TID_INVALID,
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 	C_RX_TID_FLGMS,
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@@ -914,6 +938,7 @@
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 	C_SW_PIO_WAIT,
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 	C_SW_PIO_DRAIN,
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 	C_SW_KMEM_WAIT,
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+	C_SW_TID_WAIT,
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 	C_SW_SEND_SCHED,
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 	C_SDMA_DESC_FETCHED_CNT,
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 	C_SDMA_INT_CNT,
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@@ -1228,6 +1253,7 @@
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 	C_SW_IBP_RDMA_SEQ,
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 	C_SW_IBP_UNALIGNED,
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 	C_SW_IBP_SEQ_NAK,
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+	C_SW_IBP_RC_CRWAITS,
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 	C_SW_CPU_RC_ACKS,
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 	C_SW_CPU_RC_QACKS,
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 	C_SW_CPU_RC_DELAYED_COMP,
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@@ -1417,6 +1443,22 @@
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 void hfi1_init_vnic_rsm(struct hfi1_devdata *dd);
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 void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd);
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+irqreturn_t general_interrupt(int irq, void *data);
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+irqreturn_t sdma_interrupt(int irq, void *data);
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+irqreturn_t receive_context_interrupt(int irq, void *data);
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+irqreturn_t receive_context_thread(int irq, void *data);
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+irqreturn_t receive_context_interrupt_napi(int irq, void *data);
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+
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+int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set);
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+void init_qsfp_int(struct hfi1_devdata *dd);
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+void clear_all_interrupts(struct hfi1_devdata *dd);
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+void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr);
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+void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr);
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+void reset_interrupts(struct hfi1_devdata *dd);
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+u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx);
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+void hfi1_init_aip_rsm(struct hfi1_devdata *dd);
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+void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd);
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+
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 /*
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  * Interrupt source table.
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  *