~hc/RK356X_SDK_RELEASE.git

..	..	@@ -86,6 +86,55 @@
86	86	# define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c
87	87	# define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
88	88
	89	+#define V3D_TFU_CS 0x00400
	90	+/* Stops current job, empties input fifo. */
	91	+# define V3D_TFU_CS_TFURST BIT(31)
	92	+# define V3D_TFU_CS_CVTCT_MASK V3D_MASK(23, 16)
	93	+# define V3D_TFU_CS_CVTCT_SHIFT 16
	94	+# define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8)
	95	+# define V3D_TFU_CS_NFREE_SHIFT 8
	96	+# define V3D_TFU_CS_BUSY BIT(0)
	97	+
	98	+#define V3D_TFU_SU 0x00404
	99	+/* Interrupt when FINTTHR input slots are free (0 = disabled) */
	100	+# define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8)
	101	+# define V3D_TFU_SU_FINTTHR_SHIFT 8
	102	+/* Skips resetting the CRC at the start of CRC generation. */
	103	+# define V3D_TFU_SU_CRCCHAIN BIT(4)
	104	+/* skips writes, computes CRC of the image. miplevels must be 0. */
	105	+# define V3D_TFU_SU_CRC BIT(3)
	106	+# define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0)
	107	+# define V3D_TFU_SU_THROTTLE_SHIFT 0
	108	+
	109	+#define V3D_TFU_ICFG 0x00408
	110	+/* Interrupt when the conversion is complete. */
	111	+# define V3D_TFU_ICFG_IOC BIT(0)
	112	+
	113	+/* Input Image Address */
	114	+#define V3D_TFU_IIA 0x0040c
	115	+/* Input Chroma Address */
	116	+#define V3D_TFU_ICA 0x00410
	117	+/* Input Image Stride */
	118	+#define V3D_TFU_IIS 0x00414
	119	+/* Input Image U-Plane Address */
	120	+#define V3D_TFU_IUA 0x00418
	121	+/* Output Image Address */
	122	+#define V3D_TFU_IOA 0x0041c
	123	+/* Image Output Size */
	124	+#define V3D_TFU_IOS 0x00420
	125	+/* TFU YUV Coefficient 0 */
	126	+#define V3D_TFU_COEF0 0x00424
	127	+/* Use these regs instead of the defaults. */
	128	+# define V3D_TFU_COEF0_USECOEF BIT(31)
	129	+/* TFU YUV Coefficient 1 */
	130	+#define V3D_TFU_COEF1 0x00428
	131	+/* TFU YUV Coefficient 2 */
	132	+#define V3D_TFU_COEF2 0x0042c
	133	+/* TFU YUV Coefficient 3 */
	134	+#define V3D_TFU_COEF3 0x00430
	135	+
	136	+#define V3D_TFU_CRC 0x00434
	137	+
89	138	/* Per-MMU registers. */
90	139
91	140	#define V3D_MMUC_CONTROL 0x01000
..	..	@@ -103,7 +152,8 @@
103	152	# define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19)
104	153	# define V3D_MMU_CTL_PT_INVALID_INT BIT(18)
105	154	# define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17)
106		-# define V3D_MMU_CTL_WRITE_VIOLATION BIT(16)
	155	+# define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16)
	156	+# define V3D_MMU_CTL_WRITE_VIOLATION BIT(12)
107	157	# define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11)
108	158	# define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10)
109	159	# define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9)
..	..	@@ -142,6 +192,14 @@
142	192	/* Address that faulted */
143	193	#define V3D_MMU_VIO_ADDR 0x01234
144	194
	195	+#define V3D_MMU_DEBUG_INFO 0x01238
	196	+# define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8)
	197	+# define V3D_MMU_PA_WIDTH_SHIFT 8
	198	+# define V3D_MMU_VA_WIDTH_MASK V3D_MASK(7, 4)
	199	+# define V3D_MMU_VA_WIDTH_SHIFT 4
	200	+# define V3D_MMU_VERSION_MASK V3D_MASK(3, 0)
	201	+# define V3D_MMU_VERSION_SHIFT 0
	202	+
145	203	/* Per-V3D-core registers */
146	204
147	205	#define V3D_CTL_IDENT0 0x00000
..	..	@@ -167,6 +225,8 @@
167	225	# define V3D_IDENT2_BCG_INT BIT(28)
168	226
169	227	#define V3D_CTL_MISCCFG 0x00018
	228	+# define V3D_CTL_MISCCFG_QRMAXCNT_MASK V3D_MASK(3, 1)
	229	+# define V3D_CTL_MISCCFG_QRMAXCNT_SHIFT 1
170	230	# define V3D_MISCCFG_OVRTMUOUT BIT(0)
171	231
172	232	#define V3D_CTL_L2CACTL 0x00020
..	..	@@ -187,8 +247,11 @@
187	247	#define V3D_CTL_L2TCACTL 0x00030
188	248	# define V3D_L2TCACTL_TMUWCF BIT(8)
189	249	# define V3D_L2TCACTL_L2T_NO_WM BIT(4)
	250	+/* Invalidates cache lines. */
190	251	# define V3D_L2TCACTL_FLM_FLUSH 0
	252	+/* Removes cachelines without writing dirty lines back. */
191	253	# define V3D_L2TCACTL_FLM_CLEAR 1
	254	+/* Writes out dirty cachelines and marks them clean, but doesn't invalidate. */
192	255	# define V3D_L2TCACTL_FLM_CLEAN 2
193	256	# define V3D_L2TCACTL_FLM_MASK V3D_MASK(2, 1)
194	257	# define V3D_L2TCACTL_FLM_SHIFT 1
..	..	@@ -204,6 +267,8 @@
204	267	#define V3D_CTL_INT_MSK_CLR 0x00064
205	268	# define V3D_INT_QPU_MASK V3D_MASK(27, 16)
206	269	# define V3D_INT_QPU_SHIFT 16
	270	+# define V3D_INT_CSDDONE BIT(7)
	271	+# define V3D_INT_PCTR BIT(6)
207	272	# define V3D_INT_GMPV BIT(5)
208	273	# define V3D_INT_TRFB BIT(4)
209	274	# define V3D_INT_SPILLUSE BIT(3)
..	..	@@ -267,6 +332,36 @@
267	332	# define V3D_PTB_BXCF_RWORDERDISA BIT(1)
268	333	# define V3D_PTB_BXCF_CLIPDISA BIT(0)
269	334
	335	+#define V3D_V3_PCTR_0_EN 0x00674
	336	+#define V3D_V3_PCTR_0_EN_ENABLE BIT(31)
	337	+#define V3D_V4_PCTR_0_EN 0x00650
	338	+/* When a bit is set, resets the counter to 0. */
	339	+#define V3D_V3_PCTR_0_CLR 0x00670
	340	+#define V3D_V4_PCTR_0_CLR 0x00654
	341	+#define V3D_PCTR_0_OVERFLOW 0x00658
	342	+
	343	+#define V3D_V3_PCTR_0_PCTRS0 0x00684
	344	+#define V3D_V3_PCTR_0_PCTRS15 0x00660
	345	+#define V3D_V3_PCTR_0_PCTRSX(x) (V3D_V3_PCTR_0_PCTRS0 + \
	346	+ 4 * (x))
	347	+/* Each src reg muxes four counters each. */
	348	+#define V3D_V4_PCTR_0_SRC_0_3 0x00660
	349	+#define V3D_V4_PCTR_0_SRC_28_31 0x0067c
	350	+# define V3D_PCTR_S0_MASK V3D_MASK(6, 0)
	351	+# define V3D_PCTR_S0_SHIFT 0
	352	+# define V3D_PCTR_S1_MASK V3D_MASK(14, 8)
	353	+# define V3D_PCTR_S1_SHIFT 8
	354	+# define V3D_PCTR_S2_MASK V3D_MASK(22, 16)
	355	+# define V3D_PCTR_S2_SHIFT 16
	356	+# define V3D_PCTR_S3_MASK V3D_MASK(30, 24)
	357	+# define V3D_PCTR_S3_SHIFT 24
	358	+# define V3D_PCTR_CYCLE_COUNT 32
	359	+
	360	+/* Output values of the counters. */
	361	+#define V3D_PCTR_0_PCTR0 0x00680
	362	+#define V3D_PCTR_0_PCTR31 0x006fc
	363	+#define V3D_PCTR_0_PCTRX(x) (V3D_PCTR_0_PCTR0 + \
	364	+ 4 * (x))
270	365	#define V3D_GMP_STATUS 0x00800
271	366	# define V3D_GMP_STATUS_GMPRST BIT(31)
272	367	# define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24)
..	..	@@ -293,4 +388,110 @@
293	388	#define V3D_GMP_PRESERVE_LOAD 0x00818
294	389	#define V3D_GMP_VALID_LINES 0x00820
295	390
	391	+#define V3D_CSD_STATUS 0x00900
	392	+# define V3D_CSD_STATUS_NUM_COMPLETED_MASK V3D_MASK(11, 4)
	393	+# define V3D_CSD_STATUS_NUM_COMPLETED_SHIFT 4
	394	+# define V3D_CSD_STATUS_NUM_ACTIVE_MASK V3D_MASK(3, 2)
	395	+# define V3D_CSD_STATUS_NUM_ACTIVE_SHIFT 2
	396	+# define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1)
	397	+# define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0)
	398	+
	399	+#define V3D_CSD_QUEUED_CFG0 0x00904
	400	+# define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_MASK V3D_MASK(31, 16)
	401	+# define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_SHIFT 16
	402	+# define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK V3D_MASK(15, 0)
	403	+# define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT 0
	404	+
	405	+#define V3D_CSD_QUEUED_CFG1 0x00908
	406	+# define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_MASK V3D_MASK(31, 16)
	407	+# define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_SHIFT 16
	408	+# define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK V3D_MASK(15, 0)
	409	+# define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT 0
	410	+
	411	+#define V3D_CSD_QUEUED_CFG2 0x0090c
	412	+# define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_MASK V3D_MASK(31, 16)
	413	+# define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_SHIFT 16
	414	+# define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK V3D_MASK(15, 0)
	415	+# define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT 0
	416	+
	417	+#define V3D_CSD_QUEUED_CFG3 0x00910
	418	+# define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26)
	419	+# define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_MASK V3D_MASK(25, 20)
	420	+# define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_SHIFT 20
	421	+# define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_MASK V3D_MASK(19, 12)
	422	+# define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_SHIFT 12
	423	+# define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK V3D_MASK(11, 8)
	424	+# define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT 8
	425	+# define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK V3D_MASK(7, 0)
	426	+# define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT 0
	427	+
	428	+/* Number of batches, minus 1 */
	429	+#define V3D_CSD_QUEUED_CFG4 0x00914
	430	+
	431	+/* Shader address, pnan, singleseg, threading, like a shader record. */
	432	+#define V3D_CSD_QUEUED_CFG5 0x00918
	433	+
	434	+/* Uniforms address (4 byte aligned) */
	435	+#define V3D_CSD_QUEUED_CFG6 0x0091c
	436	+
	437	+#define V3D_CSD_CURRENT_CFG0 0x00920
	438	+#define V3D_CSD_CURRENT_CFG1 0x00924
	439	+#define V3D_CSD_CURRENT_CFG2 0x00928
	440	+#define V3D_CSD_CURRENT_CFG3 0x0092c
	441	+#define V3D_CSD_CURRENT_CFG4 0x00930
	442	+#define V3D_CSD_CURRENT_CFG5 0x00934
	443	+#define V3D_CSD_CURRENT_CFG6 0x00938
	444	+
	445	+#define V3D_CSD_CURRENT_ID0 0x0093c
	446	+# define V3D_CSD_CURRENT_ID0_WG_X_MASK V3D_MASK(31, 16)
	447	+# define V3D_CSD_CURRENT_ID0_WG_X_SHIFT 16
	448	+# define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK V3D_MASK(11, 8)
	449	+# define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT 8
	450	+# define V3D_CSD_CURRENT_ID0_L_IDX_MASK V3D_MASK(7, 0)
	451	+# define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT 0
	452	+
	453	+#define V3D_CSD_CURRENT_ID1 0x00940
	454	+# define V3D_CSD_CURRENT_ID0_WG_Z_MASK V3D_MASK(31, 16)
	455	+# define V3D_CSD_CURRENT_ID0_WG_Z_SHIFT 16
	456	+# define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0)
	457	+# define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0
	458	+
	459	+#define V3D_ERR_FDBGO 0x00f04
	460	+#define V3D_ERR_FDBGB 0x00f08
	461	+#define V3D_ERR_FDBGR 0x00f0c
	462	+
	463	+#define V3D_ERR_FDBGS 0x00f10
	464	+# define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17)
	465	+# define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16)
	466	+# define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14)
	467	+# define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13)
	468	+# define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12)
	469	+# define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11)
	470	+# define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7)
	471	+# define V3D_ERR_FDBGS_EZTEST_PASS BIT(6)
	472	+# define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5)
	473	+# define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4)
	474	+# define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3)
	475	+# define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2)
	476	+# define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1)
	477	+# define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0)
	478	+
	479	+#define V3D_ERR_STAT 0x00f20
	480	+# define V3D_ERR_L2CARE BIT(15)
	481	+# define V3D_ERR_VCMBE BIT(14)
	482	+# define V3D_ERR_VCMRE BIT(13)
	483	+# define V3D_ERR_VCDI BIT(12)
	484	+# define V3D_ERR_VCDE BIT(11)
	485	+# define V3D_ERR_VDWE BIT(10)
	486	+# define V3D_ERR_VPMEAS BIT(9)
	487	+# define V3D_ERR_VPMEFNA BIT(8)
	488	+# define V3D_ERR_VPMEWNA BIT(7)
	489	+# define V3D_ERR_VPMERNA BIT(6)
	490	+# define V3D_ERR_VPMERR BIT(5)
	491	+# define V3D_ERR_VPMEWR BIT(4)
	492	+# define V3D_ERR_VPAERRGL BIT(3)
	493	+# define V3D_ERR_VPAEBRGL BIT(2)
	494	+# define V3D_ERR_VPAERGS BIT(1)
	495	+# define V3D_ERR_VPAEABB BIT(0)
	496	+
296	497	#endif /* V3D_REGS_H */