add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/radeon/radeon_object.c
..
..
@@ -29,14 +29,17 @@
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  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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  *    Dave Airlie
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  */
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+
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+#include <linux/io.h>
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 #include <linux/list.h>
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 #include <linux/slab.h>
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-#include <drm/drmP.h>
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-#include <drm/radeon_drm.h>
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+
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 #include <drm/drm_cache.h>
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+#include <drm/drm_prime.h>
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+#include <drm/radeon_drm.h>
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+
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 #include "radeon.h"
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 #include "radeon_trace.h"
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-
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43
 
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 int radeon_ttm_init(struct radeon_device *rdev);
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 void radeon_ttm_fini(struct radeon_device *rdev);
..
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@@ -82,9 +85,9 @@
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 	mutex_unlock(&bo->rdev->gem.mutex);
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 	radeon_bo_clear_surface_reg(bo);
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 	WARN_ON_ONCE(!list_empty(&bo->va));
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-	if (bo->gem_base.import_attach)
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-		drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
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-	drm_gem_object_release(&bo->gem_base);
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+	if (bo->tbo.base.import_attach)
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+		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
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+	drm_gem_object_release(&bo->tbo.base);
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 	kfree(bo);
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 }
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..
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@@ -109,58 +112,58 @@
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 		    rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
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 			rbo->placements[c].fpfn =
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 				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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+			rbo->placements[c].mem_type = TTM_PL_VRAM;
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 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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-						     TTM_PL_FLAG_UNCACHED |
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-						     TTM_PL_FLAG_VRAM;
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+						     TTM_PL_FLAG_UNCACHED;
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 		}
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119
 
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 		rbo->placements[c].fpfn = 0;
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+		rbo->placements[c].mem_type = TTM_PL_VRAM;
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 		rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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-					     TTM_PL_FLAG_UNCACHED |
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-					     TTM_PL_FLAG_VRAM;
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+					     TTM_PL_FLAG_UNCACHED;
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 	}
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 	if (domain & RADEON_GEM_DOMAIN_GTT) {
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 		if (rbo->flags & RADEON_GEM_GTT_UC) {
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 			rbo->placements[c].fpfn = 0;
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-			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
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-				TTM_PL_FLAG_TT;
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+			rbo->placements[c].mem_type = TTM_PL_TT;
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+			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
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 		} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
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 			   (rbo->rdev->flags & RADEON_IS_AGP)) {
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 			rbo->placements[c].fpfn = 0;
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+			rbo->placements[c].mem_type = TTM_PL_TT;
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 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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-				TTM_PL_FLAG_UNCACHED |
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-				TTM_PL_FLAG_TT;
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+				TTM_PL_FLAG_UNCACHED;
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 		} else {
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 			rbo->placements[c].fpfn = 0;
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-			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
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-						     TTM_PL_FLAG_TT;
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+			rbo->placements[c].mem_type = TTM_PL_TT;
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+			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
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 		}
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 	}
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 	if (domain & RADEON_GEM_DOMAIN_CPU) {
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 		if (rbo->flags & RADEON_GEM_GTT_UC) {
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 			rbo->placements[c].fpfn = 0;
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-			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
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-				TTM_PL_FLAG_SYSTEM;
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+			rbo->placements[c].mem_type = TTM_PL_SYSTEM;
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+			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED;
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 		} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
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 		    rbo->rdev->flags & RADEON_IS_AGP) {
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 			rbo->placements[c].fpfn = 0;
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+			rbo->placements[c].mem_type = TTM_PL_SYSTEM;
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 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
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-				TTM_PL_FLAG_UNCACHED |
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-				TTM_PL_FLAG_SYSTEM;
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+				TTM_PL_FLAG_UNCACHED;
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 		} else {
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 			rbo->placements[c].fpfn = 0;
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-			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
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-						     TTM_PL_FLAG_SYSTEM;
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+			rbo->placements[c].mem_type = TTM_PL_SYSTEM;
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+			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED;
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 		}
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 	}
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 	if (!c) {
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 		rbo->placements[c].fpfn = 0;
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-		rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
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-					     TTM_PL_FLAG_SYSTEM;
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+		rbo->placements[c].mem_type = TTM_PL_SYSTEM;
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+		rbo->placements[c++].flags = TTM_PL_MASK_CACHING;
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 	}
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 	rbo->placement.num_placement = c;
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@@ -168,7 +171,7 @@
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 	for (i = 0; i < c; ++i) {
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 		if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
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-		    (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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+		    (rbo->placements[i].mem_type == TTM_PL_VRAM) &&
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 		    !rbo->placements[i].fpfn)
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 			rbo->placements[i].lpfn =
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 				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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@@ -180,7 +183,7 @@
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 int radeon_bo_create(struct radeon_device *rdev,
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 		     unsigned long size, int byte_align, bool kernel,
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 		     u32 domain, u32 flags, struct sg_table *sg,
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-		     struct reservation_object *resv,
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+		     struct dma_resv *resv,
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 		     struct radeon_bo **bo_ptr)
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 {
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 	struct radeon_bo *bo;
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@@ -206,7 +209,7 @@
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 	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
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 	if (bo == NULL)
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 		return -ENOMEM;
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-	drm_gem_private_object_init(rdev->ddev, &bo->gem_base, size);
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+	drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
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 	bo->rdev = rdev;
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 	bo->surface_reg = -1;
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 	INIT_LIST_HEAD(&bo->list);
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@@ -314,11 +317,9 @@
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 void radeon_bo_unref(struct radeon_bo **bo)
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 {
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 	struct ttm_buffer_object *tbo;
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-	struct radeon_device *rdev;
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320
 
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 	if ((*bo) == NULL)
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 		return;
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-	rdev = (*bo)->rdev;
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 	tbo = &((*bo)->tbo);
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 	ttm_bo_put(tbo);
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 	*bo = NULL;
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@@ -330,7 +331,7 @@
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 	struct ttm_operation_ctx ctx = { false, false };
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 	int r, i;
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333
 
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-	if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
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+	if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
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 		return -EPERM;
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336
 
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 	if (bo->pin_count) {
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@@ -359,7 +360,7 @@
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 	radeon_ttm_placement_from_domain(bo, domain);
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 	for (i = 0; i < bo->placement.num_placement; i++) {
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 		/* force to pin into visible video ram */
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-		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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+		if ((bo->placements[i].mem_type == TTM_PL_VRAM) &&
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 		    !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
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 		    (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
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 			bo->placements[i].lpfn =
..
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@@ -421,11 +422,13 @@
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 int radeon_bo_evict_vram(struct radeon_device *rdev)
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 {
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 	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
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-	if (0 && (rdev->flags & RADEON_IS_IGP)) {
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+#ifndef CONFIG_HIBERNATION
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+	if (rdev->flags & RADEON_IS_IGP) {
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 		if (rdev->mc.igp_sideport_enabled == false)
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 			/* Useless to evict on IGP chips */
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 			return 0;
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 	}
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+#endif
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 	return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
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 }
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@@ -439,13 +442,13 @@
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 	dev_err(rdev->dev, "Userspace still has active objects !\n");
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 	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
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 		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
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-			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
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-			*((unsigned long *)&bo->gem_base.refcount));
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+			&bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
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+			*((unsigned long *)&bo->tbo.base.refcount));
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 		mutex_lock(&bo->rdev->gem.mutex);
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 		list_del_init(&bo->list);
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 		mutex_unlock(&bo->rdev->gem.mutex);
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 		/* this should unref the ttm bo */
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-		drm_gem_object_put_unlocked(&bo->gem_base);
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+		drm_gem_object_put(&bo->tbo.base);
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 	}
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 }
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@@ -607,7 +610,7 @@
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 	int steal;
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 	int i;
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-	lockdep_assert_held(&bo->tbo.resv->lock.base);
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+	dma_resv_assert_held(bo->tbo.base.resv);
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614
 
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 	if (!bo->tiling_flags)
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 		return 0;
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@@ -733,7 +736,7 @@
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 				uint32_t *tiling_flags,
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 				uint32_t *pitch)
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 {
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-	lockdep_assert_held(&bo->tbo.resv->lock.base);
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+	dma_resv_assert_held(bo->tbo.base.resv);
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740
 
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 	if (tiling_flags)
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 		*tiling_flags = bo->tiling_flags;
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@@ -745,7 +748,7 @@
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 				bool force_drop)
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 {
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 	if (!force_drop)
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-		lockdep_assert_held(&bo->tbo.resv->lock.base);
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+		dma_resv_assert_held(bo->tbo.base.resv);
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 	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
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 		return 0;
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@@ -772,7 +775,7 @@
772
775
 
773
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 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
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 			   bool evict,
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-			   struct ttm_mem_reg *new_mem)
778
+			   struct ttm_resource *new_mem)
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 {
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 	struct radeon_bo *rbo;
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781
 
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@@ -821,7 +824,7 @@
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 	lpfn =	rdev->mc.visible_vram_size >> PAGE_SHIFT;
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 	for (i = 0; i < rbo->placement.num_placement; i++) {
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 		/* Force into visible VRAM */
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-		if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
827
+		if ((rbo->placements[i].mem_type == TTM_PL_VRAM) &&
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 		    (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
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 			rbo->placements[i].lpfn = lpfn;
827
830
 	}
..
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@@ -867,10 +870,10 @@
867
870
 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
868
871
 		     bool shared)
869
872
 {
870
-	struct reservation_object *resv = bo->tbo.resv;
873
+	struct dma_resv *resv = bo->tbo.base.resv;
871
874
 
872
875
 	if (shared)
873
-		reservation_object_add_shared_fence(resv, &fence->base);
876
+		dma_resv_add_shared_fence(resv, &fence->base);
874
877
 	else
875
-		reservation_object_add_excl_fence(resv, &fence->base);
878
+		dma_resv_add_excl_fence(resv, &fence->base);
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879
 }