.. | .. |
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86 | 86 | uint64_t src_offset, |
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87 | 87 | uint64_t dst_offset, |
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88 | 88 | unsigned num_gpu_pages, |
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89 | | - struct reservation_object *resv); |
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| 89 | + struct dma_resv *resv); |
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90 | 90 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
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91 | 91 | uint32_t tiling_flags, uint32_t pitch, |
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92 | 92 | uint32_t offset, uint32_t obj_size); |
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.. | .. |
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157 | 157 | uint64_t src_offset, |
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158 | 158 | uint64_t dst_offset, |
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159 | 159 | unsigned num_gpu_pages, |
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160 | | - struct reservation_object *resv); |
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| 160 | + struct dma_resv *resv); |
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161 | 161 | void r200_set_safe_registers(struct radeon_device *rdev); |
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162 | 162 | |
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163 | 163 | /* |
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.. | .. |
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347 | 347 | struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, |
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348 | 348 | uint64_t src_offset, uint64_t dst_offset, |
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349 | 349 | unsigned num_gpu_pages, |
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350 | | - struct reservation_object *resv); |
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| 350 | + struct dma_resv *resv); |
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351 | 351 | struct radeon_fence *r600_copy_dma(struct radeon_device *rdev, |
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352 | 352 | uint64_t src_offset, uint64_t dst_offset, |
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353 | 353 | unsigned num_gpu_pages, |
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354 | | - struct reservation_object *resv); |
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| 354 | + struct dma_resv *resv); |
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355 | 355 | void r600_hpd_init(struct radeon_device *rdev); |
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356 | 356 | void r600_hpd_fini(struct radeon_device *rdev); |
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357 | 357 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
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.. | .. |
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473 | 473 | struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev, |
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474 | 474 | uint64_t src_offset, uint64_t dst_offset, |
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475 | 475 | unsigned num_gpu_pages, |
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476 | | - struct reservation_object *resv); |
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| 476 | + struct dma_resv *resv); |
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477 | 477 | u32 rv770_get_xclk(struct radeon_device *rdev); |
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478 | 478 | int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
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479 | 479 | int rv770_get_temp(struct radeon_device *rdev); |
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.. | .. |
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547 | 547 | struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, |
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548 | 548 | uint64_t src_offset, uint64_t dst_offset, |
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549 | 549 | unsigned num_gpu_pages, |
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550 | | - struct reservation_object *resv); |
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| 550 | + struct dma_resv *resv); |
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551 | 551 | int evergreen_get_temp(struct radeon_device *rdev); |
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552 | 552 | int evergreen_get_allowed_info_register(struct radeon_device *rdev, |
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553 | 553 | u32 reg, u32 *val); |
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.. | .. |
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725 | 725 | struct radeon_fence *si_copy_dma(struct radeon_device *rdev, |
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726 | 726 | uint64_t src_offset, uint64_t dst_offset, |
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727 | 727 | unsigned num_gpu_pages, |
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728 | | - struct reservation_object *resv); |
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| 728 | + struct dma_resv *resv); |
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729 | 729 | |
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730 | 730 | void si_dma_vm_copy_pages(struct radeon_device *rdev, |
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731 | 731 | struct radeon_ib *ib, |
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.. | .. |
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796 | 796 | struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, |
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797 | 797 | uint64_t src_offset, uint64_t dst_offset, |
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798 | 798 | unsigned num_gpu_pages, |
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799 | | - struct reservation_object *resv); |
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| 799 | + struct dma_resv *resv); |
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800 | 800 | struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev, |
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801 | 801 | uint64_t src_offset, uint64_t dst_offset, |
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802 | 802 | unsigned num_gpu_pages, |
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803 | | - struct reservation_object *resv); |
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| 803 | + struct dma_resv *resv); |
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804 | 804 | int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
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805 | 805 | int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
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806 | 806 | bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
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