~hc/RK356X_SDK_RELEASE.git

..	..	@@ -26,23 +26,36 @@
26	26	#include "core.h"
27	27	#include "head.h"
28	28	#include "wndw.h"
	29	+#include "handles.h"
29	30
30	31	#include <linux/dma-mapping.h>
31	32	#include <linux/hdmi.h>
	33	+#include <linux/component.h>
32	34
33		-#include <drm/drmP.h>
34	35	#include <drm/drm_atomic_helper.h>
35		-#include <drm/drm_crtc_helper.h>
36	36	#include <drm/drm_dp_helper.h>
	37	+#include <drm/drm_edid.h>
37	38	#include <drm/drm_fb_helper.h>
38	39	#include <drm/drm_plane_helper.h>
39		-#include <drm/drm_edid.h>
	40	+#include <drm/drm_probe_helper.h>
	41	+#include <drm/drm_scdc_helper.h>
	42	+#include <drm/drm_vblank.h>
	43	+
	44	+#include <nvif/push507c.h>
40	45
41	46	#include <nvif/class.h>
42	47	#include <nvif/cl0002.h>
43	48	#include <nvif/cl5070.h>
44	49	#include <nvif/cl507d.h>
45	50	#include <nvif/event.h>
	51	+#include <nvif/timer.h>
	52	+
	53	+#include <nvhw/class/cl507c.h>
	54	+#include <nvhw/class/cl507d.h>
	55	+#include <nvhw/class/cl837d.h>
	56	+#include <nvhw/class/cl887d.h>
	57	+#include <nvhw/class/cl907d.h>
	58	+#include <nvhw/class/cl917d.h>
46	59
47	60	#include "nouveau_drv.h"
48	61	#include "nouveau_dma.h"
..	..	@@ -53,24 +66,6 @@
53	66	#include "nouveau_fbcon.h"
54	67
55	68	#include <subdev/bios/dp.h>
56		-
57		-/******************************************************************************
58		- * Atomic state
59		- *****************************************************************************/
60		-
61		-struct nv50_outp_atom {
62		- struct list_head head;
63		-
64		- struct drm_encoder *encoder;
65		- bool flush_disable;
66		-
67		- union nv50_outp_atom_mask {
68		- struct {
69		- bool ctrl:1;
70		- };
71		- u8 mask;
72		- } set, clr;
73		-};
74	69
75	70	/******************************************************************************
76	71	* EVO channel
..	..	@@ -93,8 +88,9 @@
93	88	while (oclass[0]) {
94	89	for (i = 0; i < n; i++) {
95	90	if (sclass[i].oclass == oclass[0]) {
96		- ret = nvif_object_init(disp, 0, oclass[0],
97		- data, size, &chan->user);
	91	+ ret = nvif_object_ctor(disp, "kmsChan", 0,
	92	+ oclass[0], data, size,
	93	+ &chan->user);
98	94	if (ret == 0)
99	95	nvif_object_map(&chan->user, NULL, 0);
100	96	nvif_object_sclass_put(&sclass);
..	..	@@ -111,7 +107,7 @@
111	107	static void
112	108	nv50_chan_destroy(struct nv50_chan *chan)
113	109	{
114		- nvif_object_fini(&chan->user);
	110	+ nvif_object_dtor(&chan->user);
115	111	}
116	112
117	113	/******************************************************************************
..	..	@@ -121,12 +117,106 @@
121	117	void
122	118	nv50_dmac_destroy(struct nv50_dmac *dmac)
123	119	{
124		- nvif_object_fini(&dmac->vram);
125		- nvif_object_fini(&dmac->sync);
	120	+ nvif_object_dtor(&dmac->vram);
	121	+ nvif_object_dtor(&dmac->sync);
126	122
127	123	nv50_chan_destroy(&dmac->base);
128	124
129		- nvif_mem_fini(&dmac->push);
	125	+ nvif_mem_dtor(&dmac->_push.mem);
	126	+}
	127	+
	128	+static void
	129	+nv50_dmac_kick(struct nvif_push *push)
	130	+{
	131	+ struct nv50_dmac dmac = container_of(push, typeof(dmac), _push);
	132	+
	133	+ dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
	134	+ if (dmac->put != dmac->cur) {
	135	+ /* Push buffer fetches are not coherent with BAR1, we need to ensure
	136	+ * writes have been flushed right through to VRAM before writing PUT.
	137	+ */
	138	+ if (dmac->push->mem.type & NVIF_MEM_VRAM) {
	139	+ struct nvif_device *device = dmac->base.device;
	140	+ nvif_wr32(&device->object, 0x070000, 0x00000001);
	141	+ nvif_msec(device, 2000,
	142	+ if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
	143	+ break;
	144	+ );
	145	+ }
	146	+
	147	+ NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
	148	+ dmac->put = dmac->cur;
	149	+ }
	150	+
	151	+ push->bgn = push->cur;
	152	+}
	153	+
	154	+static int
	155	+nv50_dmac_free(struct nv50_dmac *dmac)
	156	+{
	157	+ u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
	158	+ if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
	159	+ return get - dmac->cur - 5;
	160	+ return dmac->max - dmac->cur;
	161	+}
	162	+
	163	+static int
	164	+nv50_dmac_wind(struct nv50_dmac *dmac)
	165	+{
	166	+ /* Wait for GET to depart from the beginning of the push buffer to
	167	+ * prevent writing PUT == GET, which would be ignored by HW.
	168	+ */
	169	+ u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
	170	+ if (get == 0) {
	171	+ /* Corner-case, HW idle, but non-committed work pending. */
	172	+ if (dmac->put == 0)
	173	+ nv50_dmac_kick(dmac->push);
	174	+
	175	+ if (nvif_msec(dmac->base.device, 2000,
	176	+ if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
	177	+ break;
	178	+ ) < 0)
	179	+ return -ETIMEDOUT;
	180	+ }
	181	+
	182	+ PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
	183	+ dmac->cur = 0;
	184	+ return 0;
	185	+}
	186	+
	187	+static int
	188	+nv50_dmac_wait(struct nvif_push *push, u32 size)
	189	+{
	190	+ struct nv50_dmac dmac = container_of(push, typeof(dmac), _push);
	191	+ int free;
	192	+
	193	+ if (WARN_ON(size > dmac->max))
	194	+ return -EINVAL;
	195	+
	196	+ dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
	197	+ if (dmac->cur + size >= dmac->max) {
	198	+ int ret = nv50_dmac_wind(dmac);
	199	+ if (ret)
	200	+ return ret;
	201	+
	202	+ push->cur = dmac->_push.mem.object.map.ptr;
	203	+ push->cur = push->cur + dmac->cur;
	204	+ nv50_dmac_kick(push);
	205	+ }
	206	+
	207	+ if (nvif_msec(dmac->base.device, 2000,
	208	+ if ((free = nv50_dmac_free(dmac)) >= size)
	209	+ break;
	210	+ ) < 0) {
	211	+ WARN_ON(1);
	212	+ return -ETIMEDOUT;
	213	+ }
	214	+
	215	+ push->bgn = dmac->_push.mem.object.map.ptr;
	216	+ push->bgn = push->bgn + dmac->cur;
	217	+ push->cur = push->bgn;
	218	+ push->end = push->cur + free;
	219	+ return 0;
130	220	}
131	221
132	222	int
..	..	@@ -153,13 +243,27 @@
153	243	if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
154	244	type \|= NVIF_MEM_VRAM;
155	245
156		- ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
	246	+ ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
	247	+ &dmac->_push.mem);
157	248	if (ret)
158	249	return ret;
159	250
160		- dmac->ptr = dmac->push.object.map.ptr;
	251	+ dmac->ptr = dmac->_push.mem.object.map.ptr;
	252	+ dmac->_push.wait = nv50_dmac_wait;
	253	+ dmac->_push.kick = nv50_dmac_kick;
	254	+ dmac->push = &dmac->_push;
	255	+ dmac->push->bgn = dmac->_push.mem.object.map.ptr;
	256	+ dmac->push->cur = dmac->push->bgn;
	257	+ dmac->push->end = dmac->push->bgn;
	258	+ dmac->max = 0x1000/4 - 1;
161	259
162		- args->pushbuf = nvif_handle(&dmac->push.object);
	260	+ /* EVO channels are affected by a HW bug where the last 12 DWORDs
	261	+ * of the push buffer aren't able to be used safely.
	262	+ */
	263	+ if (disp->oclass < GV100_DISP)
	264	+ dmac->max -= 12;
	265	+
	266	+ args->pushbuf = nvif_handle(&dmac->_push.mem.object);
163	267
164	268	ret = nv50_chan_create(device, disp, oclass, head, data, size,
165	269	&dmac->base);
..	..	@@ -169,7 +273,8 @@
169	273	if (syncbuf < 0)
170	274	return 0;
171	275
172		- ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
	276	+ ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
	277	+ NV_DMA_IN_MEMORY,
173	278	&(struct nv_dma_v0) {
174	279	.target = NV_DMA_V0_TARGET_VRAM,
175	280	.access = NV_DMA_V0_ACCESS_RDWR,
..	..	@@ -180,7 +285,8 @@
180	285	if (ret)
181	286	return ret;
182	287
183		- ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
	288	+ ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
	289	+ NV_DMA_IN_MEMORY,
184	290	&(struct nv_dma_v0) {
185	291	.target = NV_DMA_V0_TARGET_VRAM,
186	292	.access = NV_DMA_V0_ACCESS_RDWR,
..	..	@@ -192,64 +298,6 @@
192	298	return ret;
193	299
194	300	return ret;
195		-}
196		-
197		-/******************************************************************************
198		- * EVO channel helpers
199		- *****************************************************************************/
200		-static void
201		-evo_flush(struct nv50_dmac *dmac)
202		-{
203		- /* Push buffer fetches are not coherent with BAR1, we need to ensure
204		- * writes have been flushed right through to VRAM before writing PUT.
205		- */
206		- if (dmac->push.type & NVIF_MEM_VRAM) {
207		- struct nvif_device *device = dmac->base.device;
208		- nvif_wr32(&device->object, 0x070000, 0x00000001);
209		- nvif_msec(device, 2000,
210		- if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
211		- break;
212		- );
213		- }
214		-}
215		-
216		-u32 *
217		-evo_wait(struct nv50_dmac *evoc, int nr)
218		-{
219		- struct nv50_dmac *dmac = evoc;
220		- struct nvif_device *device = dmac->base.device;
221		- u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
222		-
223		- mutex_lock(&dmac->lock);
224		- if (put + nr >= (PAGE_SIZE / 4) - 8) {
225		- dmac->ptr[put] = 0x20000000;
226		- evo_flush(dmac);
227		-
228		- nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
229		- if (nvif_msec(device, 2000,
230		- if (!nvif_rd32(&dmac->base.user, 0x0004))
231		- break;
232		- ) < 0) {
233		- mutex_unlock(&dmac->lock);
234		- pr_err("nouveau: evo channel stalled\n");
235		- return NULL;
236		- }
237		-
238		- put = 0;
239		- }
240		-
241		- return dmac->ptr + put;
242		-}
243		-
244		-void
245		-evo_kick(u32 push, struct nv50_dmac evoc)
246		-{
247		- struct nv50_dmac *dmac = evoc;
248		-
249		- evo_flush(dmac);
250		-
251		- nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
252		- mutex_unlock(&dmac->lock);
253	301	}
254	302
255	303	/******************************************************************************
..	..	@@ -274,7 +322,7 @@
274	322	}
275	323
276	324	static int
277		-nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
	325	+nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
278	326	{
279	327	struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
280	328	struct nv50_disp *disp = nv50_disp(drm->dev);
..	..	@@ -286,6 +334,7 @@
286	334	.base.method = NV50_DISP_MTHD_V1_ACQUIRE,
287	335	.base.hasht = nv_encoder->dcb->hasht,
288	336	.base.hashm = nv_encoder->dcb->hashm,
	337	+ .info.hda = hda,
289	338	};
290	339	int ret;
291	340
..	..	@@ -321,8 +370,13 @@
321	370	switch (connector->connector_type) {
322	371	case DRM_MODE_CONNECTOR_LVDS:
323	372	case DRM_MODE_CONNECTOR_eDP:
324		- /* Force use of scaler for non-EDID modes. */
325		- if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
	373	+ /* Don't force scaler for EDID modes with
	374	+ * same size as the native one (e.g. different
	375	+ * refresh rate)
	376	+ */
	377	+ if (mode->hdisplay == native_mode->hdisplay &&
	378	+ mode->vdisplay == native_mode->vdisplay &&
	379	+ mode->type & DRM_MODE_TYPE_DRIVER)
326	380	break;
327	381	mode = native_mode;
328	382	asyc->scaler.full = true;
..	..	@@ -347,37 +401,95 @@
347	401	struct drm_crtc_state *crtc_state,
348	402	struct drm_connector_state *conn_state)
349	403	{
350		- struct nouveau_connector *nv_connector =
351		- nouveau_connector(conn_state->connector);
352		- return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
353		- nv_connector->native_mode);
	404	+ struct drm_connector *connector = conn_state->connector;
	405	+ struct nouveau_connector *nv_connector = nouveau_connector(connector);
	406	+ struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
	407	+ int ret;
	408	+
	409	+ ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
	410	+ nv_connector->native_mode);
	411	+ if (ret)
	412	+ return ret;
	413	+
	414	+ if (crtc_state->mode_changed \|\| crtc_state->connectors_changed)
	415	+ asyh->or.bpc = connector->display_info.bpc;
	416	+
	417	+ return 0;
	418	+}
	419	+
	420	+struct nouveau_connector *
	421	+nv50_outp_get_new_connector(struct nouveau_encoder *outp,
	422	+ struct drm_atomic_state *state)
	423	+{
	424	+ struct drm_connector *connector;
	425	+ struct drm_connector_state *connector_state;
	426	+ struct drm_encoder *encoder = to_drm_encoder(outp);
	427	+ int i;
	428	+
	429	+ for_each_new_connector_in_state(state, connector, connector_state, i) {
	430	+ if (connector_state->best_encoder == encoder)
	431	+ return nouveau_connector(connector);
	432	+ }
	433	+
	434	+ return NULL;
	435	+}
	436	+
	437	+struct nouveau_connector *
	438	+nv50_outp_get_old_connector(struct nouveau_encoder *outp,
	439	+ struct drm_atomic_state *state)
	440	+{
	441	+ struct drm_connector *connector;
	442	+ struct drm_connector_state *connector_state;
	443	+ struct drm_encoder *encoder = to_drm_encoder(outp);
	444	+ int i;
	445	+
	446	+ for_each_old_connector_in_state(state, connector, connector_state, i) {
	447	+ if (connector_state->best_encoder == encoder)
	448	+ return nouveau_connector(connector);
	449	+ }
	450	+
	451	+ return NULL;
354	452	}
355	453
356	454	/******************************************************************************
357	455	* DAC
358	456	*****************************************************************************/
359	457	static void
360		-nv50_dac_disable(struct drm_encoder *encoder)
	458	+nv50_dac_disable(struct drm_encoder encoder, struct drm_atomic_state state)
361	459	{
362	460	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
363	461	struct nv50_core *core = nv50_disp(encoder->dev)->core;
	462	+ const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
364	463	if (nv_encoder->crtc)
365		- core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
	464	+ core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
366	465	nv_encoder->crtc = NULL;
367	466	nv50_outp_release(nv_encoder);
368	467	}
369	468
370	469	static void
371		-nv50_dac_enable(struct drm_encoder *encoder)
	470	+nv50_dac_enable(struct drm_encoder encoder, struct drm_atomic_state state)
372	471	{
373	472	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
374	473	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
375	474	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
376	475	struct nv50_core *core = nv50_disp(encoder->dev)->core;
	476	+ u32 ctrl = 0;
377	477
378		- nv50_outp_acquire(nv_encoder);
	478	+ switch (nv_crtc->index) {
	479	+ case 0: ctrl \|= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
	480	+ case 1: ctrl \|= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
	481	+ case 2: ctrl \|= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
	482	+ case 3: ctrl \|= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
	483	+ default:
	484	+ WARN_ON(1);
	485	+ break;
	486	+ }
379	487
380		- core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
	488	+ ctrl \|= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
	489	+
	490	+ nv50_outp_acquire(nv_encoder, false);
	491	+
	492	+ core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
381	493	asyh->or.depth = 0;
382	494
383	495	nv_encoder->crtc = encoder->crtc;
..	..	@@ -413,8 +525,8 @@
413	525	static const struct drm_encoder_helper_funcs
414	526	nv50_dac_help = {
415	527	.atomic_check = nv50_outp_atomic_check,
416		- .enable = nv50_dac_enable,
417		- .disable = nv50_dac_disable,
	528	+ .atomic_enable = nv50_dac_enable,
	529	+ .atomic_disable = nv50_dac_disable,
418	530	.detect = nv50_dac_detect
419	531	};
420	532
..	..	@@ -460,12 +572,131 @@
460	572	return 0;
461	573	}
462	574
	575	+/*
	576	+ * audio component binding for ELD notification
	577	+ */
	578	+static void
	579	+nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
	580	+ int dev_id)
	581	+{
	582	+ if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
	583	+ acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
	584	+ port, dev_id);
	585	+}
	586	+
	587	+static int
	588	+nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
	589	+ bool enabled, unsigned char buf, int max_bytes)
	590	+{
	591	+ struct drm_device *drm_dev = dev_get_drvdata(kdev);
	592	+ struct nouveau_drm *drm = nouveau_drm(drm_dev);
	593	+ struct drm_encoder *encoder;
	594	+ struct nouveau_encoder *nv_encoder;
	595	+ struct drm_connector *connector;
	596	+ struct nouveau_crtc *nv_crtc;
	597	+ struct drm_connector_list_iter conn_iter;
	598	+ int ret = 0;
	599	+
	600	+ *enabled = false;
	601	+
	602	+ drm_for_each_encoder(encoder, drm->dev) {
	603	+ struct nouveau_connector *nv_connector = NULL;
	604	+
	605	+ nv_encoder = nouveau_encoder(encoder);
	606	+
	607	+ drm_connector_list_iter_begin(drm_dev, &conn_iter);
	608	+ drm_for_each_connector_iter(connector, &conn_iter) {
	609	+ if (connector->state->best_encoder == encoder) {
	610	+ nv_connector = nouveau_connector(connector);
	611	+ break;
	612	+ }
	613	+ }
	614	+ drm_connector_list_iter_end(&conn_iter);
	615	+ if (!nv_connector)
	616	+ continue;
	617	+
	618	+ nv_crtc = nouveau_crtc(encoder->crtc);
	619	+ if (!nv_crtc \|\| nv_encoder->or != port \|\|
	620	+ nv_crtc->index != dev_id)
	621	+ continue;
	622	+ *enabled = nv_encoder->audio;
	623	+ if (*enabled) {
	624	+ ret = drm_eld_size(nv_connector->base.eld);
	625	+ memcpy(buf, nv_connector->base.eld,
	626	+ min(max_bytes, ret));
	627	+ }
	628	+ break;
	629	+ }
	630	+
	631	+ return ret;
	632	+}
	633	+
	634	+static const struct drm_audio_component_ops nv50_audio_component_ops = {
	635	+ .get_eld = nv50_audio_component_get_eld,
	636	+};
	637	+
	638	+static int
	639	+nv50_audio_component_bind(struct device kdev, struct device hda_kdev,
	640	+ void *data)
	641	+{
	642	+ struct drm_device *drm_dev = dev_get_drvdata(kdev);
	643	+ struct nouveau_drm *drm = nouveau_drm(drm_dev);
	644	+ struct drm_audio_component *acomp = data;
	645	+
	646	+ if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
	647	+ return -ENOMEM;
	648	+
	649	+ drm_modeset_lock_all(drm_dev);
	650	+ acomp->ops = &nv50_audio_component_ops;
	651	+ acomp->dev = kdev;
	652	+ drm->audio.component = acomp;
	653	+ drm_modeset_unlock_all(drm_dev);
	654	+ return 0;
	655	+}
	656	+
	657	+static void
	658	+nv50_audio_component_unbind(struct device kdev, struct device hda_kdev,
	659	+ void *data)
	660	+{
	661	+ struct drm_device *drm_dev = dev_get_drvdata(kdev);
	662	+ struct nouveau_drm *drm = nouveau_drm(drm_dev);
	663	+ struct drm_audio_component *acomp = data;
	664	+
	665	+ drm_modeset_lock_all(drm_dev);
	666	+ drm->audio.component = NULL;
	667	+ acomp->ops = NULL;
	668	+ acomp->dev = NULL;
	669	+ drm_modeset_unlock_all(drm_dev);
	670	+}
	671	+
	672	+static const struct component_ops nv50_audio_component_bind_ops = {
	673	+ .bind = nv50_audio_component_bind,
	674	+ .unbind = nv50_audio_component_unbind,
	675	+};
	676	+
	677	+static void
	678	+nv50_audio_component_init(struct nouveau_drm *drm)
	679	+{
	680	+ if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
	681	+ drm->audio.component_registered = true;
	682	+}
	683	+
	684	+static void
	685	+nv50_audio_component_fini(struct nouveau_drm *drm)
	686	+{
	687	+ if (drm->audio.component_registered) {
	688	+ component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
	689	+ drm->audio.component_registered = false;
	690	+ }
	691	+}
	692	+
463	693	/******************************************************************************
464	694	* Audio
465	695	*****************************************************************************/
466	696	static void
467	697	nv50_audio_disable(struct drm_encoder encoder, struct nouveau_crtc nv_crtc)
468	698	{
	699	+ struct nouveau_drm *drm = nouveau_drm(encoder->dev);
469	700	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
470	701	struct nv50_disp *disp = nv50_disp(encoder->dev);
471	702	struct {
..	..	@@ -479,12 +710,21 @@
479	710	(0x0100 << nv_crtc->index),
480	711	};
481	712
	713	+ if (!nv_encoder->audio)
	714	+ return;
	715	+
	716	+ nv_encoder->audio = false;
482	717	nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
	718	+
	719	+ nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
	720	+ nv_crtc->index);
483	721	}
484	722
485	723	static void
486		-nv50_audio_enable(struct drm_encoder encoder, struct drm_display_mode mode)
	724	+nv50_audio_enable(struct drm_encoder encoder, struct drm_atomic_state state,
	725	+ struct drm_display_mode *mode)
487	726	{
	727	+ struct nouveau_drm *drm = nouveau_drm(encoder->dev);
488	728	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
489	729	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
490	730	struct nouveau_connector *nv_connector;
..	..	@@ -503,7 +743,7 @@
503	743	(0x0100 << nv_crtc->index),
504	744	};
505	745
506		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
	746	+ nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
507	747	if (!drm_detect_monitor_audio(nv_connector->edid))
508	748	return;
509	749
..	..	@@ -511,6 +751,10 @@
511	751
512	752	nvif_mthd(&disp->disp->object, 0, &args,
513	753	sizeof(args.base) + drm_eld_size(args.data));
	754	+ nv_encoder->audio = true;
	755	+
	756	+ nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
	757	+ nv_crtc->index);
514	758	}
515	759
516	760	/******************************************************************************
..	..	@@ -536,8 +780,10 @@
536	780	}
537	781
538	782	static void
539		-nv50_hdmi_enable(struct drm_encoder encoder, struct drm_display_mode mode)
	783	+nv50_hdmi_enable(struct drm_encoder encoder, struct drm_atomic_state state,
	784	+ struct drm_display_mode *mode)
540	785	{
	786	+ struct nouveau_drm *drm = nouveau_drm(encoder->dev);
541	787	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
542	788	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
543	789	struct nv50_disp *disp = nv50_disp(encoder->dev);
..	..	@@ -555,18 +801,23 @@
555	801	.pwr.rekey = 56, /* binary driver, and tegra, constant */
556	802	};
557	803	struct nouveau_connector *nv_connector;
	804	+ struct drm_hdmi_info *hdmi;
558	805	u32 max_ac_packet;
559	806	union hdmi_infoframe avi_frame;
560	807	union hdmi_infoframe vendor_frame;
	808	+ bool high_tmds_clock_ratio = false, scrambling = false;
	809	+ u8 config;
561	810	int ret;
562	811	int size;
563	812
564		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
	813	+ nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
565	814	if (!drm_detect_hdmi_monitor(nv_connector->edid))
566	815	return;
567	816
568		- ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
569		- false);
	817	+ hdmi = &nv_connector->base.display_info.hdmi;
	818	+
	819	+ ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
	820	+ &nv_connector->base, mode);
570	821	if (!ret) {
571	822	/* We have an AVI InfoFrame, populate it to the display */
572	823	args.pwr.avi_infoframe_length
..	..	@@ -589,12 +840,42 @@
589	840	max_ac_packet -= 18; /* constant from tegra */
590	841	args.pwr.max_ac_packet = max_ac_packet / 32;
591	842
	843	+ if (hdmi->scdc.scrambling.supported) {
	844	+ high_tmds_clock_ratio = mode->clock > 340000;
	845	+ scrambling = high_tmds_clock_ratio \|\|
	846	+ hdmi->scdc.scrambling.low_rates;
	847	+ }
	848	+
	849	+ args.pwr.scdc =
	850	+ NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling \|
	851	+ NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
	852	+
592	853	size = sizeof(args.base)
593	854	+ sizeof(args.pwr)
594	855	+ args.pwr.avi_infoframe_length
595	856	+ args.pwr.vendor_infoframe_length;
596	857	nvif_mthd(&disp->disp->object, 0, &args, size);
597		- nv50_audio_enable(encoder, mode);
	858	+
	859	+ nv50_audio_enable(encoder, state, mode);
	860	+
	861	+ /* If SCDC is supported by the downstream monitor, update
	862	+ * divider / scrambling settings to what we programmed above.
	863	+ */
	864	+ if (!hdmi->scdc.scrambling.supported)
	865	+ return;
	866	+
	867	+ ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
	868	+ if (ret < 0) {
	869	+ NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
	870	+ return;
	871	+ }
	872	+ config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 \| SCDC_SCRAMBLING_ENABLE);
	873	+ config \|= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
	874	+ config \|= SCDC_SCRAMBLING_ENABLE * scrambling;
	875	+ ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
	876	+ if (ret < 0)
	877	+ NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
	878	+ config, ret);
598	879	}
599	880
600	881	/******************************************************************************
..	..	@@ -604,17 +885,6 @@
604	885	#define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
605	886	#define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
606	887
607		-struct nv50_mstm {
608		- struct nouveau_encoder *outp;
609		-
610		- struct drm_dp_mst_topology_mgr mgr;
611		- struct nv50_msto *msto[4];
612		-
613		- bool modified;
614		- bool disabled;
615		- int links;
616		-};
617		-
618	888	struct nv50_mstc {
619	889	struct nv50_mstm *mstm;
620	890	struct drm_dp_mst_port *port;
..	..	@@ -622,8 +892,6 @@
622	892
623	893	struct drm_display_mode *native;
624	894	struct edid *edid;
625		-
626		- int pbn;
627	895	};
628	896
629	897	struct nv50_msto {
..	..	@@ -634,6 +902,19 @@
634	902	bool disabled;
635	903	};
636	904
	905	+struct nouveau_encoder nv50_real_outp(struct drm_encoder encoder)
	906	+{
	907	+ struct nv50_msto *msto;
	908	+
	909	+ if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
	910	+ return nouveau_encoder(encoder);
	911	+
	912	+ msto = nv50_msto(encoder);
	913	+ if (!msto->mstc)
	914	+ return NULL;
	915	+ return msto->mstc->mstm->outp;
	916	+}
	917	+
637	918	static struct drm_dp_payload *
638	919	nv50_msto_payload(struct nv50_msto *msto)
639	920	{
..	..	@@ -641,6 +922,8 @@
641	922	struct nv50_mstc *mstc = msto->mstc;
642	923	struct nv50_mstm *mstm = mstc->mstm;
643	924	int vcpi = mstc->port->vcpi.vcpi, i;
	925	+
	926	+ WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
644	927
645	928	NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
646	929	for (i = 0; i < mstm->mgr.max_payloads; i++) {
..	..	@@ -666,14 +949,15 @@
666	949	struct nv50_mstc *mstc = msto->mstc;
667	950	struct nv50_mstm *mstm = mstc->mstm;
668	951
	952	+ if (!msto->disabled)
	953	+ return;
	954	+
669	955	NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
670		- if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
671		- drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
672		- if (msto->disabled) {
673		- msto->mstc = NULL;
674		- msto->head = NULL;
675		- msto->disabled = false;
676		- }
	956	+
	957	+ drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
	958	+
	959	+ msto->mstc = NULL;
	960	+ msto->disabled = false;
677	961	}
678	962
679	963	static void
..	..	@@ -693,8 +977,10 @@
693	977	(0x0100 << msto->head->base.index),
694	978	};
695	979
	980	+ mutex_lock(&mstm->mgr.payload_lock);
	981	+
696	982	NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
697		- if (mstc->port && mstc->port->vcpi.vcpi > 0) {
	983	+ if (mstc->port->vcpi.vcpi > 0) {
698	984	struct drm_dp_payload *payload = nv50_msto_payload(msto);
699	985	if (payload) {
700	986	args.vcpi.start_slot = payload->start_slot;
..	..	@@ -708,7 +994,9 @@
708	994	msto->encoder.name, msto->head->base.base.name,
709	995	args.vcpi.start_slot, args.vcpi.num_slots,
710	996	args.vcpi.pbn, args.vcpi.aligned_pbn);
	997	+
711	998	nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
	999	+ mutex_unlock(&mstm->mgr.payload_lock);
712	1000	}
713	1001
714	1002	static int
..	..	@@ -716,32 +1004,67 @@
716	1004	struct drm_crtc_state *crtc_state,
717	1005	struct drm_connector_state *conn_state)
718	1006	{
719		- struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
	1007	+ struct drm_atomic_state *state = crtc_state->state;
	1008	+ struct drm_connector *connector = conn_state->connector;
	1009	+ struct nv50_mstc *mstc = nv50_mstc(connector);
720	1010	struct nv50_mstm *mstm = mstc->mstm;
721		- int bpp = conn_state->connector->display_info.bpc * 3;
	1011	+ struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
722	1012	int slots;
	1013	+ int ret;
723	1014
724		- mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
	1015	+ ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
	1016	+ mstc->native);
	1017	+ if (ret)
	1018	+ return ret;
725	1019
726		- slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
	1020	+ if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
	1021	+ return 0;
	1022	+
	1023	+ /*
	1024	+ * When restoring duplicated states, we need to make sure that the bw
	1025	+ * remains the same and avoid recalculating it, as the connector's bpc
	1026	+ * may have changed after the state was duplicated
	1027	+ */
	1028	+ if (!state->duplicated) {
	1029	+ const int clock = crtc_state->adjusted_mode.clock;
	1030	+
	1031	+ asyh->or.bpc = connector->display_info.bpc;
	1032	+ asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
	1033	+ false);
	1034	+ }
	1035	+
	1036	+ slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
	1037	+ asyh->dp.pbn, 0);
727	1038	if (slots < 0)
728	1039	return slots;
729	1040
730		- return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
731		- mstc->native);
	1041	+ asyh->dp.tu = slots;
	1042	+
	1043	+ return 0;
	1044	+}
	1045	+
	1046	+static u8
	1047	+nv50_dp_bpc_to_depth(unsigned int bpc)
	1048	+{
	1049	+ switch (bpc) {
	1050	+ case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
	1051	+ case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
	1052	+ case 10:
	1053	+ default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
	1054	+ }
732	1055	}
733	1056
734	1057	static void
735		-nv50_msto_enable(struct drm_encoder *encoder)
	1058	+nv50_msto_enable(struct drm_encoder encoder, struct drm_atomic_state state)
736	1059	{
737	1060	struct nv50_head *head = nv50_head(encoder->crtc);
	1061	+ struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
738	1062	struct nv50_msto *msto = nv50_msto(encoder);
739	1063	struct nv50_mstc *mstc = NULL;
740	1064	struct nv50_mstm *mstm = NULL;
741	1065	struct drm_connector *connector;
742	1066	struct drm_connector_list_iter conn_iter;
743		- u8 proto, depth;
744		- int slots;
	1067	+ u8 proto;
745	1068	bool r;
746	1069
747	1070	drm_connector_list_iter_begin(encoder->dev, &conn_iter);
..	..	@@ -757,43 +1080,34 @@
757	1080	if (WARN_ON(!mstc))
758	1081	return;
759	1082
760		- slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
761		- r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
	1083	+ r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
	1084	+ armh->dp.tu);
762	1085	if (!r)
763	1086	DRM_DEBUG_KMS("Failed to allocate VCPI\n");
764	1087
765	1088	if (!mstm->links++)
766		- nv50_outp_acquire(mstm->outp);
	1089	+ nv50_outp_acquire(mstm->outp, false /XXX: MST audio./);
767	1090
768	1091	if (mstm->outp->link & 1)
769		- proto = 0x8;
	1092	+ proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
770	1093	else
771		- proto = 0x9;
	1094	+ proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
772	1095
773		- switch (mstc->connector.display_info.bpc) {
774		- case 6: depth = 0x2; break;
775		- case 8: depth = 0x5; break;
776		- case 10:
777		- default: depth = 0x6; break;
778		- }
	1096	+ mstm->outp->update(mstm->outp, head->base.index, armh, proto,
	1097	+ nv50_dp_bpc_to_depth(armh->or.bpc));
779	1098
780		- mstm->outp->update(mstm->outp, head->base.index,
781		- nv50_head_atom(head->base.base.state), proto, depth);
782		-
783		- msto->head = head;
784	1099	msto->mstc = mstc;
785	1100	mstm->modified = true;
786	1101	}
787	1102
788	1103	static void
789		-nv50_msto_disable(struct drm_encoder *encoder)
	1104	+nv50_msto_disable(struct drm_encoder encoder, struct drm_atomic_state state)
790	1105	{
791	1106	struct nv50_msto *msto = nv50_msto(encoder);
792	1107	struct nv50_mstc *mstc = msto->mstc;
793	1108	struct nv50_mstm *mstm = mstc->mstm;
794	1109
795		- if (mstc->port)
796		- drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
	1110	+ drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
797	1111
798	1112	mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
799	1113	mstm->modified = true;
..	..	@@ -804,8 +1118,8 @@
804	1118
805	1119	static const struct drm_encoder_helper_funcs
806	1120	nv50_msto_help = {
807		- .disable = nv50_msto_disable,
808		- .enable = nv50_msto_enable,
	1121	+ .atomic_disable = nv50_msto_disable,
	1122	+ .atomic_enable = nv50_msto_enable,
809	1123	.atomic_check = nv50_msto_atomic_check,
810	1124	};
811	1125
..	..	@@ -822,52 +1136,54 @@
822	1136	.destroy = nv50_msto_destroy,
823	1137	};
824	1138
825		-static int
826		-nv50_msto_new(struct drm_device dev, u32 heads, const char name, int id,
827		- struct nv50_msto **pmsto)
	1139	+static struct nv50_msto *
	1140	+nv50_msto_new(struct drm_device dev, struct nv50_head head, int id)
828	1141	{
829	1142	struct nv50_msto *msto;
830	1143	int ret;
831	1144
832		- if (!(msto = pmsto = kzalloc(sizeof(msto), GFP_KERNEL)))
833		- return -ENOMEM;
	1145	+ msto = kzalloc(sizeof(*msto), GFP_KERNEL);
	1146	+ if (!msto)
	1147	+ return ERR_PTR(-ENOMEM);
834	1148
835	1149	ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
836		- DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
	1150	+ DRM_MODE_ENCODER_DPMST, "mst-%d", id);
837	1151	if (ret) {
838		- kfree(*pmsto);
839		- *pmsto = NULL;
840		- return ret;
	1152	+ kfree(msto);
	1153	+ return ERR_PTR(ret);
841	1154	}
842	1155
843	1156	drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
844		- msto->encoder.possible_crtcs = heads;
845		- return 0;
	1157	+ msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
	1158	+ msto->head = head;
	1159	+ return msto;
846	1160	}
847	1161
848	1162	static struct drm_encoder *
849	1163	nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
850	1164	struct drm_connector_state *connector_state)
851	1165	{
852		- struct nv50_head *head = nv50_head(connector_state->crtc);
853	1166	struct nv50_mstc *mstc = nv50_mstc(connector);
	1167	+ struct drm_crtc *crtc = connector_state->crtc;
854	1168
855		- return &mstc->mstm->msto[head->base.index]->encoder;
856		-}
	1169	+ if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
	1170	+ return NULL;
857	1171
858		-static struct drm_encoder *
859		-nv50_mstc_best_encoder(struct drm_connector *connector)
860		-{
861		- struct nv50_mstc *mstc = nv50_mstc(connector);
862		-
863		- return &mstc->mstm->msto[0]->encoder;
	1172	+ return &nv50_head(crtc)->msto->encoder;
864	1173	}
865	1174
866	1175	static enum drm_mode_status
867	1176	nv50_mstc_mode_valid(struct drm_connector *connector,
868	1177	struct drm_display_mode *mode)
869	1178	{
870		- return MODE_OK;
	1179	+ struct nv50_mstc *mstc = nv50_mstc(connector);
	1180	+ struct nouveau_encoder *outp = mstc->mstm->outp;
	1181	+
	1182	+ /* TODO: calculate the PBN from the dotclock and validate against the
	1183	+ * MSTB's max possible PBN
	1184	+ */
	1185	+
	1186	+ return nv50_dp_mode_valid(connector, outp, mode, NULL);
871	1187	}
872	1188
873	1189	static int
..	..	@@ -881,8 +1197,17 @@
881	1197	if (mstc->edid)
882	1198	ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
883	1199
884		- if (!mstc->connector.display_info.bpc)
885		- mstc->connector.display_info.bpc = 8;
	1200	+ /*
	1201	+ * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
	1202	+ * to 8 to save bandwidth on the topology. In the future, we'll want
	1203	+ * to properly fix this by dynamically selecting the highest possible
	1204	+ * bpc that would fit in the topology
	1205	+ */
	1206	+ if (connector->display_info.bpc)
	1207	+ connector->display_info.bpc =
	1208	+ clamp(connector->display_info.bpc, 6U, 8U);
	1209	+ else
	1210	+ connector->display_info.bpc = 8;
886	1211
887	1212	if (mstc->native)
888	1213	drm_mode_destroy(mstc->connector.dev, mstc->native);
..	..	@@ -890,22 +1215,45 @@
890	1215	return ret;
891	1216	}
892	1217
893		-static const struct drm_connector_helper_funcs
894		-nv50_mstc_help = {
895		- .get_modes = nv50_mstc_get_modes,
896		- .mode_valid = nv50_mstc_mode_valid,
897		- .best_encoder = nv50_mstc_best_encoder,
898		- .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
899		-};
900		-
901		-static enum drm_connector_status
902		-nv50_mstc_detect(struct drm_connector *connector, bool force)
	1218	+static int
	1219	+nv50_mstc_atomic_check(struct drm_connector *connector,
	1220	+ struct drm_atomic_state *state)
903	1221	{
904	1222	struct nv50_mstc *mstc = nv50_mstc(connector);
905		- enum drm_connector_status conn_status;
	1223	+ struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
	1224	+ struct drm_connector_state *new_conn_state =
	1225	+ drm_atomic_get_new_connector_state(state, connector);
	1226	+ struct drm_connector_state *old_conn_state =
	1227	+ drm_atomic_get_old_connector_state(state, connector);
	1228	+ struct drm_crtc_state *crtc_state;
	1229	+ struct drm_crtc *new_crtc = new_conn_state->crtc;
	1230	+
	1231	+ if (!old_conn_state->crtc)
	1232	+ return 0;
	1233	+
	1234	+ /* We only want to free VCPI if this state disables the CRTC on this
	1235	+ * connector
	1236	+ */
	1237	+ if (new_crtc) {
	1238	+ crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
	1239	+
	1240	+ if (!crtc_state \|\|
	1241	+ !drm_atomic_crtc_needs_modeset(crtc_state) \|\|
	1242	+ crtc_state->enable)
	1243	+ return 0;
	1244	+ }
	1245	+
	1246	+ return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
	1247	+}
	1248	+
	1249	+static int
	1250	+nv50_mstc_detect(struct drm_connector *connector,
	1251	+ struct drm_modeset_acquire_ctx *ctx, bool force)
	1252	+{
	1253	+ struct nv50_mstc *mstc = nv50_mstc(connector);
906	1254	int ret;
907	1255
908		- if (!mstc->port)
	1256	+ if (drm_connector_is_unregistered(connector))
909	1257	return connector_status_disconnected;
910	1258
911	1259	ret = pm_runtime_get_sync(connector->dev->dev);
..	..	@@ -914,26 +1262,40 @@
914	1262	return connector_status_disconnected;
915	1263	}
916	1264
917		- conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
918		- mstc->port);
	1265	+ ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
	1266	+ mstc->port);
	1267	+ if (ret != connector_status_connected)
	1268	+ goto out;
919	1269
	1270	+out:
920	1271	pm_runtime_mark_last_busy(connector->dev->dev);
921	1272	pm_runtime_put_autosuspend(connector->dev->dev);
922		- return conn_status;
	1273	+ return ret;
923	1274	}
	1275	+
	1276	+static const struct drm_connector_helper_funcs
	1277	+nv50_mstc_help = {
	1278	+ .get_modes = nv50_mstc_get_modes,
	1279	+ .mode_valid = nv50_mstc_mode_valid,
	1280	+ .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
	1281	+ .atomic_check = nv50_mstc_atomic_check,
	1282	+ .detect_ctx = nv50_mstc_detect,
	1283	+};
924	1284
925	1285	static void
926	1286	nv50_mstc_destroy(struct drm_connector *connector)
927	1287	{
928	1288	struct nv50_mstc *mstc = nv50_mstc(connector);
	1289	+
929	1290	drm_connector_cleanup(&mstc->connector);
	1291	+ drm_dp_mst_put_port_malloc(mstc->port);
	1292	+
930	1293	kfree(mstc);
931	1294	}
932	1295
933	1296	static const struct drm_connector_funcs
934	1297	nv50_mstc = {
935	1298	.reset = nouveau_conn_reset,
936		- .detect = nv50_mstc_detect,
937	1299	.fill_modes = drm_helper_probe_single_connector_modes,
938	1300	.destroy = nv50_mstc_destroy,
939	1301	.atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
..	..	@@ -947,8 +1309,9 @@
947	1309	const char path, struct nv50_mstc *pmstc)
948	1310	{
949	1311	struct drm_device *dev = mstm->outp->base.base.dev;
	1312	+ struct drm_crtc *crtc;
950	1313	struct nv50_mstc *mstc;
951		- int ret, i;
	1314	+ int ret;
952	1315
953	1316	if (!(mstc = pmstc = kzalloc(sizeof(mstc), GFP_KERNEL)))
954	1317	return -ENOMEM;
..	..	@@ -968,12 +1331,18 @@
968	1331	mstc->connector.funcs->reset(&mstc->connector);
969	1332	nouveau_conn_attach_properties(&mstc->connector);
970	1333
971		- for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
972		- drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
	1334	+ drm_for_each_crtc(crtc, dev) {
	1335	+ if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
	1336	+ continue;
	1337	+
	1338	+ drm_connector_attach_encoder(&mstc->connector,
	1339	+ &nv50_head(crtc)->msto->encoder);
	1340	+ }
973	1341
974	1342	drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
975	1343	drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
976	1344	drm_connector_set_path_property(&mstc->connector, path);
	1345	+ drm_dp_mst_get_port_malloc(port);
977	1346	return 0;
978	1347	}
979	1348
..	..	@@ -1027,41 +1396,6 @@
1027	1396	}
1028	1397	}
1029	1398
1030		-static void
1031		-nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1032		-{
1033		- struct nv50_mstm *mstm = nv50_mstm(mgr);
1034		- drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1035		-}
1036		-
1037		-static void
1038		-nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1039		- struct drm_connector *connector)
1040		-{
1041		- struct nouveau_drm *drm = nouveau_drm(connector->dev);
1042		- struct nv50_mstc *mstc = nv50_mstc(connector);
1043		-
1044		- drm_connector_unregister(&mstc->connector);
1045		-
1046		- drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1047		-
1048		- drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1049		- mstc->port = NULL;
1050		- drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1051		-
1052		- drm_connector_put(&mstc->connector);
1053		-}
1054		-
1055		-static void
1056		-nv50_mstm_register_connector(struct drm_connector *connector)
1057		-{
1058		- struct nouveau_drm *drm = nouveau_drm(connector->dev);
1059		-
1060		- drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1061		-
1062		- drm_connector_register(connector);
1063		-}
1064		-
1065	1399	static struct drm_connector *
1066	1400	nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1067	1401	struct drm_dp_mst_port port, const char path)
..	..	@@ -1071,11 +1405,8 @@
1071	1405	int ret;
1072	1406
1073	1407	ret = nv50_mstc_new(mstm, port, path, &mstc);
1074		- if (ret) {
1075		- if (mstc)
1076		- mstc->connector.funcs->destroy(&mstc->connector);
	1408	+ if (ret)
1077	1409	return NULL;
1078		- }
1079	1410
1080	1411	return &mstc->connector;
1081	1412	}
..	..	@@ -1083,46 +1414,53 @@
1083	1414	static const struct drm_dp_mst_topology_cbs
1084	1415	nv50_mstm = {
1085	1416	.add_connector = nv50_mstm_add_connector,
1086		- .register_connector = nv50_mstm_register_connector,
1087		- .destroy_connector = nv50_mstm_destroy_connector,
1088		- .hotplug = nv50_mstm_hotplug,
1089	1417	};
1090	1418
1091		-void
1092		-nv50_mstm_service(struct nv50_mstm *mstm)
	1419	+bool
	1420	+nv50_mstm_service(struct nouveau_drm *drm,
	1421	+ struct nouveau_connector *nv_connector,
	1422	+ struct nv50_mstm *mstm)
1093	1423	{
1094		- struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1095		- bool handled = true;
1096		- int ret;
	1424	+ struct drm_dp_aux *aux = &nv_connector->aux;
	1425	+ bool handled = true, ret = true;
	1426	+ int rc;
1097	1427	u8 esi[8] = {};
1098	1428
1099		- if (!aux)
1100		- return;
1101		-
1102	1429	while (handled) {
1103		- ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1104		- if (ret != 8) {
1105		- drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1106		- return;
	1430	+ rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
	1431	+ if (rc != 8) {
	1432	+ ret = false;
	1433	+ break;
1107	1434	}
1108	1435
1109	1436	drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1110	1437	if (!handled)
1111	1438	break;
1112	1439
1113		- drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
	1440	+ rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
	1441	+ 3);
	1442	+ if (rc != 3) {
	1443	+ ret = false;
	1444	+ break;
	1445	+ }
1114	1446	}
	1447	+
	1448	+ if (!ret)
	1449	+ NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
	1450	+ nv_connector->base.name, rc);
	1451	+
	1452	+ return ret;
1115	1453	}
1116	1454
1117	1455	void
1118	1456	nv50_mstm_remove(struct nv50_mstm *mstm)
1119	1457	{
1120		- if (mstm)
1121		- drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
	1458	+ mstm->is_mst = false;
	1459	+ drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1122	1460	}
1123	1461
1124	1462	static int
1125		-nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
	1463	+nv50_mstm_enable(struct nv50_mstm *mstm, int state)
1126	1464	{
1127	1465	struct nouveau_encoder *outp = mstm->outp;
1128	1466	struct {
..	..	@@ -1137,106 +1475,85 @@
1137	1475	};
1138	1476	struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1139	1477	struct nvif_object *disp = &drm->display->disp.object;
1140		- int ret;
1141		-
1142		- if (dpcd >= 0x12) {
1143		- /* Even if we're enabling MST, start with disabling the
1144		- * branching unit to clear any sink-side MST topology state
1145		- * that wasn't set by us
1146		- */
1147		- ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1148		- if (ret < 0)
1149		- return ret;
1150		-
1151		- if (state) {
1152		- /* Now, start initializing */
1153		- ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1154		- DP_MST_EN);
1155		- if (ret < 0)
1156		- return ret;
1157		- }
1158		- }
1159	1478
1160	1479	return nvif_mthd(disp, 0, &args, sizeof(args));
1161	1480	}
1162	1481
1163	1482	int
1164		-nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
	1483	+nv50_mstm_detect(struct nouveau_encoder *outp)
1165	1484	{
	1485	+ struct nv50_mstm *mstm = outp->dp.mstm;
1166	1486	struct drm_dp_aux *aux;
1167	1487	int ret;
1168		- bool old_state, new_state;
1169		- u8 mstm_ctrl;
1170	1488
1171		- if (!mstm)
	1489	+ if (!mstm \|\| !mstm->can_mst)
1172	1490	return 0;
1173	1491
1174		- mutex_lock(&mstm->mgr.lock);
1175		-
1176		- old_state = mstm->mgr.mst_state;
1177		- new_state = old_state;
1178	1492	aux = mstm->mgr.aux;
1179	1493
1180		- if (old_state) {
1181		- /* Just check that the MST hub is still as we expect it */
1182		- ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1183		- if (ret < 0 \|\| !(mstm_ctrl & DP_MST_EN)) {
1184		- DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1185		- new_state = false;
1186		- }
1187		- } else if (dpcd[0] >= 0x12) {
1188		- ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1189		- if (ret < 0)
1190		- goto probe_error;
	1494	+ /* Clear any leftover MST state we didn't set ourselves by first
	1495	+ * disabling MST if it was already enabled
	1496	+ */
	1497	+ ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
	1498	+ if (ret < 0)
	1499	+ return ret;
1191	1500
1192		- if (!(dpcd[1] & DP_MST_CAP))
1193		- dpcd[0] = 0x11;
1194		- else
1195		- new_state = allow;
	1501	+ /* And start enabling */
	1502	+ ret = nv50_mstm_enable(mstm, true);
	1503	+ if (ret)
	1504	+ return ret;
	1505	+
	1506	+ ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
	1507	+ if (ret) {
	1508	+ nv50_mstm_enable(mstm, false);
	1509	+ return ret;
1196	1510	}
1197	1511
1198		- if (new_state == old_state) {
1199		- mutex_unlock(&mstm->mgr.lock);
1200		- return new_state;
1201		- }
1202		-
1203		- ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1204		- if (ret)
1205		- goto probe_error;
1206		-
1207		- mutex_unlock(&mstm->mgr.lock);
1208		-
1209		- ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1210		- if (ret)
1211		- return nv50_mstm_enable(mstm, dpcd[0], 0);
1212		-
1213		- return new_state;
1214		-
1215		-probe_error:
1216		- mutex_unlock(&mstm->mgr.lock);
1217		- return ret;
	1512	+ mstm->is_mst = true;
	1513	+ return 1;
1218	1514	}
1219	1515
1220	1516	static void
1221		-nv50_mstm_fini(struct nv50_mstm *mstm)
	1517	+nv50_mstm_fini(struct nouveau_encoder *outp)
1222	1518	{
1223		- if (mstm && mstm->mgr.mst_state)
	1519	+ struct nv50_mstm *mstm = outp->dp.mstm;
	1520	+
	1521	+ if (!mstm)
	1522	+ return;
	1523	+
	1524	+ /* Don't change the MST state of this connector until we've finished
	1525	+ * resuming, since we can't safely grab hpd_irq_lock in our resume
	1526	+ * path to protect mstm->is_mst without potentially deadlocking
	1527	+ */
	1528	+ mutex_lock(&outp->dp.hpd_irq_lock);
	1529	+ mstm->suspended = true;
	1530	+ mutex_unlock(&outp->dp.hpd_irq_lock);
	1531	+
	1532	+ if (mstm->is_mst)
1224	1533	drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1225	1534	}
1226	1535
1227	1536	static void
1228		-nv50_mstm_init(struct nv50_mstm *mstm)
	1537	+nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1229	1538	{
1230		- int ret;
	1539	+ struct nv50_mstm *mstm = outp->dp.mstm;
	1540	+ int ret = 0;
1231	1541
1232		- if (!mstm \|\| !mstm->mgr.mst_state)
	1542	+ if (!mstm)
1233	1543	return;
1234	1544
1235		- ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1236		- if (ret == -1) {
1237		- drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1238		- drm_kms_helper_hotplug_event(mstm->mgr.dev);
	1545	+ if (mstm->is_mst) {
	1546	+ ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
	1547	+ if (ret == -1)
	1548	+ nv50_mstm_remove(mstm);
1239	1549	}
	1550	+
	1551	+ mutex_lock(&outp->dp.hpd_irq_lock);
	1552	+ mstm->suspended = false;
	1553	+ mutex_unlock(&outp->dp.hpd_irq_lock);
	1554	+
	1555	+ if (ret == -1)
	1556	+ drm_kms_helper_hotplug_event(mstm->mgr.dev);
1240	1557	}
1241	1558
1242	1559	static void
..	..	@@ -1257,18 +1574,7 @@
1257	1574	const int max_payloads = hweight8(outp->dcb->heads);
1258	1575	struct drm_device *dev = outp->base.base.dev;
1259	1576	struct nv50_mstm *mstm;
1260		- int ret, i;
1261		- u8 dpcd;
1262		-
1263		- /* This is a workaround for some monitors not functioning
1264		- * correctly in MST mode on initial module load. I think
1265		- * some bad interaction with the VBIOS may be responsible.
1266		- *
1267		- * A good ol' off and on again seems to work here ;)
1268		- */
1269		- ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1270		- if (ret >= 0 && dpcd >= 0x12)
1271		- drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
	1577	+ int ret;
1272	1578
1273	1579	if (!(mstm = pmstm = kzalloc(sizeof(mstm), GFP_KERNEL)))
1274	1580	return -ENOMEM;
..	..	@@ -1279,13 +1585,6 @@
1279	1585	max_payloads, conn_base_id);
1280	1586	if (ret)
1281	1587	return ret;
1282		-
1283		- for (i = 0; i < max_payloads; i++) {
1284		- ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1285		- i, &mstm->msto[i]);
1286		- if (ret)
1287		- return ret;
1288		- }
1289	1588
1290	1589	return 0;
1291	1590	}
..	..	@@ -1302,10 +1601,10 @@
1302	1601
1303	1602	if (!asyh) {
1304	1603	nv_encoder->ctrl &= ~BIT(head);
1305		- if (!(nv_encoder->ctrl & 0x0000000f))
	1604	+ if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1306	1605	nv_encoder->ctrl = 0;
1307	1606	} else {
1308		- nv_encoder->ctrl \|= proto << 8;
	1607	+ nv_encoder->ctrl \|= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1309	1608	nv_encoder->ctrl \|= BIT(head);
1310	1609	asyh->or.depth = depth;
1311	1610	}
..	..	@@ -1314,23 +1613,27 @@
1314	1613	}
1315	1614
1316	1615	static void
1317		-nv50_sor_disable(struct drm_encoder *encoder)
	1616	+nv50_sor_disable(struct drm_encoder *encoder,
	1617	+ struct drm_atomic_state *state)
1318	1618	{
1319	1619	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1320	1620	struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
	1621	+ struct nouveau_connector *nv_connector =
	1622	+ nv50_outp_get_old_connector(nv_encoder, state);
1321	1623
1322	1624	nv_encoder->crtc = NULL;
1323	1625
1324	1626	if (nv_crtc) {
1325		- struct nvkm_i2c_aux *aux = nv_encoder->aux;
	1627	+ struct drm_dp_aux *aux = &nv_connector->aux;
1326	1628	u8 pwr;
1327	1629
1328		- if (aux) {
1329		- int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
	1630	+ if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
	1631	+ int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
	1632	+
1330	1633	if (ret == 0) {
1331	1634	pwr &= ~DP_SET_POWER_MASK;
1332	1635	pwr \|= DP_SET_POWER_D3;
1333		- nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
	1636	+ drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1334	1637	}
1335	1638	}
1336	1639
..	..	@@ -1342,7 +1645,7 @@
1342	1645	}
1343	1646
1344	1647	static void
1345		-nv50_sor_enable(struct drm_encoder *encoder)
	1648	+nv50_sor_enable(struct drm_encoder encoder, struct drm_atomic_state state)
1346	1649	{
1347	1650	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1348	1651	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
..	..	@@ -1362,17 +1665,23 @@
1362	1665	struct nouveau_drm *drm = nouveau_drm(dev);
1363	1666	struct nouveau_connector *nv_connector;
1364	1667	struct nvbios *bios = &drm->vbios;
1365		- u8 proto = 0xf;
1366		- u8 depth = 0x0;
	1668	+ bool hda = false;
	1669	+ u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
	1670	+ u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1367	1671
1368		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
	1672	+ nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
1369	1673	nv_encoder->crtc = encoder->crtc;
1370		- nv50_outp_acquire(nv_encoder);
	1674	+
	1675	+ if ((disp->disp->object.oclass == GT214_DISP \|\|
	1676	+ disp->disp->object.oclass >= GF110_DISP) &&
	1677	+ drm_detect_monitor_audio(nv_connector->edid))
	1678	+ hda = true;
	1679	+ nv50_outp_acquire(nv_encoder, hda);
1371	1680
1372	1681	switch (nv_encoder->dcb->type) {
1373	1682	case DCB_OUTPUT_TMDS:
1374	1683	if (nv_encoder->link & 1) {
1375		- proto = 0x1;
	1684	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1376	1685	/* Only enable dual-link if:
1377	1686	* - Need to (i.e. rate > 165MHz)
1378	1687	* - DCB says we can
..	..	@@ -1382,15 +1691,15 @@
1382	1691	if (mode->clock >= 165000 &&
1383	1692	nv_encoder->dcb->duallink_possible &&
1384	1693	!drm_detect_hdmi_monitor(nv_connector->edid))
1385		- proto \|= 0x4;
	1694	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1386	1695	} else {
1387		- proto = 0x2;
	1696	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1388	1697	}
1389	1698
1390		- nv50_hdmi_enable(&nv_encoder->base.base, mode);
	1699	+ nv50_hdmi_enable(&nv_encoder->base.base, state, mode);
1391	1700	break;
1392	1701	case DCB_OUTPUT_LVDS:
1393		- proto = 0x0;
	1702	+ proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1394	1703
1395	1704	if (bios->fp_no_ddc) {
1396	1705	if (bios->fp.dual_link)
..	..	@@ -1414,27 +1723,21 @@
1414	1723	lvds.lvds.script \|= 0x0200;
1415	1724	}
1416	1725
1417		- if (nv_connector->base.display_info.bpc == 8)
	1726	+ if (asyh->or.bpc == 8)
1418	1727	lvds.lvds.script \|= 0x0200;
1419	1728	}
1420	1729
1421	1730	nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1422	1731	break;
1423	1732	case DCB_OUTPUT_DP:
1424		- if (nv_connector->base.display_info.bpc == 6)
1425		- depth = 0x2;
1426		- else
1427		- if (nv_connector->base.display_info.bpc == 8)
1428		- depth = 0x5;
1429		- else
1430		- depth = 0x6;
	1733	+ depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1431	1734
1432	1735	if (nv_encoder->link & 1)
1433		- proto = 0x8;
	1736	+ proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1434	1737	else
1435		- proto = 0x9;
	1738	+ proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1436	1739
1437		- nv50_audio_enable(encoder, mode);
	1740	+ nv50_audio_enable(encoder, state, mode);
1438	1741	break;
1439	1742	default:
1440	1743	BUG();
..	..	@@ -1447,8 +1750,8 @@
1447	1750	static const struct drm_encoder_helper_funcs
1448	1751	nv50_sor_help = {
1449	1752	.atomic_check = nv50_outp_atomic_check,
1450		- .enable = nv50_sor_enable,
1451		- .disable = nv50_sor_disable,
	1753	+ .atomic_enable = nv50_sor_enable,
	1754	+ .atomic_disable = nv50_sor_disable,
1452	1755	};
1453	1756
1454	1757	static void
..	..	@@ -1457,6 +1760,10 @@
1457	1760	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1458	1761	nv50_mstm_del(&nv_encoder->dp.mstm);
1459	1762	drm_encoder_cleanup(encoder);
	1763	+
	1764	+ if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
	1765	+ mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
	1766	+
1460	1767	kfree(encoder);
1461	1768	}
1462	1769
..	..	@@ -1465,17 +1772,25 @@
1465	1772	.destroy = nv50_sor_destroy,
1466	1773	};
1467	1774
	1775	+static bool nv50_has_mst(struct nouveau_drm *drm)
	1776	+{
	1777	+ struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
	1778	+ u32 data;
	1779	+ u8 ver, hdr, cnt, len;
	1780	+
	1781	+ data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
	1782	+ return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
	1783	+}
	1784	+
1468	1785	static int
1469	1786	nv50_sor_create(struct drm_connector connector, struct dcb_output dcbe)
1470	1787	{
1471	1788	struct nouveau_connector *nv_connector = nouveau_connector(connector);
1472	1789	struct nouveau_drm *drm = nouveau_drm(connector->dev);
1473		- struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1474	1790	struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1475	1791	struct nouveau_encoder *nv_encoder;
1476	1792	struct drm_encoder *encoder;
1477		- u8 ver, hdr, cnt, len;
1478		- u32 data;
	1793	+ struct nv50_disp *disp = nv50_disp(connector->dev);
1479	1794	int type, ret;
1480	1795
1481	1796	switch (dcbe->type) {
..	..	@@ -1502,10 +1817,14 @@
1502	1817
1503	1818	drm_connector_attach_encoder(connector, encoder);
1504	1819
	1820	+ disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
	1821	+
1505	1822	if (dcbe->type == DCB_OUTPUT_DP) {
1506		- struct nv50_disp *disp = nv50_disp(encoder->dev);
1507	1823	struct nvkm_i2c_aux *aux =
1508	1824	nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
	1825	+
	1826	+ mutex_init(&nv_encoder->dp.hpd_irq_lock);
	1827	+
1509	1828	if (aux) {
1510	1829	if (disp->disp->object.oclass < GF110_DISP) {
1511	1830	/* HW has no support for address-only
..	..	@@ -1520,10 +1839,9 @@
1520	1839	}
1521	1840
1522	1841	if (nv_connector->type != DCB_CONNECTOR_eDP &&
1523		- (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1524		- ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1525		- ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1526		- nv_connector->base.base.id,
	1842	+ nv50_has_mst(drm)) {
	1843	+ ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
	1844	+ 16, nv_connector->base.base.id,
1527	1845	&nv_encoder->dp.mstm);
1528	1846	if (ret)
1529	1847	return ret;
..	..	@@ -1554,56 +1872,62 @@
1554	1872	}
1555	1873
1556	1874	static void
1557		-nv50_pior_disable(struct drm_encoder *encoder)
	1875	+nv50_pior_disable(struct drm_encoder encoder, struct drm_atomic_state state)
1558	1876	{
1559	1877	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1560	1878	struct nv50_core *core = nv50_disp(encoder->dev)->core;
	1879	+ const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1561	1880	if (nv_encoder->crtc)
1562		- core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
	1881	+ core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1563	1882	nv_encoder->crtc = NULL;
1564	1883	nv50_outp_release(nv_encoder);
1565	1884	}
1566	1885
1567	1886	static void
1568		-nv50_pior_enable(struct drm_encoder *encoder)
	1887	+nv50_pior_enable(struct drm_encoder encoder, struct drm_atomic_state state)
1569	1888	{
1570	1889	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1571	1890	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1572		- struct nouveau_connector *nv_connector;
1573	1891	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1574	1892	struct nv50_core *core = nv50_disp(encoder->dev)->core;
1575		- u8 owner = 1 << nv_crtc->index;
1576		- u8 proto;
	1893	+ u32 ctrl = 0;
1577	1894
1578		- nv50_outp_acquire(nv_encoder);
	1895	+ switch (nv_crtc->index) {
	1896	+ case 0: ctrl \|= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
	1897	+ case 1: ctrl \|= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
	1898	+ default:
	1899	+ WARN_ON(1);
	1900	+ break;
	1901	+ }
1579	1902
1580		- nv_connector = nouveau_encoder_connector_get(nv_encoder);
1581		- switch (nv_connector->base.display_info.bpc) {
1582		- case 10: asyh->or.depth = 0x6; break;
1583		- case 8: asyh->or.depth = 0x5; break;
1584		- case 6: asyh->or.depth = 0x2; break;
1585		- default: asyh->or.depth = 0x0; break;
	1903	+ nv50_outp_acquire(nv_encoder, false);
	1904	+
	1905	+ switch (asyh->or.bpc) {
	1906	+ case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
	1907	+ case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
	1908	+ case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
	1909	+ default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1586	1910	}
1587	1911
1588	1912	switch (nv_encoder->dcb->type) {
1589	1913	case DCB_OUTPUT_TMDS:
1590	1914	case DCB_OUTPUT_DP:
1591		- proto = 0x0;
	1915	+ ctrl \|= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1592	1916	break;
1593	1917	default:
1594	1918	BUG();
1595	1919	break;
1596	1920	}
1597	1921
1598		- core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) \| owner, asyh);
1599		- nv_encoder->crtc = encoder->crtc;
	1922	+ core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
	1923	+ nv_encoder->crtc = &nv_crtc->base;
1600	1924	}
1601	1925
1602	1926	static const struct drm_encoder_helper_funcs
1603	1927	nv50_pior_help = {
1604	1928	.atomic_check = nv50_pior_atomic_check,
1605		- .enable = nv50_pior_enable,
1606		- .disable = nv50_pior_disable,
	1929	+ .atomic_enable = nv50_pior_enable,
	1930	+ .atomic_disable = nv50_pior_disable,
1607	1931	};
1608	1932
1609	1933	static void
..	..	@@ -1621,7 +1945,9 @@
1621	1945	static int
1622	1946	nv50_pior_create(struct drm_connector connector, struct dcb_output dcbe)
1623	1947	{
1624		- struct nouveau_drm *drm = nouveau_drm(connector->dev);
	1948	+ struct drm_device *dev = connector->dev;
	1949	+ struct nouveau_drm *drm = nouveau_drm(dev);
	1950	+ struct nv50_disp *disp = nv50_disp(dev);
1625	1951	struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1626	1952	struct nvkm_i2c_bus *bus = NULL;
1627	1953	struct nvkm_i2c_aux *aux = NULL;
..	..	@@ -1660,6 +1986,9 @@
1660	1986	drm_encoder_helper_add(encoder, &nv50_pior_help);
1661	1987
1662	1988	drm_connector_attach_encoder(connector, encoder);
	1989	+
	1990	+ disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
	1991	+
1663	1992	return 0;
1664	1993	}
1665	1994
..	..	@@ -1728,14 +2057,18 @@
1728	2057	struct nouveau_drm *drm = nouveau_drm(dev);
1729	2058	struct nv50_disp *disp = nv50_disp(dev);
1730	2059	struct nv50_atom *atom = nv50_atom(state);
	2060	+ struct nv50_core *core = disp->core;
1731	2061	struct nv50_outp_atom outp, outt;
1732	2062	u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1733	2063	int i;
	2064	+ bool flushed = false;
1734	2065
1735	2066	NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
	2067	+ nv50_crc_atomic_stop_reporting(state);
1736	2068	drm_atomic_helper_wait_for_fences(dev, state, false);
1737	2069	drm_atomic_helper_wait_for_dependencies(state);
1738	2070	drm_atomic_helper_update_legacy_modeset_state(dev, state);
	2071	+ drm_atomic_helper_calc_timestamping_constants(state);
1739	2072
1740	2073	if (atom->lock_core)
1741	2074	mutex_lock(&disp->mutex);
..	..	@@ -1747,8 +2080,11 @@
1747	2080
1748	2081	NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1749	2082	asyh->clr.mask, asyh->set.mask);
1750		- if (old_crtc_state->active && !new_crtc_state->active)
	2083	+
	2084	+ if (old_crtc_state->active && !new_crtc_state->active) {
	2085	+ pm_runtime_put_noidle(dev->dev);
1751	2086	drm_crtc_vblank_off(crtc);
	2087	+ }
1752	2088
1753	2089	if (asyh->clr.mask) {
1754	2090	nv50_head_flush_clr(head, asyh, atom->flush_disable);
..	..	@@ -1781,12 +2117,14 @@
1781	2117	outp->clr.mask, outp->set.mask);
1782	2118
1783	2119	if (outp->clr.mask) {
1784		- help->disable(encoder);
	2120	+ help->atomic_disable(encoder, state);
1785	2121	interlock[NV50_DISP_INTERLOCK_CORE] \|= 1;
1786	2122	if (outp->flush_disable) {
1787	2123	nv50_disp_atomic_commit_wndw(state, interlock);
1788	2124	nv50_disp_atomic_commit_core(state, interlock);
1789	2125	memset(interlock, 0x00, sizeof(interlock));
	2126	+
	2127	+ flushed = true;
1790	2128	}
1791	2129	}
1792	2130	}
..	..	@@ -1797,8 +2135,14 @@
1797	2135	nv50_disp_atomic_commit_wndw(state, interlock);
1798	2136	nv50_disp_atomic_commit_core(state, interlock);
1799	2137	memset(interlock, 0x00, sizeof(interlock));
	2138	+
	2139	+ flushed = true;
1800	2140	}
1801	2141	}
	2142	+
	2143	+ if (flushed)
	2144	+ nv50_crc_atomic_release_notifier_contexts(state);
	2145	+ nv50_crc_atomic_init_notifier_contexts(state);
1802	2146
1803	2147	/* Update output path(s). */
1804	2148	list_for_each_entry_safe(outp, outt, &atom->outp, head) {
..	..	@@ -1812,7 +2156,7 @@
1812	2156	outp->set.mask, outp->clr.mask);
1813	2157
1814	2158	if (outp->set.mask) {
1815		- help->enable(encoder);
	2159	+ help->atomic_enable(encoder, state);
1816	2160	interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1817	2161	}
1818	2162
..	..	@@ -1834,10 +2178,54 @@
1834	2178	}
1835	2179
1836	2180	if (new_crtc_state->active) {
1837		- if (!old_crtc_state->active)
	2181	+ if (!old_crtc_state->active) {
1838	2182	drm_crtc_vblank_on(crtc);
	2183	+ pm_runtime_get_noresume(dev->dev);
	2184	+ }
1839	2185	if (new_crtc_state->event)
1840	2186	drm_crtc_vblank_get(crtc);
	2187	+ }
	2188	+ }
	2189	+
	2190	+ /* Update window->head assignment.
	2191	+ *
	2192	+ * This has to happen in an update that's not interlocked with
	2193	+ * any window channels to avoid hitting HW error checks.
	2194	+ *
	2195	+ *TODO: Proper handling of window ownership (Turing apparently
	2196	+ * supports non-fixed mappings).
	2197	+ */
	2198	+ if (core->assign_windows) {
	2199	+ core->func->wndw.owner(core);
	2200	+ nv50_disp_atomic_commit_core(state, interlock);
	2201	+ core->assign_windows = false;
	2202	+ interlock[NV50_DISP_INTERLOCK_CORE] = 0;
	2203	+ }
	2204	+
	2205	+ /* Finish updating head(s)...
	2206	+ *
	2207	+ * NVD is rather picky about both where window assignments can change,
	2208	+ * and about certain core and window channel states matching.
	2209	+ *
	2210	+ * The EFI GOP driver on newer GPUs configures window channels with a
	2211	+ * different output format to what we do, and the core channel update
	2212	+ * in the assign_windows case above would result in a state mismatch.
	2213	+ *
	2214	+ * Delay some of the head update until after that point to workaround
	2215	+ * the issue. This only affects the initial modeset.
	2216	+ *
	2217	+ * TODO: handle this better when adding flexible window mapping
	2218	+ */
	2219	+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
	2220	+ struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
	2221	+ struct nv50_head *head = nv50_head(crtc);
	2222	+
	2223	+ NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
	2224	+ asyh->set.mask, asyh->clr.mask);
	2225	+
	2226	+ if (asyh->set.mask) {
	2227	+ nv50_head_flush_set_wndw(head, asyh);
	2228	+ interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1841	2229	}
1842	2230	}
1843	2231
..	..	@@ -1896,10 +2284,17 @@
1896	2284	}
1897	2285	}
1898	2286
	2287	+ nv50_crc_atomic_start_reporting(state);
	2288	+ if (!flushed)
	2289	+ nv50_crc_atomic_release_notifier_contexts(state);
1899	2290	drm_atomic_helper_commit_hw_done(state);
1900	2291	drm_atomic_helper_cleanup_planes(dev, state);
1901	2292	drm_atomic_helper_commit_cleanup_done(state);
1902	2293	drm_atomic_state_put(state);
	2294	+
	2295	+ /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
	2296	+ pm_runtime_mark_last_busy(dev->dev);
	2297	+ pm_runtime_put_autosuspend(dev->dev);
1903	2298	}
1904	2299
1905	2300	static void
..	..	@@ -1914,11 +2309,8 @@
1914	2309	nv50_disp_atomic_commit(struct drm_device *dev,
1915	2310	struct drm_atomic_state *state, bool nonblock)
1916	2311	{
1917		- struct nouveau_drm *drm = nouveau_drm(dev);
1918	2312	struct drm_plane_state *new_plane_state;
1919	2313	struct drm_plane *plane;
1920		- struct drm_crtc *crtc;
1921		- bool active = false;
1922	2314	int ret, i;
1923	2315
1924	2316	ret = pm_runtime_get_sync(dev->dev);
..	..	@@ -1957,26 +2349,16 @@
1957	2349
1958	2350	drm_atomic_state_get(state);
1959	2351
	2352	+ /*
	2353	+ * Grab another RPM ref for the commit tail, which will release the
	2354	+ * ref when it's finished
	2355	+ */
	2356	+ pm_runtime_get_noresume(dev->dev);
	2357	+
1960	2358	if (nonblock)
1961	2359	queue_work(system_unbound_wq, &state->commit_work);
1962	2360	else
1963	2361	nv50_disp_atomic_commit_tail(state);
1964		-
1965		- drm_for_each_crtc(crtc, dev) {
1966		- if (crtc->state->active) {
1967		- if (!drm->have_disp_power_ref) {
1968		- drm->have_disp_power_ref = true;
1969		- return 0;
1970		- }
1971		- active = true;
1972		- break;
1973		- }
1974		- }
1975		-
1976		- if (!active && drm->have_disp_power_ref) {
1977		- pm_runtime_put_autosuspend(dev->dev);
1978		- drm->have_disp_power_ref = false;
1979		- }
1980	2362
1981	2363	err_cleanup:
1982	2364	if (ret)
..	..	@@ -2064,11 +2446,27 @@
2064	2446	nv50_disp_atomic_check(struct drm_device dev, struct drm_atomic_state state)
2065	2447	{
2066	2448	struct nv50_atom *atom = nv50_atom(state);
	2449	+ struct nv50_core *core = nv50_disp(dev)->core;
2067	2450	struct drm_connector_state old_connector_state, new_connector_state;
2068	2451	struct drm_connector *connector;
2069	2452	struct drm_crtc_state *new_crtc_state;
2070	2453	struct drm_crtc *crtc;
	2454	+ struct nv50_head *head;
	2455	+ struct nv50_head_atom *asyh;
2071	2456	int ret, i;
	2457	+
	2458	+ if (core->assign_windows && core->func->head->static_wndw_map) {
	2459	+ drm_for_each_crtc(crtc, dev) {
	2460	+ new_crtc_state = drm_atomic_get_crtc_state(state,
	2461	+ crtc);
	2462	+ if (IS_ERR(new_crtc_state))
	2463	+ return PTR_ERR(new_crtc_state);
	2464	+
	2465	+ head = nv50_head(crtc);
	2466	+ asyh = nv50_head_atom(new_crtc_state);
	2467	+ core->func->head->static_wndw_map(head, asyh);
	2468	+ }
	2469	+ }
2072	2470
2073	2471	/* We need to handle colour management on a per-plane basis. */
2074	2472	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
..	..	@@ -2092,6 +2490,12 @@
2092	2490	if (ret)
2093	2491	return ret;
2094	2492	}
	2493	+
	2494	+ ret = drm_dp_mst_atomic_check(state);
	2495	+ if (ret)
	2496	+ return ret;
	2497	+
	2498	+ nv50_crc_atomic_check_outp(atom);
2095	2499
2096	2500	return 0;
2097	2501	}
..	..	@@ -2146,10 +2550,10 @@
2146	2550	* Init
2147	2551	*****************************************************************************/
2148	2552
2149		-void
2150		-nv50_display_fini(struct drm_device *dev)
	2553	+static void
	2554	+nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2151	2555	{
2152		- struct nouveau_encoder *nv_encoder;
	2556	+ struct nouveau_drm *drm = nouveau_drm(dev);
2153	2557	struct drm_encoder *encoder;
2154	2558	struct drm_plane *plane;
2155	2559
..	..	@@ -2161,27 +2565,29 @@
2161	2565	}
2162	2566
2163	2567	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2164		- if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2165		- nv_encoder = nouveau_encoder(encoder);
2166		- nv50_mstm_fini(nv_encoder->dp.mstm);
2167		- }
	2568	+ if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
	2569	+ nv50_mstm_fini(nouveau_encoder(encoder));
2168	2570	}
	2571	+
	2572	+ if (!runtime)
	2573	+ cancel_work_sync(&drm->hpd_work);
2169	2574	}
2170	2575
2171		-int
2172		-nv50_display_init(struct drm_device *dev)
	2576	+static int
	2577	+nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2173	2578	{
2174	2579	struct nv50_core *core = nv50_disp(dev)->core;
2175	2580	struct drm_encoder *encoder;
2176	2581	struct drm_plane *plane;
2177	2582
2178		- core->func->init(core);
	2583	+ if (resume \|\| runtime)
	2584	+ core->func->init(core);
2179	2585
2180	2586	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2181	2587	if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2182	2588	struct nouveau_encoder *nv_encoder =
2183	2589	nouveau_encoder(encoder);
2184		- nv50_mstm_init(nv_encoder->dp.mstm);
	2590	+ nv50_mstm_init(nv_encoder, runtime);
2185	2591	}
2186	2592	}
2187	2593
..	..	@@ -2195,11 +2601,15 @@
2195	2601	return 0;
2196	2602	}
2197	2603
2198		-void
	2604	+static void
2199	2605	nv50_display_destroy(struct drm_device *dev)
2200	2606	{
2201	2607	struct nv50_disp *disp = nv50_disp(dev);
2202	2608
	2609	+ nv50_audio_component_fini(nouveau_drm(dev));
	2610	+
	2611	+ nvif_object_unmap(&disp->caps);
	2612	+ nvif_object_dtor(&disp->caps);
2203	2613	nv50_core_del(&disp->core);
2204	2614
2205	2615	nouveau_bo_unmap(disp->sync);
..	..	@@ -2221,6 +2631,7 @@
2221	2631	struct nv50_disp *disp;
2222	2632	struct dcb_output *dcbe;
2223	2633	int crtcs, ret, i;
	2634	+ bool has_mst = nv50_has_mst(drm);
2224	2635
2225	2636	disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2226	2637	if (!disp)
..	..	@@ -2234,13 +2645,15 @@
2234	2645	nouveau_display(dev)->fini = nv50_display_fini;
2235	2646	disp->disp = &nouveau_display(dev)->disp;
2236	2647	dev->mode_config.funcs = &nv50_disp_func;
2237		- dev->driver->driver_features \|= DRIVER_PREFER_XBGR_30BPP;
	2648	+ dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
	2649	+ dev->mode_config.normalize_zpos = true;
2238	2650
2239	2651	/* small shared memory area we use for notifiers and semaphores */
2240		- ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
	2652	+ ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
	2653	+ NOUVEAU_GEM_DOMAIN_VRAM,
2241	2654	0, 0x0000, NULL, NULL, &disp->sync);
2242	2655	if (!ret) {
2243		- ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
	2656	+ ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2244	2657	if (!ret) {
2245	2658	ret = nouveau_bo_map(disp->sync);
2246	2659	if (ret)
..	..	@@ -2258,6 +2671,22 @@
2258	2671	if (ret)
2259	2672	goto out;
2260	2673
	2674	+ disp->core->func->init(disp->core);
	2675	+ if (disp->core->func->caps_init) {
	2676	+ ret = disp->core->func->caps_init(drm, disp);
	2677	+ if (ret)
	2678	+ goto out;
	2679	+ }
	2680	+
	2681	+ /* Assign the correct format modifiers */
	2682	+ if (disp->disp->object.oclass >= TU102_DISP)
	2683	+ nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
	2684	+ else
	2685	+ if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
	2686	+ nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
	2687	+ else
	2688	+ nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
	2689	+
2261	2690	/* create crtc objects to represent the hw heads */
2262	2691	if (disp->disp->object.oclass >= GV100_DISP)
2263	2692	crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
..	..	@@ -2268,16 +2697,42 @@
2268	2697	crtcs = 0x3;
2269	2698
2270	2699	for (i = 0; i < fls(crtcs); i++) {
	2700	+ struct nv50_head *head;
	2701	+
2271	2702	if (!(crtcs & (1 << i)))
2272	2703	continue;
2273		- ret = nv50_head_create(dev, i);
2274		- if (ret)
	2704	+
	2705	+ head = nv50_head_create(dev, i);
	2706	+ if (IS_ERR(head)) {
	2707	+ ret = PTR_ERR(head);
2275	2708	goto out;
	2709	+ }
	2710	+
	2711	+ if (has_mst) {
	2712	+ head->msto = nv50_msto_new(dev, head, i);
	2713	+ if (IS_ERR(head->msto)) {
	2714	+ ret = PTR_ERR(head->msto);
	2715	+ head->msto = NULL;
	2716	+ goto out;
	2717	+ }
	2718	+
	2719	+ /*
	2720	+ * FIXME: This is a hack to workaround the following
	2721	+ * issues:
	2722	+ *
	2723	+ * https://gitlab.gnome.org/GNOME/mutter/issues/759
	2724	+ * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
	2725	+ *
	2726	+ * Once these issues are closed, this should be
	2727	+ * removed
	2728	+ */
	2729	+ head->msto->encoder.possible_crtcs = crtcs;
	2730	+ }
2276	2731	}
2277	2732
2278	2733	/* create encoder/connector objects based on VBIOS DCB table */
2279	2734	for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2280		- connector = nouveau_connector_create(dev, dcbe->connector);
	2735	+ connector = nouveau_connector_create(dev, dcbe);
2281	2736	if (IS_ERR(connector))
2282	2737	continue;
2283	2738
..	..	@@ -2309,7 +2764,7 @@
2309	2764
2310	2765	/* cull any connectors we created that don't have an encoder */
2311	2766	list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2312		- if (connector->encoder_ids[0])
	2767	+ if (connector->possible_encoders)
2313	2768	continue;
2314	2769
2315	2770	NV_WARN(drm, "%s has no encoders, removing\n",
..	..	@@ -2320,8 +2775,60 @@
2320	2775	/* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2321	2776	dev->vblank_disable_immediate = true;
2322	2777
	2778	+ nv50_audio_component_init(drm);
	2779	+
2323	2780	out:
2324	2781	if (ret)
2325	2782	nv50_display_destroy(dev);
2326	2783	return ret;
2327	2784	}
	2785	+
	2786	+/******************************************************************************
	2787	+ * Format modifiers
	2788	+ *****************************************************************************/
	2789	+
	2790	+/****************************************************************
	2791	+ * Log2(block height) ----------------------------+ *
	2792	+ * Page Kind ----------------------------------+ \| *
	2793	+ * Gob Height/Page Kind Generation ------+ \| \| *
	2794	+ * Sector layout -------+ \| \| \| *
	2795	+ * Compression ------+ \| \| \| \| */
	2796	+const u64 disp50xx_modifiers[] = { /* \| \| \| \| \| */
	2797	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
	2798	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
	2799	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
	2800	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
	2801	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
	2802	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
	2803	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
	2804	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
	2805	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
	2806	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
	2807	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
	2808	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
	2809	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
	2810	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
	2811	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
	2812	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
	2813	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
	2814	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
	2815	+ DRM_FORMAT_MOD_LINEAR,
	2816	+ DRM_FORMAT_MOD_INVALID
	2817	+};
	2818	+
	2819	+/****************************************************************
	2820	+ * Log2(block height) ----------------------------+ *
	2821	+ * Page Kind ----------------------------------+ \| *
	2822	+ * Gob Height/Page Kind Generation ------+ \| \| *
	2823	+ * Sector layout -------+ \| \| \| *
	2824	+ * Compression ------+ \| \| \| \| */
	2825	+const u64 disp90xx_modifiers[] = { /* \| \| \| \| \| */
	2826	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
	2827	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
	2828	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
	2829	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
	2830	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
	2831	+ DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
	2832	+ DRM_FORMAT_MOD_LINEAR,
	2833	+ DRM_FORMAT_MOD_INVALID
	2834	+};