forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
....@@ -1,10 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright (C) 2011 Freescale Semiconductor, Inc.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License as published by
6
- * the Free Software Foundation; either version 2 of the License, or
7
- * (at your option) any later version.
84  */
95 
106 #ifndef __DW_HDMI_H__
....@@ -162,13 +158,6 @@
162158 #define HDMI_FC_SPDDEVICEINF                    0x1062
163159 #define HDMI_FC_AUDSCONF                        0x1063
164160 #define HDMI_FC_AUDSSTAT                        0x1064
165
-#define HDMI_FC_AUDSCHNLS0                      0x1067
166
-#define HDMI_FC_AUDSCHNLS1                      0x1068
167
-#define HDMI_FC_AUDSCHNLS2                      0x1069
168
-#define HDMI_FC_AUDSCHNLS3                      0x106a
169
-#define HDMI_FC_AUDSCHNLS4                      0x106b
170
-#define HDMI_FC_AUDSCHNLS5                      0x106c
171
-#define HDMI_FC_AUDSCHNLS6                      0x106d
172161 #define HDMI_FC_AUDSCHNLS7                      0x106e
173162 #define HDMI_FC_AUDSCHNLS8                      0x106f
174163 #define HDMI_FC_DATACH0FILL                     0x1070
....@@ -265,7 +254,7 @@
265254 #define HDMI_FC_POL2                            0x10DB
266255 #define HDMI_FC_PRCONF                          0x10E0
267256 #define HDMI_FC_SCRAMBLER_CTRL                  0x10E1
268
-#define HDMI_FC_PACKET_TX_EN			0x10E3
257
+#define HDMI_FC_PACKET_TX_EN                    0x10E3
269258 
270259 #define HDMI_FC_GMD_STAT                        0x1100
271260 #define HDMI_FC_GMD_EN                          0x1101
....@@ -301,36 +290,36 @@
301290 #define HDMI_FC_GMD_PB26                        0x111F
302291 #define HDMI_FC_GMD_PB27                        0x1120
303292 
304
-#define HDMI_FC_DRM_UP				0x1167
305
-#define HDMI_FC_DRM_HB0				0x1168
306
-#define HDMI_FC_DRM_HB1				0x1169
307
-#define HDMI_FC_DRM_PB0				0x116a
308
-#define HDMI_FC_DRM_PB1				0x116b
309
-#define HDMI_FC_DRM_PB2				0x116c
310
-#define HDMI_FC_DRM_PB3				0x116d
311
-#define HDMI_FC_DRM_PB4				0x116e
312
-#define HDMI_FC_DRM_PB5				0x116f
313
-#define HDMI_FC_DRM_PB6				0x1170
314
-#define HDMI_FC_DRM_PB7				0x1171
315
-#define HDMI_FC_DRM_PB8				0x1172
316
-#define HDMI_FC_DRM_PB9				0x1173
317
-#define HDMI_FC_DRM_PB10			0x1174
318
-#define HDMI_FC_DRM_PB11			0x1175
319
-#define HDMI_FC_DRM_PB12			0x1176
320
-#define HDMI_FC_DRM_PB13			0x1177
321
-#define HDMI_FC_DRM_PB14			0x1178
322
-#define HDMI_FC_DRM_PB15			0x1179
323
-#define HDMI_FC_DRM_PB16			0x117a
324
-#define HDMI_FC_DRM_PB17			0x117b
325
-#define HDMI_FC_DRM_PB18			0x117c
326
-#define HDMI_FC_DRM_PB19			0x117d
327
-#define HDMI_FC_DRM_PB20			0x117e
328
-#define HDMI_FC_DRM_PB21			0x117f
329
-#define HDMI_FC_DRM_PB22			0x1180
330
-#define HDMI_FC_DRM_PB23			0x1181
331
-#define HDMI_FC_DRM_PB24			0x1182
332
-#define HDMI_FC_DRM_PB25			0x1183
333
-#define HDMI_FC_DRM_PB26			0x1184
293
+#define HDMI_FC_DRM_UP                          0x1167
294
+#define HDMI_FC_DRM_HB0                         0x1168
295
+#define HDMI_FC_DRM_HB1                         0x1169
296
+#define HDMI_FC_DRM_PB0                         0x116A
297
+#define HDMI_FC_DRM_PB1                         0x116B
298
+#define HDMI_FC_DRM_PB2                         0x116C
299
+#define HDMI_FC_DRM_PB3                         0x116D
300
+#define HDMI_FC_DRM_PB4                         0x116E
301
+#define HDMI_FC_DRM_PB5                         0x116F
302
+#define HDMI_FC_DRM_PB6                         0x1170
303
+#define HDMI_FC_DRM_PB7                         0x1171
304
+#define HDMI_FC_DRM_PB8                         0x1172
305
+#define HDMI_FC_DRM_PB9                         0x1173
306
+#define HDMI_FC_DRM_PB10                        0x1174
307
+#define HDMI_FC_DRM_PB11                        0x1175
308
+#define HDMI_FC_DRM_PB12                        0x1176
309
+#define HDMI_FC_DRM_PB13                        0x1177
310
+#define HDMI_FC_DRM_PB14                        0x1178
311
+#define HDMI_FC_DRM_PB15                        0x1179
312
+#define HDMI_FC_DRM_PB16                        0x117A
313
+#define HDMI_FC_DRM_PB17                        0x117B
314
+#define HDMI_FC_DRM_PB18                        0x117C
315
+#define HDMI_FC_DRM_PB19                        0x117D
316
+#define HDMI_FC_DRM_PB20                        0x117E
317
+#define HDMI_FC_DRM_PB21                        0x117F
318
+#define HDMI_FC_DRM_PB22                        0x1180
319
+#define HDMI_FC_DRM_PB23                        0x1181
320
+#define HDMI_FC_DRM_PB24                        0x1182
321
+#define HDMI_FC_DRM_PB25                        0x1183
322
+#define HDMI_FC_DRM_PB26                        0x1184
334323 
335324 #define HDMI_FC_DBGFORCE                        0x1200
336325 #define HDMI_FC_DBGAUD0CH0                      0x1201
....@@ -586,6 +575,16 @@
586575 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
587576 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
588577 #define HDMI_I2CM_SDA_HOLD                      0x7E13
578
+#define HDMI_I2CM_SCDC_READ_UPDATE              0x7E14
579
+#define HDMI_I2CM_READ_REQ_EN_MSK               BIT(4)
580
+#define HDMI_I2CM_READ_REQ_EN_OFFSET            4
581
+#define HDMI_I2CM_READ_UPDATE_MSK               BIT(0)
582
+#define HDMI_I2CM_READ_UPDATE_OFFSET            0
583
+#define HDMI_I2CM_I2CM_UPRD_VSYNC_EN_MSK        BIT(5)
584
+#define HDMI_I2CM_I2CM_UPRD_VSYNC_EN_OFFSET     5
585
+#define	HDMI_I2CM_READ_BUFF0                    0x7E20
586
+#define	HDMI_I2CM_SCDC_UPDATE0                  0x7E30
587
+#define	HDMI_I2CM_SCDC_UPDATE1                  0x7E31
589588 
590589 enum {
591590 /* PRODUCT_ID0 field values */
....@@ -797,23 +796,12 @@
797796 /* HDMI_FC_AUDSCHNLS7 field values */
798797 	HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
799798 	HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
800
-	HDMI_FC_AUDSCHNLS7_SAMPFREQ_OFFSET = 0,
801
-	HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK = 0x0f,
802799 
803800 /* HDMI_FC_AUDSCHNLS8 field values */
804801 	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
805802 	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
806803 	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
807804 	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
808
-
809
-/* HDMI_FC_AUDSCHNLS Sample Rate */
810
-	HDMI_FC_AUDSCHNLS_32K = 0x3,
811
-	HDMI_FC_AUDSCHNLS_441K = 0x0,
812
-	HDMI_FC_AUDSCHNLS_48K = 0x2,
813
-	HDMI_FC_AUDSCHNLS_882K = 0x8,
814
-	HDMI_FC_AUDSCHNLS_96K = 0xa,
815
-	HDMI_FC_AUDSCHNLS_1764K = 0xc,
816
-	HDMI_FC_AUDSCHNLS_192K = 0xe,
817805 
818806 /* FC_AUDSCONF field values */
819807 	HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
....@@ -845,9 +833,9 @@
845833 	HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
846834 
847835 /* FC_PACKET_TX_EN field values */
848
-	HDMI_FC_PACKET_DRM_TX_EN_MASK = 0x80,
849
-	HDMI_FC_PACKET_DRM_TX_EN = 0x80,
850
-	HDMI_FC_PACKET_DRM_TX_DEN = 0x00,
836
+	HDMI_FC_PACKET_TX_EN_DRM_MASK = 0x80,
837
+	HDMI_FC_PACKET_TX_EN_DRM_ENABLE = 0x80,
838
+	HDMI_FC_PACKET_TX_EN_DRM_DISABLE = 0x00,
851839 
852840 /* FC_AVICONF0-FC_AVICONF3 field values */
853841 	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
....@@ -976,21 +964,18 @@
976964 
977965 /* AUD_CONF0 field values */
978966 	HDMI_AUD_CONF0_SW_RESET = 0x80,
979
-	HDMI_AUD_CONF0_I2S_SELECT_MASK = 0x20,
980
-	HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE = 0x21,
981
-	HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE = 0x23,
982
-	HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE = 0x27,
983
-	HDMI_AUD_CONF0_I2S_8CHANNEL_ENABLE = 0x2F,
984
-	HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F,
985
-
986
-/* AUD_INT field values */
987
-	HDMI_AUD_INT_FIFO_EMPTY_MSK = BIT(3),
988
-	HDMI_AUD_INT_FIFO_FULL_MSK = BIT(2),
967
+	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
968
+	HDMI_AUD_CONF0_I2S_EN3 = 0x08,
969
+	HDMI_AUD_CONF0_I2S_EN2 = 0x04,
970
+	HDMI_AUD_CONF0_I2S_EN1 = 0x02,
971
+	HDMI_AUD_CONF0_I2S_EN0 = 0x01,
989972 
990973 /* AUD_CONF1 field values */
991974 	HDMI_AUD_CONF1_MODE_I2S = 0x00,
992
-	HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02,
993
-	HDMI_AUD_CONF1_MODE_LEFT_J = 0x04,
975
+	HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20,
976
+	HDMI_AUD_CONF1_MODE_LEFT_J = 0x40,
977
+	HDMI_AUD_CONF1_MODE_BURST_1 = 0x60,
978
+	HDMI_AUD_CONF1_MODE_BURST_2 = 0x80,
994979 	HDMI_AUD_CONF1_WIDTH_16 = 0x10,
995980 	HDMI_AUD_CONF1_WIDTH_21 = 0x15,
996981 	HDMI_AUD_CONF1_WIDTH_24 = 0x18,
....@@ -1064,6 +1049,7 @@
10641049 	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
10651050 
10661051 /* MC_SWRSTZ field values */
1052
+	HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08,
10671053 	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
10681054 
10691055 /* MC_FLOWCTRL field values */
....@@ -1152,7 +1138,10 @@
11521138 	HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
11531139 
11541140 /* I2CM_OPERATION field values */
1141
+	HDMI_I2CM_OPERATION_BUS_CLEAR = 0x20,
11551142 	HDMI_I2CM_OPERATION_WRITE = 0x10,
1143
+	HDMI_I2CM_OPERATION_READ8_EXT = 0x8,
1144
+	HDMI_I2CM_OPERATION_READ8 = 0x4,
11561145 	HDMI_I2CM_OPERATION_READ_EXT = 0x2,
11571146 	HDMI_I2CM_OPERATION_READ = 0x1,
11581147 
....@@ -1170,9 +1159,6 @@
11701159 	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
11711160 	HDMI_I2CM_DIV_FAST_MODE = 0x8,
11721161 	HDMI_I2CM_DIV_STD_MODE = 0,
1173
-
1174
-/* HDMI_MC_SWRSTZ filed values */
1175
-	HDMI_MC_SWRSTZ_I2S_RESET_MSK = BIT(3),
11761162 };
11771163 
11781164 /*