hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h
....@@ -1,10 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License as published by
6
- * the Free Software Foundation; either version 2 of the License, or
7
- * (at your option) any later version.
84 */
95
106 #ifndef __DW_HDMI_H__
....@@ -162,13 +158,6 @@
162158 #define HDMI_FC_SPDDEVICEINF 0x1062
163159 #define HDMI_FC_AUDSCONF 0x1063
164160 #define HDMI_FC_AUDSSTAT 0x1064
165
-#define HDMI_FC_AUDSCHNLS0 0x1067
166
-#define HDMI_FC_AUDSCHNLS1 0x1068
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-#define HDMI_FC_AUDSCHNLS2 0x1069
168
-#define HDMI_FC_AUDSCHNLS3 0x106a
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-#define HDMI_FC_AUDSCHNLS4 0x106b
170
-#define HDMI_FC_AUDSCHNLS5 0x106c
171
-#define HDMI_FC_AUDSCHNLS6 0x106d
172161 #define HDMI_FC_AUDSCHNLS7 0x106e
173162 #define HDMI_FC_AUDSCHNLS8 0x106f
174163 #define HDMI_FC_DATACH0FILL 0x1070
....@@ -265,7 +254,7 @@
265254 #define HDMI_FC_POL2 0x10DB
266255 #define HDMI_FC_PRCONF 0x10E0
267256 #define HDMI_FC_SCRAMBLER_CTRL 0x10E1
268
-#define HDMI_FC_PACKET_TX_EN 0x10E3
257
+#define HDMI_FC_PACKET_TX_EN 0x10E3
269258
270259 #define HDMI_FC_GMD_STAT 0x1100
271260 #define HDMI_FC_GMD_EN 0x1101
....@@ -301,36 +290,36 @@
301290 #define HDMI_FC_GMD_PB26 0x111F
302291 #define HDMI_FC_GMD_PB27 0x1120
303292
304
-#define HDMI_FC_DRM_UP 0x1167
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-#define HDMI_FC_DRM_HB0 0x1168
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-#define HDMI_FC_DRM_HB1 0x1169
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-#define HDMI_FC_DRM_PB0 0x116a
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-#define HDMI_FC_DRM_PB1 0x116b
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-#define HDMI_FC_DRM_PB2 0x116c
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-#define HDMI_FC_DRM_PB3 0x116d
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-#define HDMI_FC_DRM_PB4 0x116e
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-#define HDMI_FC_DRM_PB5 0x116f
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-#define HDMI_FC_DRM_PB6 0x1170
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-#define HDMI_FC_DRM_PB7 0x1171
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-#define HDMI_FC_DRM_PB8 0x1172
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-#define HDMI_FC_DRM_PB9 0x1173
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-#define HDMI_FC_DRM_PB10 0x1174
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-#define HDMI_FC_DRM_PB11 0x1175
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-#define HDMI_FC_DRM_PB12 0x1176
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-#define HDMI_FC_DRM_PB13 0x1177
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-#define HDMI_FC_DRM_PB14 0x1178
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-#define HDMI_FC_DRM_PB15 0x1179
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-#define HDMI_FC_DRM_PB16 0x117a
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-#define HDMI_FC_DRM_PB17 0x117b
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-#define HDMI_FC_DRM_PB18 0x117c
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-#define HDMI_FC_DRM_PB19 0x117d
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-#define HDMI_FC_DRM_PB20 0x117e
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-#define HDMI_FC_DRM_PB21 0x117f
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-#define HDMI_FC_DRM_PB22 0x1180
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-#define HDMI_FC_DRM_PB23 0x1181
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-#define HDMI_FC_DRM_PB24 0x1182
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-#define HDMI_FC_DRM_PB25 0x1183
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-#define HDMI_FC_DRM_PB26 0x1184
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+#define HDMI_FC_DRM_UP 0x1167
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+#define HDMI_FC_DRM_HB0 0x1168
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+#define HDMI_FC_DRM_HB1 0x1169
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+#define HDMI_FC_DRM_PB0 0x116A
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+#define HDMI_FC_DRM_PB1 0x116B
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+#define HDMI_FC_DRM_PB2 0x116C
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+#define HDMI_FC_DRM_PB3 0x116D
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+#define HDMI_FC_DRM_PB4 0x116E
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+#define HDMI_FC_DRM_PB5 0x116F
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+#define HDMI_FC_DRM_PB6 0x1170
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+#define HDMI_FC_DRM_PB7 0x1171
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+#define HDMI_FC_DRM_PB8 0x1172
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+#define HDMI_FC_DRM_PB9 0x1173
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+#define HDMI_FC_DRM_PB10 0x1174
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+#define HDMI_FC_DRM_PB11 0x1175
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+#define HDMI_FC_DRM_PB12 0x1176
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+#define HDMI_FC_DRM_PB13 0x1177
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+#define HDMI_FC_DRM_PB14 0x1178
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+#define HDMI_FC_DRM_PB15 0x1179
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+#define HDMI_FC_DRM_PB16 0x117A
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+#define HDMI_FC_DRM_PB17 0x117B
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+#define HDMI_FC_DRM_PB18 0x117C
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+#define HDMI_FC_DRM_PB19 0x117D
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+#define HDMI_FC_DRM_PB20 0x117E
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+#define HDMI_FC_DRM_PB21 0x117F
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+#define HDMI_FC_DRM_PB22 0x1180
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+#define HDMI_FC_DRM_PB23 0x1181
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+#define HDMI_FC_DRM_PB24 0x1182
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+#define HDMI_FC_DRM_PB25 0x1183
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+#define HDMI_FC_DRM_PB26 0x1184
334323
335324 #define HDMI_FC_DBGFORCE 0x1200
336325 #define HDMI_FC_DBGAUD0CH0 0x1201
....@@ -807,23 +796,12 @@
807796 /* HDMI_FC_AUDSCHNLS7 field values */
808797 HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
809798 HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
810
- HDMI_FC_AUDSCHNLS7_SAMPFREQ_OFFSET = 0,
811
- HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK = 0x0f,
812799
813800 /* HDMI_FC_AUDSCHNLS8 field values */
814801 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
815802 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
816803 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
817804 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
818
-
819
-/* HDMI_FC_AUDSCHNLS Sample Rate */
820
- HDMI_FC_AUDSCHNLS_32K = 0x3,
821
- HDMI_FC_AUDSCHNLS_441K = 0x0,
822
- HDMI_FC_AUDSCHNLS_48K = 0x2,
823
- HDMI_FC_AUDSCHNLS_882K = 0x8,
824
- HDMI_FC_AUDSCHNLS_96K = 0xa,
825
- HDMI_FC_AUDSCHNLS_1764K = 0xc,
826
- HDMI_FC_AUDSCHNLS_192K = 0xe,
827805
828806 /* FC_AUDSCONF field values */
829807 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
....@@ -855,9 +833,9 @@
855833 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
856834
857835 /* FC_PACKET_TX_EN field values */
858
- HDMI_FC_PACKET_DRM_TX_EN_MASK = 0x80,
859
- HDMI_FC_PACKET_DRM_TX_EN = 0x80,
860
- HDMI_FC_PACKET_DRM_TX_DEN = 0x00,
836
+ HDMI_FC_PACKET_TX_EN_DRM_MASK = 0x80,
837
+ HDMI_FC_PACKET_TX_EN_DRM_ENABLE = 0x80,
838
+ HDMI_FC_PACKET_TX_EN_DRM_DISABLE = 0x00,
861839
862840 /* FC_AVICONF0-FC_AVICONF3 field values */
863841 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
....@@ -986,21 +964,18 @@
986964
987965 /* AUD_CONF0 field values */
988966 HDMI_AUD_CONF0_SW_RESET = 0x80,
989
- HDMI_AUD_CONF0_I2S_SELECT_MASK = 0x20,
990
- HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE = 0x21,
991
- HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE = 0x23,
992
- HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE = 0x27,
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- HDMI_AUD_CONF0_I2S_8CHANNEL_ENABLE = 0x2F,
994
- HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F,
995
-
996
-/* AUD_INT field values */
997
- HDMI_AUD_INT_FIFO_EMPTY_MSK = BIT(3),
998
- HDMI_AUD_INT_FIFO_FULL_MSK = BIT(2),
967
+ HDMI_AUD_CONF0_I2S_SELECT = 0x20,
968
+ HDMI_AUD_CONF0_I2S_EN3 = 0x08,
969
+ HDMI_AUD_CONF0_I2S_EN2 = 0x04,
970
+ HDMI_AUD_CONF0_I2S_EN1 = 0x02,
971
+ HDMI_AUD_CONF0_I2S_EN0 = 0x01,
999972
1000973 /* AUD_CONF1 field values */
1001974 HDMI_AUD_CONF1_MODE_I2S = 0x00,
1002
- HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02,
1003
- HDMI_AUD_CONF1_MODE_LEFT_J = 0x04,
975
+ HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20,
976
+ HDMI_AUD_CONF1_MODE_LEFT_J = 0x40,
977
+ HDMI_AUD_CONF1_MODE_BURST_1 = 0x60,
978
+ HDMI_AUD_CONF1_MODE_BURST_2 = 0x80,
1004979 HDMI_AUD_CONF1_WIDTH_16 = 0x10,
1005980 HDMI_AUD_CONF1_WIDTH_21 = 0x15,
1006981 HDMI_AUD_CONF1_WIDTH_24 = 0x18,
....@@ -1074,6 +1049,7 @@
10741049 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
10751050
10761051 /* MC_SWRSTZ field values */
1052
+ HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08,
10771053 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
10781054
10791055 /* MC_FLOWCTRL field values */
....@@ -1183,9 +1159,6 @@
11831159 HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
11841160 HDMI_I2CM_DIV_FAST_MODE = 0x8,
11851161 HDMI_I2CM_DIV_STD_MODE = 0,
1186
-
1187
-/* HDMI_MC_SWRSTZ filed values */
1188
- HDMI_MC_SWRSTZ_I2S_RESET_MSK = BIT(3),
11891162 };
11901163
11911164 /*