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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or modify |
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5 | | - * it under the terms of the GNU General Public License as published by |
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6 | | - * the Free Software Foundation; either version 2 of the License, or |
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7 | | - * (at your option) any later version. |
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8 | 4 | */ |
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9 | 5 | |
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10 | 6 | #ifndef __DW_HDMI_H__ |
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.. | .. |
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162 | 158 | #define HDMI_FC_SPDDEVICEINF 0x1062 |
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163 | 159 | #define HDMI_FC_AUDSCONF 0x1063 |
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164 | 160 | #define HDMI_FC_AUDSSTAT 0x1064 |
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165 | | -#define HDMI_FC_AUDSCHNLS0 0x1067 |
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166 | | -#define HDMI_FC_AUDSCHNLS1 0x1068 |
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167 | | -#define HDMI_FC_AUDSCHNLS2 0x1069 |
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168 | | -#define HDMI_FC_AUDSCHNLS3 0x106a |
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169 | | -#define HDMI_FC_AUDSCHNLS4 0x106b |
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170 | | -#define HDMI_FC_AUDSCHNLS5 0x106c |
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171 | | -#define HDMI_FC_AUDSCHNLS6 0x106d |
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172 | 161 | #define HDMI_FC_AUDSCHNLS7 0x106e |
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173 | 162 | #define HDMI_FC_AUDSCHNLS8 0x106f |
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174 | 163 | #define HDMI_FC_DATACH0FILL 0x1070 |
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.. | .. |
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265 | 254 | #define HDMI_FC_POL2 0x10DB |
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266 | 255 | #define HDMI_FC_PRCONF 0x10E0 |
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267 | 256 | #define HDMI_FC_SCRAMBLER_CTRL 0x10E1 |
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268 | | -#define HDMI_FC_PACKET_TX_EN 0x10E3 |
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| 257 | +#define HDMI_FC_PACKET_TX_EN 0x10E3 |
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269 | 258 | |
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270 | 259 | #define HDMI_FC_GMD_STAT 0x1100 |
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271 | 260 | #define HDMI_FC_GMD_EN 0x1101 |
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.. | .. |
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301 | 290 | #define HDMI_FC_GMD_PB26 0x111F |
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302 | 291 | #define HDMI_FC_GMD_PB27 0x1120 |
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303 | 292 | |
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304 | | -#define HDMI_FC_DRM_UP 0x1167 |
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305 | | -#define HDMI_FC_DRM_HB0 0x1168 |
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306 | | -#define HDMI_FC_DRM_HB1 0x1169 |
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307 | | -#define HDMI_FC_DRM_PB0 0x116a |
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308 | | -#define HDMI_FC_DRM_PB1 0x116b |
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309 | | -#define HDMI_FC_DRM_PB2 0x116c |
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310 | | -#define HDMI_FC_DRM_PB3 0x116d |
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311 | | -#define HDMI_FC_DRM_PB4 0x116e |
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312 | | -#define HDMI_FC_DRM_PB5 0x116f |
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313 | | -#define HDMI_FC_DRM_PB6 0x1170 |
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314 | | -#define HDMI_FC_DRM_PB7 0x1171 |
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315 | | -#define HDMI_FC_DRM_PB8 0x1172 |
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316 | | -#define HDMI_FC_DRM_PB9 0x1173 |
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317 | | -#define HDMI_FC_DRM_PB10 0x1174 |
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318 | | -#define HDMI_FC_DRM_PB11 0x1175 |
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319 | | -#define HDMI_FC_DRM_PB12 0x1176 |
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320 | | -#define HDMI_FC_DRM_PB13 0x1177 |
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321 | | -#define HDMI_FC_DRM_PB14 0x1178 |
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322 | | -#define HDMI_FC_DRM_PB15 0x1179 |
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323 | | -#define HDMI_FC_DRM_PB16 0x117a |
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324 | | -#define HDMI_FC_DRM_PB17 0x117b |
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325 | | -#define HDMI_FC_DRM_PB18 0x117c |
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326 | | -#define HDMI_FC_DRM_PB19 0x117d |
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327 | | -#define HDMI_FC_DRM_PB20 0x117e |
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328 | | -#define HDMI_FC_DRM_PB21 0x117f |
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329 | | -#define HDMI_FC_DRM_PB22 0x1180 |
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330 | | -#define HDMI_FC_DRM_PB23 0x1181 |
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331 | | -#define HDMI_FC_DRM_PB24 0x1182 |
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332 | | -#define HDMI_FC_DRM_PB25 0x1183 |
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333 | | -#define HDMI_FC_DRM_PB26 0x1184 |
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| 293 | +#define HDMI_FC_DRM_UP 0x1167 |
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| 294 | +#define HDMI_FC_DRM_HB0 0x1168 |
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| 295 | +#define HDMI_FC_DRM_HB1 0x1169 |
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| 296 | +#define HDMI_FC_DRM_PB0 0x116A |
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| 297 | +#define HDMI_FC_DRM_PB1 0x116B |
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| 298 | +#define HDMI_FC_DRM_PB2 0x116C |
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| 299 | +#define HDMI_FC_DRM_PB3 0x116D |
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| 300 | +#define HDMI_FC_DRM_PB4 0x116E |
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| 301 | +#define HDMI_FC_DRM_PB5 0x116F |
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| 302 | +#define HDMI_FC_DRM_PB6 0x1170 |
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| 303 | +#define HDMI_FC_DRM_PB7 0x1171 |
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| 304 | +#define HDMI_FC_DRM_PB8 0x1172 |
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| 305 | +#define HDMI_FC_DRM_PB9 0x1173 |
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| 306 | +#define HDMI_FC_DRM_PB10 0x1174 |
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| 307 | +#define HDMI_FC_DRM_PB11 0x1175 |
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| 308 | +#define HDMI_FC_DRM_PB12 0x1176 |
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| 309 | +#define HDMI_FC_DRM_PB13 0x1177 |
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| 310 | +#define HDMI_FC_DRM_PB14 0x1178 |
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| 311 | +#define HDMI_FC_DRM_PB15 0x1179 |
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| 312 | +#define HDMI_FC_DRM_PB16 0x117A |
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| 313 | +#define HDMI_FC_DRM_PB17 0x117B |
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| 314 | +#define HDMI_FC_DRM_PB18 0x117C |
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| 315 | +#define HDMI_FC_DRM_PB19 0x117D |
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| 316 | +#define HDMI_FC_DRM_PB20 0x117E |
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| 317 | +#define HDMI_FC_DRM_PB21 0x117F |
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| 318 | +#define HDMI_FC_DRM_PB22 0x1180 |
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| 319 | +#define HDMI_FC_DRM_PB23 0x1181 |
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| 320 | +#define HDMI_FC_DRM_PB24 0x1182 |
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| 321 | +#define HDMI_FC_DRM_PB25 0x1183 |
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| 322 | +#define HDMI_FC_DRM_PB26 0x1184 |
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334 | 323 | |
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335 | 324 | #define HDMI_FC_DBGFORCE 0x1200 |
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336 | 325 | #define HDMI_FC_DBGAUD0CH0 0x1201 |
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.. | .. |
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807 | 796 | /* HDMI_FC_AUDSCHNLS7 field values */ |
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808 | 797 | HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, |
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809 | 798 | HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, |
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810 | | - HDMI_FC_AUDSCHNLS7_SAMPFREQ_OFFSET = 0, |
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811 | | - HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK = 0x0f, |
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812 | 799 | |
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813 | 800 | /* HDMI_FC_AUDSCHNLS8 field values */ |
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814 | 801 | HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, |
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815 | 802 | HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, |
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816 | 803 | HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, |
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817 | 804 | HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, |
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818 | | - |
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819 | | -/* HDMI_FC_AUDSCHNLS Sample Rate */ |
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820 | | - HDMI_FC_AUDSCHNLS_32K = 0x3, |
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821 | | - HDMI_FC_AUDSCHNLS_441K = 0x0, |
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822 | | - HDMI_FC_AUDSCHNLS_48K = 0x2, |
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823 | | - HDMI_FC_AUDSCHNLS_882K = 0x8, |
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824 | | - HDMI_FC_AUDSCHNLS_96K = 0xa, |
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825 | | - HDMI_FC_AUDSCHNLS_1764K = 0xc, |
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826 | | - HDMI_FC_AUDSCHNLS_192K = 0xe, |
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827 | 805 | |
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828 | 806 | /* FC_AUDSCONF field values */ |
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829 | 807 | HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, |
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.. | .. |
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855 | 833 | HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, |
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856 | 834 | |
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857 | 835 | /* FC_PACKET_TX_EN field values */ |
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858 | | - HDMI_FC_PACKET_DRM_TX_EN_MASK = 0x80, |
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859 | | - HDMI_FC_PACKET_DRM_TX_EN = 0x80, |
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860 | | - HDMI_FC_PACKET_DRM_TX_DEN = 0x00, |
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| 836 | + HDMI_FC_PACKET_TX_EN_DRM_MASK = 0x80, |
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| 837 | + HDMI_FC_PACKET_TX_EN_DRM_ENABLE = 0x80, |
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| 838 | + HDMI_FC_PACKET_TX_EN_DRM_DISABLE = 0x00, |
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861 | 839 | |
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862 | 840 | /* FC_AVICONF0-FC_AVICONF3 field values */ |
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863 | 841 | HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, |
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.. | .. |
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986 | 964 | |
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987 | 965 | /* AUD_CONF0 field values */ |
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988 | 966 | HDMI_AUD_CONF0_SW_RESET = 0x80, |
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989 | | - HDMI_AUD_CONF0_I2S_SELECT_MASK = 0x20, |
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990 | | - HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE = 0x21, |
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991 | | - HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE = 0x23, |
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992 | | - HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE = 0x27, |
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993 | | - HDMI_AUD_CONF0_I2S_8CHANNEL_ENABLE = 0x2F, |
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994 | | - HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F, |
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995 | | - |
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996 | | -/* AUD_INT field values */ |
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997 | | - HDMI_AUD_INT_FIFO_EMPTY_MSK = BIT(3), |
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998 | | - HDMI_AUD_INT_FIFO_FULL_MSK = BIT(2), |
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| 967 | + HDMI_AUD_CONF0_I2S_SELECT = 0x20, |
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| 968 | + HDMI_AUD_CONF0_I2S_EN3 = 0x08, |
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| 969 | + HDMI_AUD_CONF0_I2S_EN2 = 0x04, |
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| 970 | + HDMI_AUD_CONF0_I2S_EN1 = 0x02, |
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| 971 | + HDMI_AUD_CONF0_I2S_EN0 = 0x01, |
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999 | 972 | |
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1000 | 973 | /* AUD_CONF1 field values */ |
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1001 | 974 | HDMI_AUD_CONF1_MODE_I2S = 0x00, |
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1002 | | - HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02, |
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1003 | | - HDMI_AUD_CONF1_MODE_LEFT_J = 0x04, |
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| 975 | + HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20, |
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| 976 | + HDMI_AUD_CONF1_MODE_LEFT_J = 0x40, |
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| 977 | + HDMI_AUD_CONF1_MODE_BURST_1 = 0x60, |
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| 978 | + HDMI_AUD_CONF1_MODE_BURST_2 = 0x80, |
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1004 | 979 | HDMI_AUD_CONF1_WIDTH_16 = 0x10, |
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1005 | 980 | HDMI_AUD_CONF1_WIDTH_21 = 0x15, |
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1006 | 981 | HDMI_AUD_CONF1_WIDTH_24 = 0x18, |
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.. | .. |
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1074 | 1049 | HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, |
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1075 | 1050 | |
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1076 | 1051 | /* MC_SWRSTZ field values */ |
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| 1052 | + HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08, |
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1077 | 1053 | HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, |
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1078 | 1054 | |
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1079 | 1055 | /* MC_FLOWCTRL field values */ |
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.. | .. |
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1183 | 1159 | HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, |
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1184 | 1160 | HDMI_I2CM_DIV_FAST_MODE = 0x8, |
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1185 | 1161 | HDMI_I2CM_DIV_STD_MODE = 0, |
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1186 | | - |
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1187 | | -/* HDMI_MC_SWRSTZ filed values */ |
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1188 | | - HDMI_MC_SWRSTZ_I2S_RESET_MSK = BIT(3), |
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1189 | 1162 | }; |
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1190 | 1163 | |
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1191 | 1164 | /* |
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