~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,54 +1,52 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* DesignWare High-Definition Multimedia Interface (HDMI) driver
3	4	*
4	5	* Copyright (C) 2013-2015 Mentor Graphics Inc.
5	6	* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6	7	* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7		- *
8		- * This program is free software; you can redistribute it and/or modify
9		- * it under the terms of the GNU General Public License as published by
10		- * the Free Software Foundation; either version 2 of the License, or
11		- * (at your option) any later version.
12		- *
13	8	*/
14		-#include <linux/module.h>
15		-#include <linux/irq.h>
	9	+#include <linux/clk.h>
16	10	#include <linux/delay.h>
17	11	#include <linux/err.h>
18	12	#include <linux/extcon.h>
19	13	#include <linux/extcon-provider.h>
20		-#include <linux/clk.h>
21	14	#include <linux/hdmi.h>
	15	+#include <linux/irq.h>
	16	+#include <linux/module.h>
22	17	#include <linux/mutex.h>
23	18	#include <linux/of_device.h>
	19	+#include <linux/pinctrl/consumer.h>
24	20	#include <linux/regmap.h>
	21	+#include <linux/dma-mapping.h>
25	22	#include <linux/spinlock.h>
26	23	#include <linux/pinctrl/consumer.h>
27	24
28		-#include <drm/drm_of.h>
29		-#include <drm/drmP.h>
30		-#include <drm/drm_atomic.h>
31		-#include <drm/drm_atomic_helper.h>
32		-#include <drm/drm_crtc_helper.h>
33		-#include <drm/drm_edid.h>
34		-#include <drm/drm_encoder_slave.h>
35		-#include <drm/drm_scdc_helper.h>
36		-#include <drm/bridge/dw_hdmi.h>
	25	+#include <media/cec-notifier.h>
37	26
38	27	#include <uapi/linux/media-bus-format.h>
39	28	#include <uapi/linux/videodev2.h>
40	29
41		-#include "dw-hdmi.h"
	30	+#include <drm/bridge/dw_hdmi.h>
	31	+#include <drm/drm_atomic.h>
	32	+#include <drm/drm_atomic_helper.h>
	33	+#include <drm/drm_bridge.h>
	34	+#include <drm/drm_edid.h>
	35	+#include <drm/drm_of.h>
	36	+#include <drm/drm_print.h>
	37	+#include <drm/drm_probe_helper.h>
	38	+#include <drm/drm_scdc_helper.h>
	39	+
42	40	#include "dw-hdmi-audio.h"
43	41	#include "dw-hdmi-cec.h"
44	42	#include "dw-hdmi-hdcp.h"
45		-
46		-#include <media/cec-notifier.h>
	43	+#include "dw-hdmi.h"
47	44
48	45	#define DDC_CI_ADDR 0x37
49	46	#define DDC_SEGMENT_ADDR 0x30
50	47
51	48	#define HDMI_EDID_LEN 512
	49	+#define HDMI_EDID_BLOCK_LEN 128
52	50
53	51	/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
54	52	#define SCDC_MIN_SOURCE_VERSION 0x1
..	..	@@ -149,56 +147,20 @@
149	147
150	148	static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
151	149	{ 0x2591, 0x1322, 0x074b, 0x0000 },
152		- { 0xe535, 0x2000, 0xfacc, 0x0200 },
153		- { 0xeacd, 0xf534, 0x2000, 0x0200 }
154		-};
155		-
156		-static const u16 csc_coeff_rgb_in_eitu601_10bit[3][4] = {
157		- { 0x2591, 0x1322, 0x074b, 0x0000 },
158		- { 0xe535, 0x2000, 0xfacc, 0x0800 },
159		- { 0xeacd, 0xf534, 0x2000, 0x0800 }
160		-};
161		-
162		-static const u16 csc_coeff_rgb_in_eitu601_limited[3][4] = {
163		- { 0x2044, 0x106f, 0x0644, 0x0040 },
164		- { 0xe677, 0x1c1c, 0xfd46, 0x0200 },
165		- { 0xed60, 0xf685, 0x1c1c, 0x0200 }
166		-};
167		-
168		-static const u16 csc_coeff_rgb_in_eitu601_10bit_limited[3][4] = {
169		- { 0x2044, 0x106f, 0x0644, 0x0100 },
170		- { 0xe677, 0x1c1c, 0xfd46, 0x0800 },
171		- { 0xed60, 0xf685, 0x1c1c, 0x0800 }
	150	+ { 0x6535, 0x2000, 0x7acc, 0x0200 },
	151	+ { 0x6acd, 0x7534, 0x2000, 0x0200 }
172	152	};
173	153
174	154	static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
175	155	{ 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
176		- { 0xe2f0, 0x2000, 0xfd11, 0x0200 },
177		- { 0xe756, 0xf8ab, 0x2000, 0x0200 }
	156	+ { 0x62f0, 0x2000, 0x7d11, 0x0200 },
	157	+ { 0x6756, 0x78ab, 0x2000, 0x0200 }
178	158	};
179	159
180		-static const u16 csc_coeff_rgb_in_eitu709_10bit[3][4] = {
181		- { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
182		- { 0xe2f0, 0x2000, 0xfd11, 0x0800 },
183		- { 0xe756, 0xf8ab, 0x2000, 0x0800 }
184		-};
185		-
186		-static const u16 csc_coeff_rgb_in_eitu709_limited[3][4] = {
187		- { 0x2750, 0x0baf, 0x03f8, 0x0040 },
188		- { 0xe677, 0x1c1c, 0xfd6d, 0x0200 },
189		- { 0xea55, 0xf98f, 0x1c1c, 0x0200 }
190		-};
191		-
192		-static const u16 csc_coeff_rgb_in_eitu709_10bit_limited[3][4] = {
193		- { 0x2750, 0x0baf, 0x03f8, 0x0100 },
194		- { 0xe677, 0x1c1c, 0xfd6d, 0x0800 },
195		- { 0xea55, 0xf98f, 0x1c1c, 0x0800 }
196		-};
197		-
198		-static const u16 csc_coeff_full_to_limited[3][4] = {
199		- { 0x36f7, 0x0000, 0x0000, 0x0040 },
200		- { 0x0000, 0x36f7, 0x0000, 0x0040 },
201		- { 0x0000, 0x0000, 0x36f7, 0x0040 }
	160	+static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
	161	+ { 0x1b7c, 0x0000, 0x0000, 0x0020 },
	162	+ { 0x0000, 0x1b7c, 0x0000, 0x0020 },
	163	+ { 0x0000, 0x0000, 0x1b7c, 0x0020 }
202	164	};
203	165
204	166	static const struct drm_display_mode dw_hdmi_default_modes[] = {
..	..	@@ -206,36 +168,32 @@
206	168	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
207	169	1430, 1650, 0, 720, 725, 730, 750, 0,
208	170	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
209		- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
	171	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
210	172	/* 16 - 1920x1080@60Hz 16:9 */
211	173	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
212	174	2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
213	175	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
214		- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
	176	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
215	177	/* 31 - 1920x1080@50Hz 16:9 */
216	178	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
217	179	2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
218	180	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
219		- .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
	181	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
220	182	/* 19 - 1280x720@50Hz 16:9 */
221	183	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
222	184	1760, 1980, 0, 720, 725, 730, 750, 0,
223	185	DRM_MODE_FLAG_PHSYNC \| DRM_MODE_FLAG_PVSYNC),
224		- .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
225		- /* 0x10 - 1024x768@60Hz */
226		- { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
227		- 1184, 1344, 0, 768, 771, 777, 806, 0,
228		- DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC) },
	186	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
229	187	/* 17 - 720x576@50Hz 4:3 */
230	188	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
231	189	796, 864, 0, 576, 581, 586, 625, 0,
232	190	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
233		- .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
	191	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
234	192	/* 2 - 720x480@60Hz 4:3 */
235	193	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
236	194	798, 858, 0, 480, 489, 495, 525, 0,
237	195	DRM_MODE_FLAG_NHSYNC \| DRM_MODE_FLAG_NVSYNC),
238		- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
	196	+ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
239	197	};
240	198
241	199	struct hdmi_vmode {
..	..	@@ -257,7 +215,7 @@
257	215	unsigned int quant_range;
258	216	unsigned int pix_repet_factor;
259	217	struct hdmi_vmode video_mode;
260		- bool update;
	218	+ bool rgb_limited_range;
261	219	};
262	220
263	221	struct dw_hdmi_i2c {
..	..	@@ -303,6 +261,7 @@
303	261
304	262	struct hdmi_data_info hdmi_data;
305	263	const struct dw_hdmi_plat_data *plat_data;
	264	+ const struct dw_hdmi_cec_wake_ops *cec_ops;
306	265	struct dw_hdcp *hdcp;
307	266
308	267	int vic;
..	..	@@ -331,8 +290,13 @@
331	290	struct delayed_work work;
332	291	struct workqueue_struct *workqueue;
333	292
	293	+ struct pinctrl *pinctrl;
	294	+ struct pinctrl_state *default_state;
	295	+ struct pinctrl_state *unwedge_state;
	296	+
334	297	struct mutex mutex; /* for state below and previous_mode */
335	298	enum drm_connector_force force; /* mutex-protected force state */
	299	+ struct drm_connector curr_conn;/ current connector (only valid when !disabled) */
336	300	bool disabled; /* DRM has disabled our bridge */
337	301	bool bridge_is_on; /* indicates the bridge is on */
338	302	bool rxsense; /* rxsense state */
..	..	@@ -355,13 +319,17 @@
355	319	void (enable_audio)(struct dw_hdmi hdmi);
356	320	void (disable_audio)(struct dw_hdmi hdmi);
357	321
	322	+ struct mutex cec_notifier_mutex;
358	323	struct cec_notifier *cec_notifier;
	324	+ struct cec_adapter *cec_adap;
359	325
360		- bool initialized; /* hdmi is enabled before bind */
361	326	hdmi_codec_plugged_cb plugged_cb;
362	327	struct device *codec_dev;
363	328	enum drm_connector_status last_connector_result;
364		- bool rgb_quant_range_selectable;
	329	+ bool initialized; /* hdmi is enabled before bind */
	330	+ bool logo_plug_out; /* hdmi is plug out when kernel logo */
	331	+ bool update;
	332	+ bool hdr2sdr; /* from hdr to sdr */
365	333	};
366	334
367	335	#define HDMI_IH_PHY_STAT0_RX_SENSE \
..	..	@@ -441,6 +409,8 @@
441	409	static void repo_hpd_event(struct work_struct *p_work)
442	410	{
443	411	struct dw_hdmi *hdmi = container_of(p_work, struct dw_hdmi, work.work);
	412	+ enum drm_connector_status status = hdmi->hpd_state ?
	413	+ connector_status_connected : connector_status_disconnected;
444	414	u8 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
445	415
446	416	mutex_lock(&hdmi->mutex);
..	..	@@ -455,12 +425,12 @@
455	425
456	426	change = drm_helper_hpd_irq_event(hdmi->bridge.dev);
457	427
458		-#ifdef CONFIG_CEC_NOTIFIER
459		- if (change)
460		- cec_notifier_repo_cec_hpd(hdmi->cec_notifier,
461		- hdmi->hpd_state,
462		- ktime_get());
463		-#endif
	428	+ if (change && hdmi->cec_adap &&
	429	+ hdmi->cec_adap->devnode.registered)
	430	+ cec_queue_pin_hpd_event(hdmi->cec_adap,
	431	+ hdmi->hpd_state,
	432	+ ktime_get());
	433	+ drm_bridge_hpd_notify(&hdmi->bridge, status);
464	434	}
465	435	}
466	436
..	..	@@ -538,6 +508,13 @@
538	508
539	509	static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
540	510	{
	511	+ hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
	512	+ HDMI_PHY_I2CM_INT_ADDR);
	513	+
	514	+ hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL \|
	515	+ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
	516	+ HDMI_PHY_I2CM_CTLINT_ADDR);
	517	+
541	518	/* Software reset */
542	519	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
543	520
..	..	@@ -564,11 +541,83 @@
564	541	dw_hdmi_i2c_set_divs(hdmi);
565	542	}
566	543
	544	+static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
	545	+{
	546	+ /* If no unwedge state then give up */
	547	+ if (!hdmi->unwedge_state)
	548	+ return false;
	549	+
	550	+ dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
	551	+
	552	+ /*
	553	+ * This is a huge hack to workaround a problem where the dw_hdmi i2c
	554	+ * bus could sometimes get wedged. Once wedged there doesn't appear
	555	+ * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
	556	+ * other than pulsing the SDA line.
	557	+ *
	558	+ * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
	559	+ * by:
	560	+ * 1. Remux the pin as a GPIO output, driven low.
	561	+ * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
	562	+ * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
	563	+ *
	564	+ * At the moment of remuxing, the line will still be low due to its
	565	+ * recent stint as an output, but then it will be pulled high by the
	566	+ * (presumed) external pullup. dw_hdmi seems to see this as a rising
	567	+ * edge and that seems to get it out of its jam.
	568	+ *
	569	+ * This wedging was only ever seen on one TV, and only on one of
	570	+ * its HDMI ports. It happened when the TV was powered on while the
	571	+ * device was plugged in. A scope trace shows the TV bringing both SDA
	572	+ * and SCL low, then bringing them both back up at roughly the same
	573	+ * time. Presumably this confuses dw_hdmi because it saw activity but
	574	+ * no real STOP (maybe it thinks there's another master on the bus?).
	575	+ * Giving it a clean rising edge of SDA while SCL is already high
	576	+ * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
	577	+ * of its stupor.
	578	+ *
	579	+ * Note that after coming back alive, transfers seem to immediately
	580	+ * resume, so if we unwedge due to a timeout we should wait a little
	581	+ * longer for our transfer to finish, since it might have just started
	582	+ * now.
	583	+ */
	584	+ pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
	585	+ msleep(10);
	586	+ pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
	587	+
	588	+ return true;
	589	+}
	590	+
	591	+static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
	592	+{
	593	+ struct dw_hdmi_i2c *i2c = hdmi->i2c;
	594	+ int stat;
	595	+
	596	+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
	597	+ if (!stat) {
	598	+ /* If we can't unwedge, return timeout */
	599	+ if (!dw_hdmi_i2c_unwedge(hdmi))
	600	+ return -EAGAIN;
	601	+
	602	+ /* We tried to unwedge; give it another chance */
	603	+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
	604	+ if (!stat)
	605	+ return -EAGAIN;
	606	+ }
	607	+
	608	+ /* Check for error condition on the bus */
	609	+ if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
	610	+ return -EIO;
	611	+
	612	+ return 0;
	613	+}
	614	+
567	615	static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
568	616	unsigned char *buf, unsigned int length)
569	617	{
570	618	struct dw_hdmi_i2c *i2c = hdmi->i2c;
571		- int stat;
	619	+ int ret, retry, i;
	620	+ bool read_edid = false;
572	621
573	622	if (!i2c->is_regaddr) {
574	623	dev_dbg(hdmi->dev, "set read register address to 0\n");
..	..	@@ -576,27 +625,80 @@
576	625	i2c->is_regaddr = true;
577	626	}
578	627
579		- while (length--) {
580		- reinit_completion(&i2c->cmp);
	628	+ /* edid reads are in 128 bytes. scdc reads are in 1 byte */
	629	+ if (length == HDMI_EDID_BLOCK_LEN)
	630	+ read_edid = true;
581	631
582		- hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
583		- if (i2c->is_segment)
584		- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
585		- HDMI_I2CM_OPERATION);
586		- else
587		- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
588		- HDMI_I2CM_OPERATION);
	632	+ while (length > 0) {
	633	+ retry = 100;
	634	+ hdmi_writeb(hdmi, i2c->slave_reg, HDMI_I2CM_ADDRESS);
589	635
590		- stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
591		- if (!stat)
592		- return -EAGAIN;
	636	+ if (read_edid) {
	637	+ i2c->slave_reg += 8;
	638	+ length -= 8;
	639	+ } else {
	640	+ i2c->slave_reg++;
	641	+ length--;
	642	+ }
593	643
594		- /* Check for error condition on the bus */
595		- if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
	644	+ while (retry > 0) {
	645	+ if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD)) {
	646	+ void *data = hdmi->plat_data->phy_data;
	647	+
	648	+ dev_dbg(hdmi->dev, "hdmi disconnect, stop ddc read\n");
	649	+ if (hdmi->plat_data->set_ddc_io)
	650	+ hdmi->plat_data->set_ddc_io(data, false);
	651	+ return -EPERM;
	652	+ }
	653	+
	654	+ if (i2c->is_segment) {
	655	+ if (read_edid)
	656	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT,
	657	+ HDMI_I2CM_OPERATION);
	658	+ else
	659	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
	660	+ HDMI_I2CM_OPERATION);
	661	+ } else {
	662	+ if (read_edid)
	663	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8,
	664	+ HDMI_I2CM_OPERATION);
	665	+ else
	666	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
	667	+ HDMI_I2CM_OPERATION);
	668	+ }
	669	+
	670	+ ret = dw_hdmi_i2c_wait(hdmi);
	671	+ if (ret == -EAGAIN) {
	672	+ dev_dbg(hdmi->dev, "ddc read time out\n");
	673	+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
	674	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
	675	+ HDMI_I2CM_OPERATION);
	676	+ retry -= 10;
	677	+ continue;
	678	+ } else if (ret == -EIO) {
	679	+ dev_dbg(hdmi->dev, "ddc read err\n");
	680	+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
	681	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
	682	+ HDMI_I2CM_OPERATION);
	683	+ retry--;
	684	+ usleep_range(10000, 11000);
	685	+ continue;
	686	+ }
	687	+ /* read success */
	688	+ break;
	689	+ }
	690	+ if (retry <= 0) {
	691	+ dev_err(hdmi->dev, "ddc read failed\n");
596	692	return -EIO;
	693	+ }
597	694
598		- *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
	695	+ if (read_edid)
	696	+ for (i = 0; i < 8; i++)
	697	+ *buf++ = hdmi_readb(hdmi, HDMI_I2CM_READ_BUFF0 + i);
	698	+ else
	699	+ *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
599	700	}
	701	+
600	702	i2c->is_segment = false;
601	703
602	704	return 0;
..	..	@@ -606,7 +708,7 @@
606	708	unsigned char *buf, unsigned int length)
607	709	{
608	710	struct dw_hdmi_i2c *i2c = hdmi->i2c;
609		- int stat;
	711	+ int ret, retry;
610	712
611	713	if (!i2c->is_regaddr) {
612	714	/* Use the first write byte as register address */
..	..	@@ -617,20 +719,51 @@
617	719	}
618	720
619	721	while (length--) {
620		- reinit_completion(&i2c->cmp);
	722	+ retry = 100;
621	723
622	724	hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
623	725	hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
624		- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
625		- HDMI_I2CM_OPERATION);
626	726
627		- stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
628		- if (!stat)
629		- return -EAGAIN;
	727	+ while (retry > 0) {
	728	+ if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD)) {
	729	+ void *data = hdmi->plat_data->phy_data;
630	730
631		- /* Check for error condition on the bus */
632		- if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
	731	+ dev_dbg(hdmi->dev, "hdmi disconnect, stop ddc write\n");
	732	+ if (hdmi->plat_data->set_ddc_io)
	733	+ hdmi->plat_data->set_ddc_io(data, false);
	734	+ return -EPERM;
	735	+ }
	736	+
	737	+ reinit_completion(&i2c->cmp);
	738	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
	739	+ HDMI_I2CM_OPERATION);
	740	+
	741	+ ret = dw_hdmi_i2c_wait(hdmi);
	742	+ if (ret == -EAGAIN) {
	743	+ dev_dbg(hdmi->dev, "ddc write time out\n");
	744	+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
	745	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
	746	+ HDMI_I2CM_OPERATION);
	747	+ retry -= 10;
	748	+ continue;
	749	+ } else if (ret == -EIO) {
	750	+ dev_dbg(hdmi->dev, "ddc write err\n");
	751	+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
	752	+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
	753	+ HDMI_I2CM_OPERATION);
	754	+ retry--;
	755	+ usleep_range(10000, 11000);
	756	+ continue;
	757	+ }
	758	+
	759	+ /* write success */
	760	+ break;
	761	+ }
	762	+
	763	+ if (retry <= 0) {
	764	+ dev_err(hdmi->dev, "ddc write failed\n");
633	765	return -EIO;
	766	+ }
634	767	}
635	768
636	769	return 0;
..	..	@@ -642,6 +775,7 @@
642	775	struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
643	776	struct dw_hdmi_i2c *i2c = hdmi->i2c;
644	777	u8 addr = msgs[0].addr;
	778	+ void *data = hdmi->plat_data->phy_data;
645	779	int i, ret = 0;
646	780
647	781	if (addr == DDC_CI_ADDR)
..	..	@@ -665,6 +799,12 @@
665	799	}
666	800
667	801	mutex_lock(&i2c->lock);
	802	+
	803	+ if (hdmi->plat_data->set_ddc_io)
	804	+ hdmi->plat_data->set_ddc_io(data, true);
	805	+
	806	+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
	807	+ udelay(100);
668	808
669	809	/* Unmute DONE and ERROR interrupts */
670	810	hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
..	..	@@ -765,8 +905,14 @@
765	905	/* nshift factor = 0 */
766	906	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
767	907
768		- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) \|
769		- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
	908	+ /* Use automatic CTS generation mode when CTS is not set */
	909	+ if (cts)
	910	+ hdmi_writeb(hdmi, ((cts >> 16) &
	911	+ HDMI_AUD_CTS3_AUDCTS19_16_MASK) \|
	912	+ HDMI_AUD_CTS3_CTS_MANUAL,
	913	+ HDMI_AUD_CTS3);
	914	+ else
	915	+ hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
770	916	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
771	917	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
772	918
..	..	@@ -888,29 +1034,58 @@
888	1034	return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
889	1035	}
890	1036
	1037	+/*
	1038	+ * When transmitting IEC60958 linear PCM audio, these registers allow to
	1039	+ * configure the channel status information of all the channel status
	1040	+ * bits in the IEC60958 frame. For the moment this configuration is only
	1041	+ * used when the I2S audio interface, General Purpose Audio (GPA),
	1042	+ * or AHB audio DMA (AHBAUDDMA) interface is active
	1043	+ * (for S/PDIF interface this information comes from the stream).
	1044	+ */
	1045	+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
	1046	+ u8 *channel_status)
	1047	+{
	1048	+ /*
	1049	+ * Set channel status register for frequency and word length.
	1050	+ * Use default values for other registers.
	1051	+ */
	1052	+ hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
	1053	+ hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
	1054	+}
	1055	+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
	1056	+
891	1057	static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
892	1058	unsigned long pixel_clk, unsigned int sample_rate)
893	1059	{
894	1060	unsigned long ftdms = pixel_clk;
895	1061	unsigned int n, cts;
	1062	+ u8 config3;
896	1063	u64 tmp;
897	1064
898	1065	n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
899	1066
900		- /*
901		- * Compute the CTS value from the N value. Note that CTS and N
902		- * can be up to 20 bits in total, so we need 64-bit math. Also
903		- * note that our TDMS clock is not fully accurate; it is accurate
904		- * to kHz. This can introduce an unnecessary remainder in the
905		- * calculation below, so we don't try to warn about that.
906		- */
907		- tmp = (u64)ftdms * n;
908		- do_div(tmp, 128 * sample_rate);
909		- cts = tmp;
	1067	+ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
910	1068
911		- dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
912		- __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
913		- n, cts);
	1069	+ /* Only compute CTS when using internal AHB audio */
	1070	+ if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
	1071	+ /*
	1072	+ * Compute the CTS value from the N value. Note that CTS and N
	1073	+ * can be up to 20 bits in total, so we need 64-bit math. Also
	1074	+ * note that our TDMS clock is not fully accurate; it is
	1075	+ * accurate to kHz. This can introduce an unnecessary remainder
	1076	+ * in the calculation below, so we don't try to warn about that.
	1077	+ */
	1078	+ tmp = (u64)ftdms * n;
	1079	+ do_div(tmp, 128 * sample_rate);
	1080	+ cts = tmp;
	1081	+
	1082	+ dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
	1083	+ __func__, sample_rate,
	1084	+ ftdms / 1000000, (ftdms / 1000) % 1000,
	1085	+ n, cts);
	1086	+ } else {
	1087	+ cts = 0;
	1088	+ }
914	1089
915	1090	spin_lock_irq(&hdmi->audio_lock);
916	1091	hdmi->audio_n = n;
..	..	@@ -944,6 +1119,42 @@
944	1119	}
945	1120	EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
946	1121
	1122	+void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
	1123	+{
	1124	+ u8 layout;
	1125	+
	1126	+ mutex_lock(&hdmi->audio_mutex);
	1127	+
	1128	+ /*
	1129	+ * For >2 channel PCM audio, we need to select layout 1
	1130	+ * and set an appropriate channel map.
	1131	+ */
	1132	+ if (cnt > 2)
	1133	+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
	1134	+ else
	1135	+ layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
	1136	+
	1137	+ hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
	1138	+ HDMI_FC_AUDSCONF);
	1139	+
	1140	+ /* Set the audio infoframes channel count */
	1141	+ hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
	1142	+ HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
	1143	+
	1144	+ mutex_unlock(&hdmi->audio_mutex);
	1145	+}
	1146	+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
	1147	+
	1148	+void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
	1149	+{
	1150	+ mutex_lock(&hdmi->audio_mutex);
	1151	+
	1152	+ hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
	1153	+
	1154	+ mutex_unlock(&hdmi->audio_mutex);
	1155	+}
	1156	+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
	1157	+
947	1158	static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
948	1159	{
949	1160	if (enable)
..	..	@@ -951,6 +1162,14 @@
951	1162	else
952	1163	hdmi->mc_clkdis \|= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
953	1164	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
	1165	+}
	1166	+
	1167	+static u8 hdmi_audio_get_eld(struct dw_hdmi hdmi)
	1168	+{
	1169	+ if (!hdmi->curr_conn)
	1170	+ return NULL;
	1171	+
	1172	+ return hdmi->curr_conn->eld;
954	1173	}
955	1174
956	1175	static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
..	..	@@ -1161,25 +1380,14 @@
1161	1380
1162	1381	static int is_color_space_conversion(struct dw_hdmi *hdmi)
1163	1382	{
1164		- const struct drm_display_mode mode = hdmi->previous_mode;
1165		- bool is_cea_default;
	1383	+ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
	1384	+ bool is_input_rgb, is_output_rgb;
1166	1385
1167		- is_cea_default = (drm_match_cea_mode(&mode) > 1) &&
1168		- (hdmi->hdmi_data.quant_range ==
1169		- HDMI_QUANTIZATION_RANGE_DEFAULT);
	1386	+ is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
	1387	+ is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
1170	1388
1171		- /*
1172		- * When output is rgb limited range or default range with
1173		- * cea mode, csc should be enabled.
1174		- */
1175		- if (hdmi->hdmi_data.enc_in_bus_format !=
1176		- hdmi->hdmi_data.enc_out_bus_format \|\|
1177		- ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED \|\|
1178		- is_cea_default) &&
1179		- hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format)))
1180		- return 1;
1181		-
1182		- return 0;
	1389	+ return (is_input_rgb != is_output_rgb) \|\|
	1390	+ (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
1183	1391	}
1184	1392
1185	1393	static int is_color_space_decimation(struct dw_hdmi *hdmi)
..	..	@@ -1206,43 +1414,46 @@
1206	1414	return 0;
1207	1415	}
1208	1416
	1417	+static bool is_csc_needed(struct dw_hdmi *hdmi)
	1418	+{
	1419	+ return is_color_space_conversion(hdmi) \|\|
	1420	+ is_color_space_decimation(hdmi) \|\|
	1421	+ is_color_space_interpolation(hdmi);
	1422	+}
	1423	+
	1424	+static bool is_rgb_full_to_limited_needed(struct dw_hdmi *hdmi)
	1425	+{
	1426	+ if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED \|\|
	1427	+ (!hdmi->hdmi_data.quant_range && hdmi->hdmi_data.rgb_limited_range))
	1428	+ return true;
	1429	+
	1430	+ return false;
	1431	+}
	1432	+
1209	1433	static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1210	1434	{
1211	1435	const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
	1436	+ bool is_input_rgb, is_output_rgb;
1212	1437	unsigned i;
1213	1438	u32 csc_scale = 1;
1214		- int enc_out_rgb, enc_in_rgb;
1215		- int color_depth;
1216	1439
1217		- enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1218		- enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1219		- color_depth = hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
	1440	+ is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
	1441	+ is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1220	1442
1221		- if (is_color_space_conversion(hdmi)) {
1222		- if (enc_out_rgb && enc_in_rgb) {
1223		- csc_coeff = &csc_coeff_full_to_limited;
1224		- csc_scale = 0;
1225		- } else if (enc_out_rgb) {
1226		- if (hdmi->hdmi_data.enc_out_encoding ==
1227		- V4L2_YCBCR_ENC_601)
1228		- csc_coeff = &csc_coeff_rgb_out_eitu601;
1229		- else
1230		- csc_coeff = &csc_coeff_rgb_out_eitu709;
1231		- } else if (enc_in_rgb) {
1232		- if (hdmi->hdmi_data.enc_out_encoding ==
1233		- V4L2_YCBCR_ENC_601) {
1234		- if (color_depth == 10)
1235		- csc_coeff = &csc_coeff_rgb_in_eitu601_10bit_limited;
1236		- else
1237		- csc_coeff = &csc_coeff_rgb_in_eitu601_limited;
1238		- } else {
1239		- if (color_depth == 10)
1240		- csc_coeff = &csc_coeff_rgb_in_eitu709_10bit_limited;
1241		- else
1242		- csc_coeff = &csc_coeff_rgb_in_eitu709_limited;
1243		- }
1244		- csc_scale = 0;
1245		- }
	1443	+ if (!is_input_rgb && is_output_rgb) {
	1444	+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
	1445	+ csc_coeff = &csc_coeff_rgb_out_eitu601;
	1446	+ else
	1447	+ csc_coeff = &csc_coeff_rgb_out_eitu709;
	1448	+ } else if (is_input_rgb && !is_output_rgb) {
	1449	+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
	1450	+ csc_coeff = &csc_coeff_rgb_in_eitu601;
	1451	+ else
	1452	+ csc_coeff = &csc_coeff_rgb_in_eitu709;
	1453	+ csc_scale = 0;
	1454	+ } else if (is_input_rgb && is_output_rgb &&
	1455	+ is_rgb_full_to_limited_needed(hdmi)) {
	1456	+ csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1246	1457	}
1247	1458
1248	1459	/* The CSC registers are sequential, alternating MSB then LSB */
..	..	@@ -1378,14 +1589,7 @@
1378	1589	HDMI_VP_CONF_PR_EN_MASK \|
1379	1590	HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1380	1591
1381		- if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) \|\|
1382		- (color_depth == 6 && hdmi->previous_mode.htotal % 2))
1383		- hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
1384		- HDMI_VP_STUFF);
1385		- else
1386		- hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1387		- HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1388		-
	1592	+ hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1389	1593	hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1390	1594
1391	1595	if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
..	..	@@ -1457,30 +1661,16 @@
1457	1661	}
1458	1662	EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1459	1663
1460		-static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1461		-{
1462		- int val;
1463		-
1464		- hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1465		- hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1466		- hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1467		- hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1468		- hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1469		- HDMI_PHY_I2CM_OPERATION_ADDR);
1470		- hdmi_phy_wait_i2c_done(hdmi, 1000);
1471		- val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1472		- val = (val & 0xff) << 8;
1473		- val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1474		- return val;
1475		-}
1476		-
1477	1664	/* Filter out invalid setups to avoid configuring SCDC and scrambling */
1478		-static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
	1665	+static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
	1666	+ const struct drm_display_info *display)
1479	1667	{
1480		- struct drm_display_info *display = &hdmi->connector.display_info;
1481		-
1482	1668	/* Completely disable SCDC support for older controllers */
1483	1669	if (hdmi->version < 0x200a)
	1670	+ return false;
	1671	+
	1672	+ /* Disable if no DDC bus */
	1673	+ if (!hdmi->ddc)
1484	1674	return false;
1485	1675
1486	1676	/* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
..	..	@@ -1499,6 +1689,23 @@
1499	1689	return true;
1500	1690	}
1501	1691
	1692	+static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
	1693	+{
	1694	+ int val;
	1695	+
	1696	+ hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
	1697	+ hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
	1698	+ hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
	1699	+ hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
	1700	+ hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
	1701	+ HDMI_PHY_I2CM_OPERATION_ADDR);
	1702	+ hdmi_phy_wait_i2c_done(hdmi, 1000);
	1703	+ val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
	1704	+ val = (val & 0xff) << 8;
	1705	+ val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
	1706	+ return val;
	1707	+}
	1708	+
1502	1709	/*
1503	1710	* HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1504	1711	* - The Source shall suspend transmission of the TMDS clock and data
..	..	@@ -1512,12 +1719,13 @@
1512	1719	* helper should called right before enabling the TMDS Clock and Data in
1513	1720	* the PHY configuration callback.
1514	1721	*/
1515		-void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
	1722	+void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
	1723	+ const struct drm_display_info *display)
1516	1724	{
1517	1725	unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1518	1726
1519	1727	/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1520		- if (dw_hdmi_support_scdc(hdmi)) {
	1728	+ if (dw_hdmi_support_scdc(hdmi, display)) {
1521	1729	if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1522	1730	drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1523	1731	else
..	..	@@ -1730,7 +1938,8 @@
1730	1938	return 0;
1731	1939	}
1732	1940
1733		-static int hdmi_phy_configure(struct dw_hdmi *hdmi)
	1941	+static int hdmi_phy_configure(struct dw_hdmi *hdmi,
	1942	+ const struct drm_display_info *display)
1734	1943	{
1735	1944	const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1736	1945	const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
..	..	@@ -1740,7 +1949,7 @@
1740	1949
1741	1950	dw_hdmi_phy_power_off(hdmi);
1742	1951
1743		- dw_hdmi_set_high_tmds_clock_ratio(hdmi);
	1952	+ dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1744	1953
1745	1954	/* Leave low power consumption mode by asserting SVSRET. */
1746	1955	if (phy->has_svsret)
..	..	@@ -1754,7 +1963,7 @@
1754	1963
1755	1964	/* Write to the PHY as configured by the platform */
1756	1965	if (pdata->configure_phy)
1757		- ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
	1966	+ ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1758	1967	else
1759	1968	ret = phy->configure(hdmi, pdata, mpixelclock);
1760	1969	if (ret) {
..	..	@@ -1771,7 +1980,8 @@
1771	1980	}
1772	1981
1773	1982	static int dw_hdmi_phy_init(struct dw_hdmi hdmi, void data,
1774		- struct drm_display_mode *mode)
	1983	+ const struct drm_display_info *display,
	1984	+ const struct drm_display_mode *mode)
1775	1985	{
1776	1986	int i, ret;
1777	1987
..	..	@@ -1780,7 +1990,7 @@
1780	1990	dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1781	1991	dw_hdmi_phy_sel_interface_control(hdmi, 0);
1782	1992
1783		- ret = hdmi_phy_configure(hdmi);
	1993	+ ret = hdmi_phy_configure(hdmi, display);
1784	1994	if (ret)
1785	1995	return ret;
1786	1996	}
..	..	@@ -1883,23 +2093,35 @@
1883	2093	hdmi->hdcp->hdcp_start(hdmi->hdcp);
1884	2094	}
1885	2095
1886		-static void hdmi_config_AVI(struct dw_hdmi hdmi, struct drm_display_mode mode)
	2096	+static void hdmi_config_AVI(struct dw_hdmi *hdmi,
	2097	+ const struct drm_connector *connector,
	2098	+ const struct drm_display_mode *mode)
1887	2099	{
1888	2100	struct hdmi_avi_infoframe frame;
1889	2101	u8 val;
1890		- bool is_hdmi2 = false;
1891		- enum hdmi_quantization_range rgb_quant_range =
1892		- hdmi->hdmi_data.quant_range;
	2102	+ bool is_hdmi2;
	2103	+ const struct drm_display_info *info = &connector->display_info;
1893	2104
1894		- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) \|\|
1895		- hdmi->connector.display_info.hdmi.scdc.supported)
1896		- is_hdmi2 = true;
	2105	+ is_hdmi2 = info->hdmi.scdc.supported \|\| (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
	2106	+
1897	2107	/* Initialise info frame from DRM mode */
1898		- drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
	2108	+ drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1899	2109
1900		- drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range,
1901		- hdmi->rgb_quant_range_selectable \|\| is_hdmi2,
1902		- is_hdmi2);
	2110	+ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
	2111	+ /* default range */
	2112	+ if (!hdmi->hdmi_data.quant_range)
	2113	+ drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
	2114	+ hdmi->hdmi_data.rgb_limited_range ?
	2115	+ HDMI_QUANTIZATION_RANGE_LIMITED :
	2116	+ HDMI_QUANTIZATION_RANGE_FULL);
	2117	+ else
	2118	+ drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
	2119	+ hdmi->hdmi_data.quant_range);
	2120	+ } else {
	2121	+ frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
	2122	+ frame.ycc_quantization_range =
	2123	+ HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
	2124	+ }
1903	2125
1904	2126	if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1905	2127	frame.colorspace = HDMI_COLORSPACE_YUV444;
..	..	@@ -1935,21 +2157,31 @@
1935	2157	else
1936	2158	frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1937	2159	frame.extended_colorimetry =
1938		- HDMI_EXTENDED_COLORIMETRY_BT2020;
1939		- break;
	2160	+ HDMI_EXTENDED_COLORIMETRY_BT2020;
	2161	+ break;
1940	2162	default: /* Carries no data */
1941	2163	frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1942	2164	frame.extended_colorimetry =
1943	2165	HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1944	2166	break;
1945	2167	}
	2168	+ frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1946	2169	} else {
1947		- frame.colorimetry = HDMI_COLORIMETRY_NONE;
1948		- frame.extended_colorimetry =
1949		- HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1950		- }
	2170	+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_BT2020) {
	2171	+ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
	2172	+ frame.extended_colorimetry =
	2173	+ HDMI_EXTENDED_COLORIMETRY_BT2020;
	2174	+ } else {
	2175	+ frame.colorimetry = HDMI_COLORIMETRY_NONE;
	2176	+ frame.extended_colorimetry =
	2177	+ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
	2178	+ }
1951	2179
1952		- frame.scan_mode = HDMI_SCAN_MODE_NONE;
	2180	+ if (is_hdmi2 && frame.quantization_range == HDMI_QUANTIZATION_RANGE_FULL)
	2181	+ frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_FULL;
	2182	+ else
	2183	+ frame.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
	2184	+ }
1953	2185
1954	2186	/*
1955	2187	* The Designware IP uses a different byte format from standard
..	..	@@ -1986,7 +2218,11 @@
1986	2218	hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1987	2219
1988	2220	/* AVI data byte 4 differences: none */
1989		- val = frame.video_code & 0x7f;
	2221	+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) \|\|
	2222	+ hdmi->connector.display_info.hdmi.scdc.supported)
	2223	+ val = hdmi->vic;
	2224	+ else
	2225	+ val = frame.video_code & 0x7f;
1990	2226	hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1991	2227
1992	2228	/* AVI Data Byte 5- set up input and output pixel repetition */
..	..	@@ -2018,11 +2254,20 @@
2018	2254	}
2019	2255
2020	2256	static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
2021		- struct drm_display_mode *mode)
	2257	+ const struct drm_connector *connector,
	2258	+ const struct drm_display_mode *mode)
2022	2259	{
2023	2260	struct hdmi_vendor_infoframe frame;
2024	2261	u8 buffer[10];
2025	2262	ssize_t err;
	2263	+
	2264	+ /* if sink support hdmi2.0, don't send vsi */
	2265	+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) \|\|
	2266	+ hdmi->connector.display_info.hdmi.scdc.supported) {
	2267	+ hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
	2268	+ HDMI_FC_DATAUTO0_VSD_MASK);
	2269	+ return;
	2270	+ }
2026	2271
2027	2272	err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
2028	2273	&hdmi->connector,
..	..	@@ -2071,6 +2316,77 @@
2071	2316	HDMI_FC_DATAUTO0_VSD_MASK);
2072	2317	}
2073	2318
	2319	+static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
	2320	+ const struct drm_connector *connector)
	2321	+{
	2322	+ const struct drm_connector_state *conn_state = connector->state;
	2323	+ struct hdr_output_metadata *hdr_metadata;
	2324	+ struct hdmi_drm_infoframe frame;
	2325	+ u8 buffer[30];
	2326	+ ssize_t err;
	2327	+ int i;
	2328	+
	2329	+ /* Dynamic Range and Mastering Infoframe is introduced in v2.11a. */
	2330	+ if (hdmi->version < 0x211a) {
	2331	+ DRM_ERROR("Not support DRM Infoframe\n");
	2332	+ return;
	2333	+ }
	2334	+
	2335	+ if (!hdmi->plat_data->use_drm_infoframe)
	2336	+ return;
	2337	+
	2338	+ hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
	2339	+ HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
	2340	+
	2341	+ if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
	2342	+ DRM_DEBUG("No need to set HDR metadata in infoframe\n");
	2343	+ return;
	2344	+ }
	2345	+
	2346	+ if (!conn_state->hdr_output_metadata) {
	2347	+ DRM_DEBUG("source metadata not set yet\n");
	2348	+ return;
	2349	+ }
	2350	+
	2351	+ hdr_metadata = (struct hdr_output_metadata *)
	2352	+ conn_state->hdr_output_metadata->data;
	2353	+
	2354	+ if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
	2355	+ BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
	2356	+ DRM_ERROR("Not support EOTF %d\n",
	2357	+ hdr_metadata->hdmi_metadata_type1.eotf);
	2358	+ return;
	2359	+ }
	2360	+
	2361	+ err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
	2362	+ if (err < 0)
	2363	+ return;
	2364	+
	2365	+ err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
	2366	+ if (err < 0) {
	2367	+ dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
	2368	+ return;
	2369	+ }
	2370	+
	2371	+ hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
	2372	+ hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
	2373	+
	2374	+ for (i = 0; i < frame.length; i++)
	2375	+ hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
	2376	+
	2377	+ hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
	2378	+ /*
	2379	+ * avi and hdr infoframe cannot be sent at the same time
	2380	+ * for compatibility with Huawei TV
	2381	+ */
	2382	+ msleep(300);
	2383	+ hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
	2384	+ HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
	2385	+
	2386	+ DRM_DEBUG("%s eotf %d end\n", __func__,
	2387	+ hdr_metadata->hdmi_metadata_type1.eotf);
	2388	+}
	2389	+
2074	2390	static unsigned int
2075	2391	hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock)
2076	2392	{
..	..	@@ -2097,109 +2413,12 @@
2097	2413	return tmdsclock;
2098	2414	}
2099	2415
2100		-#define HDR_LSB(n) ((n) & 0xff)
2101		-#define HDR_MSB(n) (((n) & 0xff00) >> 8)
2102		-
2103		-/* Set Dynamic Range and Mastering Infoframe */
2104		-static void hdmi_config_hdr_infoframe(struct dw_hdmi *hdmi)
2105		-{
2106		- struct hdmi_drm_infoframe frame;
2107		- struct hdr_output_metadata *hdr_metadata;
2108		- struct drm_connector_state *conn_state = hdmi->connector.state;
2109		- int ret;
2110		-
2111		- /* Dynamic Range and Mastering Infoframe is introduced in v2.11a. */
2112		- if (hdmi->version < 0x211a) {
2113		- DRM_ERROR("Not support DRM Infoframe\n");
2114		- return;
2115		- }
2116		-
2117		- hdmi_modb(hdmi, HDMI_FC_PACKET_DRM_TX_DEN,
2118		- HDMI_FC_PACKET_DRM_TX_EN_MASK, HDMI_FC_PACKET_TX_EN);
2119		-
2120		- if (!hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf) {
2121		- DRM_DEBUG("No need to set HDR metadata in infoframe\n");
2122		- return;
2123		- }
2124		-
2125		- if (!conn_state->hdr_output_metadata) {
2126		- DRM_DEBUG("source metadata not set yet\n");
2127		- return;
2128		- }
2129		-
2130		- hdr_metadata = (struct hdr_output_metadata *)
2131		- conn_state->hdr_output_metadata->data;
2132		-
2133		- if (!(hdmi->connector.hdr_sink_metadata.hdmi_type1.eotf &
2134		- BIT(hdr_metadata->hdmi_metadata_type1.eotf))) {
2135		- DRM_ERROR("Not support EOTF %d\n",
2136		- hdr_metadata->hdmi_metadata_type1.eotf);
2137		- return;
2138		- }
2139		-
2140		- ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
2141		- if (ret < 0) {
2142		- DRM_ERROR("couldn't set HDR metadata in infoframe\n");
2143		- return;
2144		- }
2145		-
2146		- hdmi_writeb(hdmi, 1, HDMI_FC_DRM_HB0);
2147		- hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
2148		- hdmi_writeb(hdmi, frame.eotf, HDMI_FC_DRM_PB0);
2149		- hdmi_writeb(hdmi, frame.metadata_type, HDMI_FC_DRM_PB1);
2150		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[0].x),
2151		- HDMI_FC_DRM_PB2);
2152		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[0].x),
2153		- HDMI_FC_DRM_PB3);
2154		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[0].y),
2155		- HDMI_FC_DRM_PB4);
2156		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[0].y),
2157		- HDMI_FC_DRM_PB5);
2158		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[1].x),
2159		- HDMI_FC_DRM_PB6);
2160		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[1].x),
2161		- HDMI_FC_DRM_PB7);
2162		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[1].y),
2163		- HDMI_FC_DRM_PB8);
2164		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[1].y),
2165		- HDMI_FC_DRM_PB9);
2166		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[2].x),
2167		- HDMI_FC_DRM_PB10);
2168		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[2].x),
2169		- HDMI_FC_DRM_PB11);
2170		- hdmi_writeb(hdmi, HDR_LSB(frame.display_primaries[2].y),
2171		- HDMI_FC_DRM_PB12);
2172		- hdmi_writeb(hdmi, HDR_MSB(frame.display_primaries[2].y),
2173		- HDMI_FC_DRM_PB13);
2174		- hdmi_writeb(hdmi, HDR_LSB(frame.white_point.x), HDMI_FC_DRM_PB14);
2175		- hdmi_writeb(hdmi, HDR_MSB(frame.white_point.x), HDMI_FC_DRM_PB15);
2176		- hdmi_writeb(hdmi, HDR_LSB(frame.white_point.y), HDMI_FC_DRM_PB16);
2177		- hdmi_writeb(hdmi, HDR_MSB(frame.white_point.y), HDMI_FC_DRM_PB17);
2178		- hdmi_writeb(hdmi, HDR_LSB(frame.max_display_mastering_luminance),
2179		- HDMI_FC_DRM_PB18);
2180		- hdmi_writeb(hdmi, HDR_MSB(frame.max_display_mastering_luminance),
2181		- HDMI_FC_DRM_PB19);
2182		- hdmi_writeb(hdmi, HDR_LSB(frame.min_display_mastering_luminance),
2183		- HDMI_FC_DRM_PB20);
2184		- hdmi_writeb(hdmi, HDR_MSB(frame.min_display_mastering_luminance),
2185		- HDMI_FC_DRM_PB21);
2186		- hdmi_writeb(hdmi, HDR_LSB(frame.max_cll), HDMI_FC_DRM_PB22);
2187		- hdmi_writeb(hdmi, HDR_MSB(frame.max_cll), HDMI_FC_DRM_PB23);
2188		- hdmi_writeb(hdmi, HDR_LSB(frame.max_fall), HDMI_FC_DRM_PB24);
2189		- hdmi_writeb(hdmi, HDR_MSB(frame.max_fall), HDMI_FC_DRM_PB25);
2190		- hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
2191		- hdmi_modb(hdmi, HDMI_FC_PACKET_DRM_TX_EN,
2192		- HDMI_FC_PACKET_DRM_TX_EN_MASK, HDMI_FC_PACKET_TX_EN);
2193		-
2194		- DRM_DEBUG("%s eotf %d end\n", __func__,
2195		- hdr_metadata->hdmi_metadata_type1.eotf);
2196		-}
2197		-
2198	2416	static void hdmi_av_composer(struct dw_hdmi *hdmi,
	2417	+ const struct drm_display_info *display,
2199	2418	const struct drm_display_mode *mode)
2200	2419	{
2201	2420	u8 inv_val, bytes;
2202		- struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
	2421	+ const struct drm_hdmi_info *hdmi_info = &display->hdmi;
2203	2422	struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
2204	2423	int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
2205	2424	unsigned int vdisplay, hdisplay;
..	..	@@ -2215,6 +2434,10 @@
2215	2434	vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
2216	2435	if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2217	2436	vmode->mtmdsclock /= 2;
	2437	+ dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
	2438	+
	2439	+ if (hdmi->update)
	2440	+ return;
2218	2441
2219	2442	/* Set up HDMI_FC_INVIDCONF
2220	2443	* Some display equipments require that the interval
..	..	@@ -2282,13 +2505,10 @@
2282	2505	vblank /= 2;
2283	2506	v_de_vs /= 2;
2284	2507	vsync_len /= 2;
2285		- } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
2286		- DRM_MODE_FLAG_3D_FRAME_PACKING) {
2287		- vdisplay += mode->vtotal;
2288	2508	}
2289	2509
2290	2510	/* Scrambling Control */
2291		- if (dw_hdmi_support_scdc(hdmi)) {
	2511	+ if (dw_hdmi_support_scdc(hdmi, display)) {
2292	2512	if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK \|\|
2293	2513	(hdmi_info->scdc.scrambling.low_rates &&
2294	2514	hdmi->scramble_low_rates)) {
..	..	@@ -2373,22 +2593,18 @@
2373	2593	hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2374	2594
2375	2595	/* Enable pixel clock and tmds data path */
2376		- hdmi->mc_clkdis \|= HDMI_MC_CLKDIS_HDCPCLK_DISABLE \|
2377		- HDMI_MC_CLKDIS_CSCCLK_DISABLE \|
2378		- HDMI_MC_CLKDIS_AUDCLK_DISABLE \|
2379		- HDMI_MC_CLKDIS_PREPCLK_DISABLE \|
2380		- HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
	2596	+
	2597	+ if (!hdmi->update)
	2598	+ hdmi->mc_clkdis \|= HDMI_MC_CLKDIS_HDCPCLK_DISABLE \|
	2599	+ HDMI_MC_CLKDIS_CSCCLK_DISABLE \|
	2600	+ HDMI_MC_CLKDIS_AUDCLK_DISABLE \|
	2601	+ HDMI_MC_CLKDIS_PREPCLK_DISABLE \|
	2602	+ HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2381	2603	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2382	2604	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2383	2605
2384	2606	hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2385	2607	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2386		-
2387		- /* Enable csc path */
2388		- if (is_color_space_conversion(hdmi)) {
2389		- hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2390		- hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2391		- }
2392	2608
2393	2609	/* Enable pixel repetition path */
2394	2610	if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
..	..	@@ -2396,13 +2612,20 @@
2396	2612	hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2397	2613	}
2398	2614
2399		- /* Enable color space conversion if needed */
2400		- if (is_color_space_conversion(hdmi))
	2615	+ /* Enable csc path */
	2616	+ if (is_csc_needed(hdmi)) {
	2617	+ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
	2618	+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
	2619	+
2401	2620	hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2402	2621	HDMI_MC_FLOWCTRL);
2403		- else
	2622	+ } else {
	2623	+ hdmi->mc_clkdis \|= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
	2624	+ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
	2625	+
2404	2626	hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2405	2627	HDMI_MC_FLOWCTRL);
	2628	+ }
2406	2629	}
2407	2630
2408	2631	/* Workaround to clear the overflow condition */
..	..	@@ -2425,6 +2648,8 @@
2425	2648	* iteration for others.
2426	2649	* The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
2427	2650	* the workaround with a single iteration.
	2651	+ * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
	2652	+ * been identified as needing the workaround with a single iteration.
2428	2653	*/
2429	2654
2430	2655	switch (hdmi->version) {
..	..	@@ -2432,9 +2657,11 @@
2432	2657	count = 4;
2433	2658	break;
2434	2659	case 0x131a:
	2660	+ case 0x132a:
2435	2661	case 0x200a:
2436	2662	case 0x201a:
2437	2663	case 0x211a:
	2664	+ case 0x212a:
2438	2665	count = 1;
2439	2666	break;
2440	2667	default:
..	..	@@ -2455,11 +2682,44 @@
2455	2682	HDMI_IH_MUTE_FC_STAT2);
2456	2683	}
2457	2684
2458		-static int dw_hdmi_setup(struct dw_hdmi hdmi, struct drm_display_mode mode)
	2685	+static void dw_hdmi_force_output_pattern(struct dw_hdmi hdmi, const struct drm_display_mode mode)
	2686	+{
	2687	+ /* force output black */
	2688	+ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
	2689	+ enum hdmi_quantization_range rgb_quant_range = drm_default_rgb_quant_range(mode);
	2690	+
	2691	+ if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_FULL) {
	2692	+ hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS2); /R/
	2693	+ hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS1); /G/
	2694	+ hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS0); /B/
	2695	+ } else if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
	2696	+ hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS2); /R/
	2697	+ hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS1); /G/
	2698	+ hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS0); /B/
	2699	+ } else if (hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_DEFAULT) {
	2700	+ if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_FULL) {
	2701	+ hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS2); /R/
	2702	+ hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS1); /G/
	2703	+ hdmi_writeb(hdmi, 0x00, HDMI_FC_DBGTMDS0); /B/
	2704	+ } else if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
	2705	+ hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS2); /R/
	2706	+ hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS1); /G/
	2707	+ hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS0); /B/
	2708	+ }
	2709	+ }
	2710	+ } else {
	2711	+ hdmi_writeb(hdmi, 0x80, HDMI_FC_DBGTMDS2); /Cr/
	2712	+ hdmi_writeb(hdmi, 0x10, HDMI_FC_DBGTMDS1); /Y/
	2713	+ hdmi_writeb(hdmi, 0x80, HDMI_FC_DBGTMDS0); /Cb/
	2714	+ }
	2715	+}
	2716	+
	2717	+static int dw_hdmi_setup(struct dw_hdmi *hdmi,
	2718	+ const struct drm_connector *connector,
	2719	+ const struct drm_display_mode *mode)
2459	2720	{
2460	2721	int ret;
2461	2722	void *data = hdmi->plat_data->phy_data;
2462		- bool need_delay = false;
2463	2723
2464	2724	hdmi_disable_overflow_interrupts(hdmi);
2465	2725
..	..	@@ -2508,6 +2768,9 @@
2508	2768	hdmi->hdmi_data.enc_out_bus_format =
2509	2769	MEDIA_BUS_FMT_RGB888_1X24;
2510	2770
	2771	+ if (hdmi->plat_data->set_prev_bus_format)
	2772	+ hdmi->plat_data->set_prev_bus_format(data, hdmi->hdmi_data.enc_out_bus_format);
	2773	+
2511	2774	/* TOFIX: Get input encoding from plat data or fallback to none */
2512	2775	if (hdmi->plat_data->get_enc_in_encoding)
2513	2776	hdmi->hdmi_data.enc_in_encoding =
..	..	@@ -2518,11 +2781,14 @@
2518	2781	else
2519	2782	hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2520	2783
	2784	+
2521	2785	if (hdmi->plat_data->get_quant_range)
2522	2786	hdmi->hdmi_data.quant_range =
2523	2787	hdmi->plat_data->get_quant_range(data);
2524		- else
2525		- hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
	2788	+
	2789	+ hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
	2790	+ drm_default_rgb_quant_range(mode) ==
	2791	+ HDMI_QUANTIZATION_RANGE_LIMITED;
2526	2792
2527	2793	if (!hdmi->sink_is_hdmi)
2528	2794	hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_FULL;
..	..	@@ -2537,23 +2803,11 @@
2537	2803	(mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
2538	2804	hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2539	2805
2540		- /* HDMI Initialization Step B.1 */
2541		- hdmi_av_composer(hdmi, mode);
	2806	+ dw_hdmi_force_output_pattern(hdmi, mode);
2542	2807
2543		- /* HDMI Initializateion Step B.2 */
2544		- if (!hdmi->phy.enabled \|\|
2545		- hdmi->hdmi_data.video_mode.previous_pixelclock !=
2546		- hdmi->hdmi_data.video_mode.mpixelclock \|\|
2547		- hdmi->hdmi_data.video_mode.previous_tmdsclock !=
2548		- hdmi->hdmi_data.video_mode.mtmdsclock) {
2549		- ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2550		- &hdmi->previous_mode);
2551		- if (ret)
2552		- return ret;
2553		- hdmi->phy.enabled = true;
2554		- } else {
2555		- need_delay = true;
2556		- }
	2808	+ /* HDMI Initialization Step B.1 */
	2809	+ hdmi_av_composer(hdmi, &connector->display_info, mode);
	2810	+
2557	2811	/* HDMI Initialization Step B.3 */
2558	2812	dw_hdmi_enable_video_path(hdmi);
2559	2813
..	..	@@ -2570,9 +2824,9 @@
2570	2824	dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2571	2825
2572	2826	/* HDMI Initialization Step F - Configure AVI InfoFrame */
2573		- hdmi_config_AVI(hdmi, mode);
2574		- hdmi_config_vendor_specific_infoframe(hdmi, mode);
2575		- hdmi_config_hdr_infoframe(hdmi);
	2827	+ hdmi_config_AVI(hdmi, connector, mode);
	2828	+ hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
	2829	+ hdmi_config_drm_infoframe(hdmi, connector);
2576	2830	} else {
2577	2831	dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2578	2832	}
..	..	@@ -2582,22 +2836,33 @@
2582	2836	hdmi_video_sample(hdmi);
2583	2837	hdmi_tx_hdcp_config(hdmi, mode);
2584	2838
	2839	+ /* HDMI Enable phy output */
	2840	+ if (!hdmi->phy.enabled \|\|
	2841	+ hdmi->hdmi_data.video_mode.previous_pixelclock !=
	2842	+ hdmi->hdmi_data.video_mode.mpixelclock \|\|
	2843	+ hdmi->hdmi_data.video_mode.previous_tmdsclock !=
	2844	+ hdmi->hdmi_data.video_mode.mtmdsclock) {
	2845	+ ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
	2846	+ &connector->display_info,
	2847	+ &hdmi->previous_mode);
	2848	+ if (ret)
	2849	+ return ret;
	2850	+ hdmi->phy.enabled = true;
	2851	+ }
	2852	+
2585	2853	dw_hdmi_clear_overflow(hdmi);
2586	2854
2587		- /* XXX: Add delay to make csc work before unmute video. */
2588		- if (need_delay)
	2855	+ /*
	2856	+ * konka tv should switch pattern after set to yuv420 10bit or
	2857	+ * the TV might not recognize the signal.
	2858	+ */
	2859	+ if (!hdmi->update) {
	2860	+ hdmi_writeb(hdmi, 1, HDMI_FC_DBGFORCE);
2589	2861	msleep(50);
	2862	+ hdmi_writeb(hdmi, 0, HDMI_FC_DBGFORCE);
	2863	+ }
	2864	+
2590	2865	return 0;
2591		-}
2592		-
2593		-static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
2594		-{
2595		- hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2596		- HDMI_PHY_I2CM_INT_ADDR);
2597		-
2598		- hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL \|
2599		- HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2600		- HDMI_PHY_I2CM_CTLINT_ADDR);
2601	2866	}
2602	2867
2603	2868	static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
..	..	@@ -2654,7 +2919,12 @@
2654	2919	static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2655	2920	{
2656	2921	hdmi->bridge_is_on = true;
2657		- dw_hdmi_setup(hdmi, &hdmi->previous_mode);
	2922	+
	2923	+ /*
	2924	+ * The curr_conn field is guaranteed to be valid here, as this function
	2925	+ * is only be called when !hdmi->disabled.
	2926	+ */
	2927	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2658	2928	}
2659	2929
2660	2930	static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
..	..	@@ -2686,6 +2956,7 @@
2686	2956	if (hdmi->initialized) {
2687	2957	hdmi->initialized = false;
2688	2958	hdmi->disabled = true;
	2959	+ hdmi->logo_plug_out = true;
2689	2960	}
2690	2961	if (hdmi->bridge_is_on)
2691	2962	dw_hdmi_poweroff(hdmi);
..	..	@@ -2715,11 +2986,8 @@
2715	2986	hdmi->rxsense);
2716	2987	}
2717	2988
2718		-static enum drm_connector_status
2719		-dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
	2989	+static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2720	2990	{
2721		- struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2722		- connector);
2723	2991	enum drm_connector_status result;
2724	2992
2725	2993	if (!hdmi->force_logo) {
..	..	@@ -2731,20 +2999,56 @@
2731	2999	}
2732	3000
2733	3001	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
	3002	+ mutex_lock(&hdmi->mutex);
	3003	+ if (result != hdmi->last_connector_result) {
	3004	+ dev_dbg(hdmi->dev, "read_hpd result: %d", result);
	3005	+ handle_plugged_change(hdmi,
	3006	+ result == connector_status_connected);
	3007	+ hdmi->last_connector_result = result;
	3008	+ }
	3009	+ mutex_unlock(&hdmi->mutex);
	3010	+
2734	3011	if (result == connector_status_connected)
2735	3012	extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
2736	3013	else
2737	3014	extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
2738	3015
2739		- mutex_lock(&hdmi->mutex);
2740		- if (result != hdmi->last_connector_result) {
2741		- dev_dbg(hdmi->dev, "read_hpd result: %d", result);
2742		- handle_plugged_change(hdmi,
2743		- result == connector_status_connected);
2744		- hdmi->last_connector_result = result;
2745		- }
2746		- mutex_unlock(&hdmi->mutex);
2747	3016	return result;
	3017	+}
	3018	+
	3019	+static struct edid dw_hdmi_get_edid(struct dw_hdmi hdmi,
	3020	+ struct drm_connector *connector)
	3021	+{
	3022	+ struct edid *edid;
	3023	+
	3024	+ if (!hdmi->ddc)
	3025	+ return NULL;
	3026	+
	3027	+ edid = drm_get_edid(connector, hdmi->ddc);
	3028	+ if (!edid) {
	3029	+ dev_dbg(hdmi->dev, "failed to get edid\n");
	3030	+ return NULL;
	3031	+ }
	3032	+
	3033	+ dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
	3034	+ edid->width_cm, edid->height_cm);
	3035	+
	3036	+ hdmi->support_hdmi = drm_detect_hdmi_monitor(edid);
	3037	+ hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
	3038	+
	3039	+ return edid;
	3040	+}
	3041	+
	3042	+/* -----------------------------------------------------------------------------
	3043	+ * DRM Connector Operations
	3044	+ */
	3045	+
	3046	+static enum drm_connector_status
	3047	+dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
	3048	+{
	3049	+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
	3050	+ connector);
	3051	+ return dw_hdmi_detect(hdmi);
2748	3052	}
2749	3053
2750	3054	static int
..	..	@@ -2785,41 +3089,49 @@
2785	3089	struct edid *edid;
2786	3090	struct drm_display_mode *mode;
2787	3091	struct drm_display_info *info = &connector->display_info;
2788		- int i, ret = 0;
	3092	+ void *data = hdmi->plat_data->phy_data;
	3093	+ int i, ret = 0;
2789	3094
2790	3095	memset(metedata, 0, sizeof(*metedata));
2791		- if (!hdmi->ddc)
2792		- return 0;
2793		-
2794		- edid = drm_get_edid(connector, hdmi->ddc);
	3096	+#if 0
	3097	+ edid = dw_hdmi_get_edid(hdmi, connector);
2795	3098	if (edid) {
	3099	+ int vic = 0;
	3100	+
2796	3101	dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2797	3102	edid->width_cm, edid->height_cm);
2798		-
2799		- hdmi->support_hdmi = drm_detect_hdmi_monitor(edid);
2800		- hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2801		- hdmi->rgb_quant_range_selectable = drm_rgb_quant_range_selectable(edid);
2802	3103	drm_connector_update_edid_property(connector, edid);
2803	3104	cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2804	3105	ret = drm_add_edid_modes(connector, edid);
2805		- dw_hdmi_update_hdr_property(connector);
	3106	+ if (hdmi->plat_data->get_color_changed)
	3107	+ hdmi->plat_data->get_yuv422_format(connector, edid);
	3108	+ if (hdmi->plat_data->get_colorimetry)
	3109	+ hdmi->plat_data->get_colorimetry(data, edid);
	3110	+
	3111	+ list_for_each_entry(mode, &connector->probed_modes, head) {
	3112	+ vic = drm_match_cea_mode(mode);
	3113	+
	3114	+ if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) {
	3115	+ if (vic >= 93 && vic <= 95)
	3116	+ mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
	3117	+ else if (vic == 98)
	3118	+ mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135;
	3119	+ }
	3120	+ }
	3121	+
2806	3122	kfree(edid);
2807	3123	} else {
	3124	+#endif
2808	3125	hdmi->support_hdmi = true;
2809	3126	hdmi->sink_has_audio = true;
2810		- hdmi->rgb_quant_range_selectable = false;
2811		-
2812	3127	for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
2813	3128	const struct drm_display_mode *ptr =
2814	3129	&dw_hdmi_default_modes[i];
2815	3130
2816	3131	mode = drm_mode_duplicate(connector->dev, ptr);
2817	3132	if (mode) {
2818		- if (!i) {
	3133	+ if (!i)
2819	3134	mode->type = DRM_MODE_TYPE_PREFERRED;
2820		- mode->picture_aspect_ratio =
2821		- HDMI_PICTURE_ASPECT_NONE;
2822		- }
2823	3135	drm_mode_probed_add(connector, mode);
2824	3136	ret++;
2825	3137	}
..	..	@@ -2829,10 +3141,206 @@
2829	3141	info->color_formats = 0;
2830	3142
2831	3143	dev_info(hdmi->dev, "failed to get edid\n");
2832		- }
	3144	+// }
	3145	+ dw_hdmi_update_hdr_property(connector);
2833	3146	dw_hdmi_check_output_type_changed(hdmi);
2834	3147
2835	3148	return ret;
	3149	+}
	3150	+
	3151	+static struct drm_encoder *
	3152	+dw_hdmi_connector_best_encoder(struct drm_connector *connector)
	3153	+{
	3154	+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
	3155	+ connector);
	3156	+
	3157	+ return hdmi->bridge.encoder;
	3158	+}
	3159	+
	3160	+static bool dw_hdmi_color_changed(struct drm_connector *connector)
	3161	+{
	3162	+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
	3163	+ connector);
	3164	+ void *data = hdmi->plat_data->phy_data;
	3165	+ bool ret = false;
	3166	+
	3167	+ if (hdmi->plat_data->get_color_changed)
	3168	+ ret = hdmi->plat_data->get_color_changed(data);
	3169	+
	3170	+ return ret;
	3171	+}
	3172	+
	3173	+static bool hdr_metadata_equal(struct dw_hdmi hdmi, const struct drm_connector_state old_state,
	3174	+ const struct drm_connector_state *new_state)
	3175	+{
	3176	+ struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
	3177	+ struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
	3178	+ int i, ret;
	3179	+ u8 *data;
	3180	+
	3181	+ hdmi->hdr2sdr = false;
	3182	+
	3183	+ if (!old_blob && !new_blob)
	3184	+ return true;
	3185	+
	3186	+ if (!old_blob) {
	3187	+ data = (u8 *)new_blob->data;
	3188	+
	3189	+ for (i = 0; i < new_blob->length; i++)
	3190	+ if (data[i])
	3191	+ return false;
	3192	+
	3193	+ return true;
	3194	+ }
	3195	+
	3196	+ if (!new_blob) {
	3197	+ data = (u8 *)old_blob->data;
	3198	+
	3199	+ for (i = 0; i < old_blob->length; i++)
	3200	+ if (data[i])
	3201	+ return false;
	3202	+
	3203	+ return true;
	3204	+ }
	3205	+
	3206	+ if (old_blob->length != new_blob->length)
	3207	+ return false;
	3208	+
	3209	+ ret = !memcmp(old_blob->data, new_blob->data, old_blob->length);
	3210	+
	3211	+ if (!ret && new_blob) {
	3212	+ data = (u8 *)new_blob->data;
	3213	+
	3214	+ for (i = 0; i < new_blob->length; i++)
	3215	+ if (data[i])
	3216	+ break;
	3217	+
	3218	+ if (i == new_blob->length)
	3219	+ hdmi->hdr2sdr = true;
	3220	+ }
	3221	+
	3222	+ return ret;
	3223	+}
	3224	+
	3225	+static bool check_hdr_color_change(struct drm_connector_state *old_state,
	3226	+ struct drm_connector_state *new_state,
	3227	+ struct dw_hdmi *hdmi)
	3228	+{
	3229	+ void *data = hdmi->plat_data->phy_data;
	3230	+
	3231	+ if (!hdr_metadata_equal(hdmi, old_state, new_state)) {
	3232	+ hdmi->plat_data->check_hdr_color_change(new_state, data);
	3233	+ return true;
	3234	+ }
	3235	+
	3236	+ return false;
	3237	+}
	3238	+
	3239	+static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
	3240	+ struct drm_atomic_state *state)
	3241	+{
	3242	+ struct drm_connector_state *old_state =
	3243	+ drm_atomic_get_old_connector_state(state, connector);
	3244	+ struct drm_connector_state *new_state =
	3245	+ drm_atomic_get_new_connector_state(state, connector);
	3246	+ struct drm_crtc *crtc = new_state->crtc;
	3247	+ struct drm_crtc_state *crtc_state;
	3248	+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
	3249	+ connector);
	3250	+ struct drm_display_mode *mode = NULL;
	3251	+ void *data = hdmi->plat_data->phy_data;
	3252	+ struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
	3253	+
	3254	+ if (!crtc)
	3255	+ return 0;
	3256	+
	3257	+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
	3258	+ if (IS_ERR(crtc_state))
	3259	+ return PTR_ERR(crtc_state);
	3260	+
	3261	+ mode = &crtc_state->mode;
	3262	+
	3263	+ /*
	3264	+ * If HDMI is enabled in uboot, it's need to record
	3265	+ * drm_display_mode and set phy status to enabled.
	3266	+ */
	3267	+ if (!vmode->mpixelclock) {
	3268	+ u8 val;
	3269	+
	3270	+ hdmi->curr_conn = connector;
	3271	+
	3272	+ if (hdmi->plat_data->get_enc_in_encoding)
	3273	+ hdmi->hdmi_data.enc_in_encoding =
	3274	+ hdmi->plat_data->get_enc_in_encoding(data);
	3275	+ if (hdmi->plat_data->get_enc_out_encoding)
	3276	+ hdmi->hdmi_data.enc_out_encoding =
	3277	+ hdmi->plat_data->get_enc_out_encoding(data);
	3278	+ if (hdmi->plat_data->get_input_bus_format)
	3279	+ hdmi->hdmi_data.enc_in_bus_format =
	3280	+ hdmi->plat_data->get_input_bus_format(data);
	3281	+ if (hdmi->plat_data->get_output_bus_format)
	3282	+ hdmi->hdmi_data.enc_out_bus_format =
	3283	+ hdmi->plat_data->get_output_bus_format(data);
	3284	+
	3285	+ memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
	3286	+ vmode->mpixelclock = mode->crtc_clock * 1000;
	3287	+ vmode->previous_pixelclock = mode->clock * 1000;
	3288	+ vmode->previous_tmdsclock = mode->clock * 1000;
	3289	+ vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi,
	3290	+ vmode->mpixelclock);
	3291	+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
	3292	+ vmode->mtmdsclock /= 2;
	3293	+
	3294	+ dw_hdmi_force_output_pattern(hdmi, mode);
	3295	+ drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
	3296	+
	3297	+ /* if plug out before hdmi bind, reset hdmi */
	3298	+ if (vmode->mtmdsclock >= 340000000 && !(val & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40))
	3299	+ hdmi->logo_plug_out = true;
	3300	+ }
	3301	+
	3302	+ if (check_hdr_color_change(old_state, new_state, hdmi) \|\| hdmi->logo_plug_out \|\|
	3303	+ dw_hdmi_color_changed(connector)) {
	3304	+ u32 mtmdsclk;
	3305	+
	3306	+ if (hdmi->plat_data->update_color_format)
	3307	+ hdmi->plat_data->update_color_format(new_state, data);
	3308	+ if (hdmi->plat_data->get_enc_in_encoding)
	3309	+ hdmi->hdmi_data.enc_in_encoding =
	3310	+ hdmi->plat_data->get_enc_in_encoding(data);
	3311	+ if (hdmi->plat_data->get_enc_out_encoding)
	3312	+ hdmi->hdmi_data.enc_out_encoding =
	3313	+ hdmi->plat_data->get_enc_out_encoding(data);
	3314	+ if (hdmi->plat_data->get_input_bus_format)
	3315	+ hdmi->hdmi_data.enc_in_bus_format =
	3316	+ hdmi->plat_data->get_input_bus_format(data);
	3317	+ if (hdmi->plat_data->get_output_bus_format)
	3318	+ hdmi->hdmi_data.enc_out_bus_format =
	3319	+ hdmi->plat_data->get_output_bus_format(data);
	3320	+
	3321	+ mtmdsclk = hdmi_get_tmdsclock(hdmi, mode->clock);
	3322	+
	3323	+ if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
	3324	+ mtmdsclk /= 2;
	3325	+
	3326	+ if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD))
	3327	+ return 0;
	3328	+
	3329	+ if (hdmi->hdmi_data.video_mode.mpixelclock == (mode->clock * 1000) &&
	3330	+ hdmi->hdmi_data.video_mode.mtmdsclock == (mtmdsclk * 1000) &&
	3331	+ !hdmi->logo_plug_out && !hdmi->disabled) {
	3332	+ hdmi->update = true;
	3333	+ hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
	3334	+ mdelay(180);
	3335	+ handle_plugged_change(hdmi, false);
	3336	+ } else {
	3337	+ hdmi->update = false;
	3338	+ crtc_state->mode_changed = true;
	3339	+ hdmi->logo_plug_out = false;
	3340	+ }
	3341	+ }
	3342	+
	3343	+ return 0;
2836	3344	}
2837	3345
2838	3346	static int
..	..	@@ -2879,92 +3387,19 @@
2879	3387	property, val);
2880	3388	}
2881	3389
2882		-static bool dw_hdmi_color_changed(struct drm_connector *connector)
	3390	+static void dw_hdmi_connector_atomic_commit(struct drm_connector *connector,
	3391	+ struct drm_connector_state *state)
2883	3392	{
2884		- struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2885		- connector);
2886		- void *data = hdmi->plat_data->phy_data;
2887		- bool ret = false;
	3393	+ struct dw_hdmi *hdmi =
	3394	+ container_of(connector, struct dw_hdmi, connector);
2888	3395
2889		- if (hdmi->plat_data->get_color_changed)
2890		- ret = hdmi->plat_data->get_color_changed(data);
2891		-
2892		- return ret;
2893		-}
2894		-
2895		-static bool hdr_metadata_equal(const struct drm_connector_state *old_state,
2896		- const struct drm_connector_state *new_state)
2897		-{
2898		- struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
2899		- struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
2900		-
2901		- if (!old_blob \|\| !new_blob)
2902		- return old_blob == new_blob;
2903		-
2904		- if (old_blob->length != new_blob->length)
2905		- return false;
2906		-
2907		- return !memcmp(old_blob->data, new_blob->data, old_blob->length);
2908		-}
2909		-
2910		-static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2911		- struct drm_atomic_state *state)
2912		-{
2913		- struct drm_connector_state *old_state =
2914		- drm_atomic_get_old_connector_state(state, connector);
2915		- struct drm_connector_state *new_state =
2916		- drm_atomic_get_new_connector_state(state, connector);
2917		- struct drm_crtc *crtc = new_state->crtc;
2918		- struct drm_crtc_state *crtc_state;
2919		- struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2920		- connector);
2921		- struct drm_display_mode *mode = NULL;
2922		- void *data = hdmi->plat_data->phy_data;
2923		- struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
2924		-
2925		- if (!crtc)
2926		- return 0;
2927		-
2928		- /*
2929		- * If HDMI is enabled in uboot, it's need to record
2930		- * drm_display_mode and set phy status to enabled.
2931		- */
2932		- if (!vmode->mpixelclock) {
2933		- crtc_state = drm_atomic_get_crtc_state(state, crtc);
2934		- if (hdmi->plat_data->get_enc_in_encoding)
2935		- hdmi->hdmi_data.enc_in_encoding =
2936		- hdmi->plat_data->get_enc_in_encoding(data);
2937		- if (hdmi->plat_data->get_enc_out_encoding)
2938		- hdmi->hdmi_data.enc_out_encoding =
2939		- hdmi->plat_data->get_enc_out_encoding(data);
2940		- if (hdmi->plat_data->get_input_bus_format)
2941		- hdmi->hdmi_data.enc_in_bus_format =
2942		- hdmi->plat_data->get_input_bus_format(data);
2943		- if (hdmi->plat_data->get_output_bus_format)
2944		- hdmi->hdmi_data.enc_out_bus_format =
2945		- hdmi->plat_data->get_output_bus_format(data);
2946		-
2947		- mode = &crtc_state->mode;
2948		- memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2949		- vmode->mpixelclock = mode->crtc_clock * 1000;
2950		- vmode->previous_pixelclock = mode->clock;
2951		- vmode->previous_tmdsclock = mode->clock;
2952		- vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi,
2953		- vmode->mpixelclock);
2954		- if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2955		- vmode->mtmdsclock /= 2;
	3396	+ if (hdmi->update) {
	3397	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
	3398	+ mdelay(50);
	3399	+ handle_plugged_change(hdmi, true);
	3400	+ hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
	3401	+ hdmi->update = false;
2956	3402	}
2957		-
2958		- if (!hdr_metadata_equal(old_state, new_state) \|\|
2959		- dw_hdmi_color_changed(connector)) {
2960		- crtc_state = drm_atomic_get_crtc_state(state, crtc);
2961		- if (IS_ERR(crtc_state))
2962		- return PTR_ERR(crtc_state);
2963		-
2964		- crtc_state->mode_changed = true;
2965		- }
2966		-
2967		- return 0;
2968	3403	}
2969	3404
2970	3405	void dw_hdmi_set_quant_range(struct dw_hdmi *hdmi)
..	..	@@ -2973,7 +3408,7 @@
2973	3408	return;
2974	3409
2975	3410	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
2976		- dw_hdmi_setup(hdmi, &hdmi->previous_mode);
	3411	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2977	3412	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
2978	3413	}
2979	3414	EXPORT_SYMBOL_GPL(dw_hdmi_set_quant_range);
..	..	@@ -2989,7 +3424,7 @@
2989	3424	return;
2990	3425
2991	3426	hdmi_writeb(hdmi, HDMI_FC_GCP_SET_AVMUTE, HDMI_FC_GCP);
2992		- dw_hdmi_setup(hdmi, &hdmi->previous_mode);
	3427	+ dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2993	3428	hdmi_writeb(hdmi, HDMI_FC_GCP_CLEAR_AVMUTE, HDMI_FC_GCP);
2994	3429	}
2995	3430	EXPORT_SYMBOL_GPL(dw_hdmi_set_output_type);
..	..	@@ -3005,6 +3440,19 @@
3005	3440	return hdmi->support_hdmi;
3006	3441	}
3007	3442	EXPORT_SYMBOL_GPL(dw_hdmi_get_output_type_cap);
	3443	+
	3444	+void dw_hdmi_set_hpd_wake(struct dw_hdmi *hdmi)
	3445	+{
	3446	+ if (!hdmi->cec)
	3447	+ return;
	3448	+
	3449	+ if (!hdmi->cec_ops)
	3450	+ return;
	3451	+
	3452	+ if (hdmi->cec_ops->hpd_wake_up)
	3453	+ hdmi->cec_ops->hpd_wake_up(hdmi->cec);
	3454	+}
	3455	+EXPORT_SYMBOL_GPL(dw_hdmi_set_hpd_wake);
3008	3456
3009	3457	static void dw_hdmi_connector_force(struct drm_connector *connector)
3010	3458	{
..	..	@@ -3043,8 +3491,9 @@
3043	3491
3044	3492	static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
3045	3493	.get_modes = dw_hdmi_connector_get_modes,
3046		- .best_encoder = drm_atomic_helper_best_encoder,
	3494	+ .best_encoder = dw_hdmi_connector_best_encoder,
3047	3495	.atomic_check = dw_hdmi_connector_atomic_check,
	3496	+ .atomic_commit = dw_hdmi_connector_atomic_commit,
3048	3497	};
3049	3498
3050	3499	static void dw_hdmi_attach_properties(struct dw_hdmi *hdmi)
..	..	@@ -3113,7 +3562,7 @@
3113	3562	if (ops && ops->attach_properties)
3114	3563	return ops->attach_properties(&hdmi->connector,
3115	3564	color, hdmi->version,
3116		- hdmi->plat_data->phy_data);
	3565	+ hdmi->plat_data->phy_data, 0);
3117	3566	}
3118	3567
3119	3568	static void dw_hdmi_destroy_properties(struct dw_hdmi *hdmi)
..	..	@@ -3126,61 +3575,411 @@
3126	3575	hdmi->plat_data->phy_data);
3127	3576	}
3128	3577
3129		-static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
	3578	+static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
3130	3579	{
3131		- struct dw_hdmi *hdmi = bridge->driver_private;
3132		- struct drm_encoder *encoder = bridge->encoder;
3133	3580	struct drm_connector *connector = &hdmi->connector;
3134		- int ret;
	3581	+ struct cec_connector_info conn_info;
	3582	+ struct cec_notifier *notifier;
3135	3583
3136		- if (!hdmi->next_bridge) {
3137		- connector->interlace_allowed = 1;
3138		- connector->polled = DRM_CONNECTOR_POLL_HPD;
	3584	+ if (hdmi->version >= 0x200a)
	3585	+ connector->ycbcr_420_allowed =
	3586	+ hdmi->plat_data->ycbcr_420_allowed;
	3587	+ else
	3588	+ connector->ycbcr_420_allowed = false;
3139	3589
3140		- drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
	3590	+ connector->interlace_allowed = 1;
	3591	+ connector->polled = DRM_CONNECTOR_POLL_HPD;
3141	3592
3142		- drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
3143		- DRM_MODE_CONNECTOR_HDMIA);
	3593	+ drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
3144	3594
3145		- drm_connector_attach_encoder(connector, encoder);
	3595	+ drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
	3596	+ &dw_hdmi_connector_funcs,
	3597	+ DRM_MODE_CONNECTOR_HDMIA,
	3598	+ hdmi->ddc);
3146	3599
3147		- dw_hdmi_attach_properties(hdmi);
	3600	+ /*
	3601	+ * drm_connector_attach_max_bpc_property() requires the
	3602	+ * connector to have a state.
	3603	+ */
	3604	+ drm_atomic_helper_connector_reset(connector);
3148	3605
3149		- return 0;
3150		- }
	3606	+ drm_connector_attach_max_bpc_property(connector, 8, 16);
3151	3607
3152		- hdmi->next_bridge->encoder = bridge->encoder;
3153		- ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge);
3154		- if (ret) {
3155		- DRM_ERROR("Failed to attach bridge with dw-hdmi\n");
3156		- return ret;
3157		- }
	3608	+ if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
	3609	+ drm_object_attach_property(&connector->base,
	3610	+ connector->dev->mode_config.hdr_output_metadata_property, 0);
3158	3611
3159		- bridge->next = hdmi->next_bridge;
	3612	+ drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
	3613	+
	3614	+ dw_hdmi_attach_properties(hdmi);
	3615	+
	3616	+ cec_fill_conn_info_from_drm(&conn_info, connector);
	3617	+
	3618	+ notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
	3619	+ if (!notifier)
	3620	+ return -ENOMEM;
	3621	+
	3622	+ mutex_lock(&hdmi->cec_notifier_mutex);
	3623	+ hdmi->cec_notifier = notifier;
	3624	+ mutex_unlock(&hdmi->cec_notifier_mutex);
3160	3625
3161	3626	return 0;
3162	3627	}
3163	3628
	3629	+/* -----------------------------------------------------------------------------
	3630	+ * DRM Bridge Operations
	3631	+ */
	3632	+
	3633	+/*
	3634	+ * Possible output formats :
	3635	+ * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
	3636	+ * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
	3637	+ * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
	3638	+ * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
	3639	+ * - MEDIA_BUS_FMT_YUV16_1X48,
	3640	+ * - MEDIA_BUS_FMT_RGB161616_1X48,
	3641	+ * - MEDIA_BUS_FMT_UYVY12_1X24,
	3642	+ * - MEDIA_BUS_FMT_YUV12_1X36,
	3643	+ * - MEDIA_BUS_FMT_RGB121212_1X36,
	3644	+ * - MEDIA_BUS_FMT_UYVY10_1X20,
	3645	+ * - MEDIA_BUS_FMT_YUV10_1X30,
	3646	+ * - MEDIA_BUS_FMT_RGB101010_1X30,
	3647	+ * - MEDIA_BUS_FMT_UYVY8_1X16,
	3648	+ * - MEDIA_BUS_FMT_YUV8_1X24,
	3649	+ * - MEDIA_BUS_FMT_RGB888_1X24,
	3650	+ */
	3651	+
	3652	+/* Can return a maximum of 11 possible output formats for a mode/connector */
	3653	+#define MAX_OUTPUT_SEL_FORMATS 11
	3654	+
	3655	+static u32 dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge bridge,
	3656	+ struct drm_bridge_state *bridge_state,
	3657	+ struct drm_crtc_state *crtc_state,
	3658	+ struct drm_connector_state *conn_state,
	3659	+ unsigned int *num_output_fmts)
	3660	+{
	3661	+ struct drm_connector *conn = conn_state->connector;
	3662	+ struct drm_display_info *info = &conn->display_info;
	3663	+ struct drm_display_mode *mode = &crtc_state->mode;
	3664	+ u8 max_bpc = conn_state->max_requested_bpc;
	3665	+ bool is_hdmi2_sink = info->hdmi.scdc.supported \|\|
	3666	+ (info->color_formats & DRM_COLOR_FORMAT_YCRCB420);
	3667	+ u32 *output_fmts;
	3668	+ unsigned int i = 0;
	3669	+
	3670	+ *num_output_fmts = 0;
	3671	+
	3672	+ output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
	3673	+ GFP_KERNEL);
	3674	+ if (!output_fmts)
	3675	+ return NULL;
	3676	+
	3677	+ /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
	3678	+ if (list_is_singular(&bridge->encoder->bridge_chain) \|\|
	3679	+ list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
	3680	+ *num_output_fmts = 1;
	3681	+ output_fmts[0] = MEDIA_BUS_FMT_FIXED;
	3682	+
	3683	+ return output_fmts;
	3684	+ }
	3685	+
	3686	+ /*
	3687	+ * If the current mode enforces 4:2:0, force the output but format
	3688	+ * to 4:2:0 and do not add the YUV422/444/RGB formats
	3689	+ */
	3690	+ if (conn->ycbcr_420_allowed &&
	3691	+ (drm_mode_is_420_only(info, mode) \|\|
	3692	+ (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
	3693	+
	3694	+ /* Order bus formats from 16bit to 8bit if supported */
	3695	+ if (max_bpc >= 16 && info->bpc == 16 &&
	3696	+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
	3697	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
	3698	+
	3699	+ if (max_bpc >= 12 && info->bpc >= 12 &&
	3700	+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
	3701	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
	3702	+
	3703	+ if (max_bpc >= 10 && info->bpc >= 10 &&
	3704	+ (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
	3705	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
	3706	+
	3707	+ /* Default 8bit fallback */
	3708	+ output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
	3709	+
	3710	+ *num_output_fmts = i;
	3711	+
	3712	+ return output_fmts;
	3713	+ }
	3714	+
	3715	+ /*
	3716	+ * Order bus formats from 16bit to 8bit and from YUV422 to RGB
	3717	+ * if supported. In any case the default RGB888 format is added
	3718	+ */
	3719	+
	3720	+ /* Default 8bit RGB fallback */
	3721	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3722	+
	3723	+ if (max_bpc >= 16 && info->bpc == 16) {
	3724	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3725	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
	3726	+
	3727	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
	3728	+ }
	3729	+
	3730	+ if (max_bpc >= 12 && info->bpc >= 12) {
	3731	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
	3732	+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3733	+
	3734	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3735	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3736	+
	3737	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3738	+ }
	3739	+
	3740	+ if (max_bpc >= 10 && info->bpc >= 10) {
	3741	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
	3742	+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3743	+
	3744	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3745	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3746	+
	3747	+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3748	+ }
	3749	+
	3750	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
	3751	+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3752	+
	3753	+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
	3754	+ output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3755	+
	3756	+ *num_output_fmts = i;
	3757	+
	3758	+ return output_fmts;
	3759	+}
	3760	+
	3761	+/*
	3762	+ * Possible input formats :
	3763	+ * - MEDIA_BUS_FMT_RGB888_1X24
	3764	+ * - MEDIA_BUS_FMT_YUV8_1X24
	3765	+ * - MEDIA_BUS_FMT_UYVY8_1X16
	3766	+ * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
	3767	+ * - MEDIA_BUS_FMT_RGB101010_1X30
	3768	+ * - MEDIA_BUS_FMT_YUV10_1X30
	3769	+ * - MEDIA_BUS_FMT_UYVY10_1X20
	3770	+ * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
	3771	+ * - MEDIA_BUS_FMT_RGB121212_1X36
	3772	+ * - MEDIA_BUS_FMT_YUV12_1X36
	3773	+ * - MEDIA_BUS_FMT_UYVY12_1X24
	3774	+ * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
	3775	+ * - MEDIA_BUS_FMT_RGB161616_1X48
	3776	+ * - MEDIA_BUS_FMT_YUV16_1X48
	3777	+ * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
	3778	+ */
	3779	+
	3780	+/* Can return a maximum of 3 possible input formats for an output format */
	3781	+#define MAX_INPUT_SEL_FORMATS 3
	3782	+
	3783	+static u32 dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge bridge,
	3784	+ struct drm_bridge_state *bridge_state,
	3785	+ struct drm_crtc_state *crtc_state,
	3786	+ struct drm_connector_state *conn_state,
	3787	+ u32 output_fmt,
	3788	+ unsigned int *num_input_fmts)
	3789	+{
	3790	+ u32 *input_fmts;
	3791	+ unsigned int i = 0;
	3792	+
	3793	+ *num_input_fmts = 0;
	3794	+
	3795	+ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
	3796	+ GFP_KERNEL);
	3797	+ if (!input_fmts)
	3798	+ return NULL;
	3799	+
	3800	+ switch (output_fmt) {
	3801	+ /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
	3802	+ case MEDIA_BUS_FMT_FIXED:
	3803	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3804	+ break;
	3805	+ /* 8bit */
	3806	+ case MEDIA_BUS_FMT_RGB888_1X24:
	3807	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3808	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3809	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3810	+ break;
	3811	+ case MEDIA_BUS_FMT_YUV8_1X24:
	3812	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3813	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3814	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3815	+ break;
	3816	+ case MEDIA_BUS_FMT_UYVY8_1X16:
	3817	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
	3818	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
	3819	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
	3820	+ break;
	3821	+
	3822	+ /* 10bit */
	3823	+ case MEDIA_BUS_FMT_RGB101010_1X30:
	3824	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3825	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3826	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3827	+ break;
	3828	+ case MEDIA_BUS_FMT_YUV10_1X30:
	3829	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3830	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3831	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3832	+ break;
	3833	+ case MEDIA_BUS_FMT_UYVY10_1X20:
	3834	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
	3835	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
	3836	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
	3837	+ break;
	3838	+
	3839	+ /* 12bit */
	3840	+ case MEDIA_BUS_FMT_RGB121212_1X36:
	3841	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3842	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3843	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3844	+ break;
	3845	+ case MEDIA_BUS_FMT_YUV12_1X36:
	3846	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3847	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3848	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3849	+ break;
	3850	+ case MEDIA_BUS_FMT_UYVY12_1X24:
	3851	+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
	3852	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
	3853	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
	3854	+ break;
	3855	+
	3856	+ /* 16bit */
	3857	+ case MEDIA_BUS_FMT_RGB161616_1X48:
	3858	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
	3859	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
	3860	+ break;
	3861	+ case MEDIA_BUS_FMT_YUV16_1X48:
	3862	+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
	3863	+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
	3864	+ break;
	3865	+
	3866	+ /YUV 4:2:0 /
	3867	+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
	3868	+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
	3869	+ case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
	3870	+ case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
	3871	+ input_fmts[i++] = output_fmt;
	3872	+ break;
	3873	+ }
	3874	+
	3875	+ *num_input_fmts = i;
	3876	+
	3877	+ if (*num_input_fmts == 0) {
	3878	+ kfree(input_fmts);
	3879	+ input_fmts = NULL;
	3880	+ }
	3881	+
	3882	+ return input_fmts;
	3883	+}
	3884	+
	3885	+static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
	3886	+ struct drm_bridge_state *bridge_state,
	3887	+ struct drm_crtc_state *crtc_state,
	3888	+ struct drm_connector_state *conn_state)
	3889	+{
	3890	+ struct dw_hdmi *hdmi = bridge->driver_private;
	3891	+ void *data = hdmi->plat_data->phy_data;
	3892	+
	3893	+ if (bridge_state->output_bus_cfg.format == MEDIA_BUS_FMT_FIXED) {
	3894	+ if (hdmi->plat_data->get_output_bus_format)
	3895	+ hdmi->hdmi_data.enc_out_bus_format =
	3896	+ hdmi->plat_data->get_output_bus_format(data);
	3897	+ else
	3898	+ hdmi->hdmi_data.enc_out_bus_format =
	3899	+ MEDIA_BUS_FMT_RGB888_1X24;
	3900	+
	3901	+ if (hdmi->plat_data->get_input_bus_format)
	3902	+ hdmi->hdmi_data.enc_in_bus_format =
	3903	+ hdmi->plat_data->get_input_bus_format(data);
	3904	+ else if (hdmi->plat_data->input_bus_format)
	3905	+ hdmi->hdmi_data.enc_in_bus_format =
	3906	+ hdmi->plat_data->input_bus_format;
	3907	+ else
	3908	+ hdmi->hdmi_data.enc_in_bus_format =
	3909	+ MEDIA_BUS_FMT_RGB888_1X24;
	3910	+ } else {
	3911	+ hdmi->hdmi_data.enc_out_bus_format =
	3912	+ bridge_state->output_bus_cfg.format;
	3913	+
	3914	+ hdmi->hdmi_data.enc_in_bus_format =
	3915	+ bridge_state->input_bus_cfg.format;
	3916	+
	3917	+ dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
	3918	+ bridge_state->input_bus_cfg.format,
	3919	+ bridge_state->output_bus_cfg.format);
	3920	+ }
	3921	+
	3922	+ return 0;
	3923	+}
	3924	+
	3925	+static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
	3926	+ enum drm_bridge_attach_flags flags)
	3927	+{
	3928	+ struct dw_hdmi *hdmi = bridge->driver_private;
	3929	+ int ret;
	3930	+
	3931	+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
	3932	+ return 0;
	3933	+
	3934	+ if (hdmi->next_bridge) {
	3935	+ hdmi->next_bridge->encoder = bridge->encoder;
	3936	+ ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge, flags);
	3937	+ if (ret) {
	3938	+ DRM_ERROR("Failed to attach bridge with dw-hdmi\n");
	3939	+ return ret;
	3940	+ }
	3941	+
	3942	+ return 0;
	3943	+ }
	3944	+
	3945	+ return dw_hdmi_connector_create(hdmi);
	3946	+}
	3947	+
	3948	+static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
	3949	+{
	3950	+ struct dw_hdmi *hdmi = bridge->driver_private;
	3951	+
	3952	+ mutex_lock(&hdmi->cec_notifier_mutex);
	3953	+ cec_notifier_conn_unregister(hdmi->cec_notifier);
	3954	+ hdmi->cec_notifier = NULL;
	3955	+ mutex_unlock(&hdmi->cec_notifier_mutex);
	3956	+}
	3957	+
3164	3958	static enum drm_mode_status
3165	3959	dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
	3960	+ const struct drm_display_info *info,
3166	3961	const struct drm_display_mode *mode)
3167	3962	{
3168	3963	struct dw_hdmi *hdmi = bridge->driver_private;
3169		- struct drm_connector *connector = &hdmi->connector;
	3964	+ const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
3170	3965	enum drm_mode_status mode_status = MODE_OK;
3171	3966
3172	3967	if (hdmi->next_bridge)
3173	3968	return MODE_OK;
3174	3969
3175		- if (hdmi->plat_data->mode_valid)
3176		- mode_status = hdmi->plat_data->mode_valid(connector, mode);
	3970	+ if (!(hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD) && hdmi->hdr2sdr)
	3971	+ return MODE_OK;
	3972	+
	3973	+ if (pdata->mode_valid)
	3974	+ mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
	3975	+ mode);
3177	3976
3178	3977	return mode_status;
3179	3978	}
3180	3979
3181	3980	static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
3182		- struct drm_display_mode *orig_mode,
3183		- struct drm_display_mode *mode)
	3981	+ const struct drm_display_mode *orig_mode,
	3982	+ const struct drm_display_mode *mode)
3184	3983	{
3185	3984	struct dw_hdmi *hdmi = bridge->driver_private;
3186	3985
..	..	@@ -3192,35 +3991,90 @@
3192	3991	mutex_unlock(&hdmi->mutex);
3193	3992	}
3194	3993
3195		-static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
	3994	+static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
	3995	+ struct drm_bridge_state *old_state)
3196	3996	{
3197	3997	struct dw_hdmi *hdmi = bridge->driver_private;
	3998	+ void *data = hdmi->plat_data->phy_data;
3198	3999
3199	4000	mutex_lock(&hdmi->mutex);
3200	4001	hdmi->disabled = true;
	4002	+ handle_plugged_change(hdmi, false);
	4003	+ hdmi->curr_conn = NULL;
3201	4004	dw_hdmi_update_power(hdmi);
3202	4005	dw_hdmi_update_phy_mask(hdmi);
	4006	+ if (hdmi->plat_data->dclk_set)
	4007	+ hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, false, 0);
3203	4008	mutex_unlock(&hdmi->mutex);
	4009	+
	4010	+ mutex_lock(&hdmi->i2c->lock);
	4011	+ if (hdmi->plat_data->set_ddc_io)
	4012	+ hdmi->plat_data->set_ddc_io(data, false);
	4013	+ mutex_unlock(&hdmi->i2c->lock);
3204	4014	}
3205	4015
3206		-static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
	4016	+static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
	4017	+ struct drm_bridge_state *old_state)
3207	4018	{
3208	4019	struct dw_hdmi *hdmi = bridge->driver_private;
	4020	+ struct drm_atomic_state *state = old_state->base.state;
	4021	+ struct drm_connector *connector;
	4022	+
	4023	+ connector = drm_atomic_get_new_connector_for_encoder(state,
	4024	+ bridge->encoder);
3209	4025
3210	4026	mutex_lock(&hdmi->mutex);
3211	4027	hdmi->disabled = false;
	4028	+ hdmi->curr_conn = connector;
	4029	+ if (hdmi->plat_data->dclk_set)
	4030	+ hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, true, 0);
3212	4031	dw_hdmi_update_power(hdmi);
3213	4032	dw_hdmi_update_phy_mask(hdmi);
	4033	+ handle_plugged_change(hdmi, true);
3214	4034	mutex_unlock(&hdmi->mutex);
3215	4035	}
3216	4036
	4037	+static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
	4038	+{
	4039	+ struct dw_hdmi *hdmi = bridge->driver_private;
	4040	+
	4041	+ return dw_hdmi_detect(hdmi);
	4042	+}
	4043	+
	4044	+static struct edid dw_hdmi_bridge_get_edid(struct drm_bridge bridge,
	4045	+ struct drm_connector *connector)
	4046	+{
	4047	+ struct dw_hdmi *hdmi = bridge->driver_private;
	4048	+
	4049	+ return dw_hdmi_get_edid(hdmi, connector);
	4050	+}
	4051	+
3217	4052	static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
	4053	+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
	4054	+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
	4055	+ .atomic_reset = drm_atomic_helper_bridge_reset,
3218	4056	.attach = dw_hdmi_bridge_attach,
3219		- .enable = dw_hdmi_bridge_enable,
3220		- .disable = dw_hdmi_bridge_disable,
	4057	+ .detach = dw_hdmi_bridge_detach,
	4058	+ .atomic_check = dw_hdmi_bridge_atomic_check,
	4059	+ .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
	4060	+ .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
	4061	+ .atomic_enable = dw_hdmi_bridge_atomic_enable,
	4062	+ .atomic_disable = dw_hdmi_bridge_atomic_disable,
3221	4063	.mode_set = dw_hdmi_bridge_mode_set,
3222	4064	.mode_valid = dw_hdmi_bridge_mode_valid,
	4065	+ .detect = dw_hdmi_bridge_detect,
	4066	+ .get_edid = dw_hdmi_bridge_get_edid,
3223	4067	};
	4068	+
	4069	+void dw_hdmi_set_cec_adap(struct dw_hdmi hdmi, struct cec_adapter adap)
	4070	+{
	4071	+ hdmi->cec_adap = adap;
	4072	+}
	4073	+EXPORT_SYMBOL_GPL(dw_hdmi_set_cec_adap);
	4074	+
	4075	+/* -----------------------------------------------------------------------------
	4076	+ * IRQ Handling
	4077	+ */
3224	4078
3225	4079	static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
3226	4080	{
..	..	@@ -3330,9 +4184,11 @@
3330	4184	phy_stat & HDMI_PHY_HPD,
3331	4185	phy_stat & HDMI_PHY_RX_SENSE);
3332	4186
3333		- if ((phy_stat & (HDMI_PHY_RX_SENSE \| HDMI_PHY_HPD)) == 0)
3334		- cec_notifier_set_phys_addr(hdmi->cec_notifier,
3335		- CEC_PHYS_ADDR_INVALID);
	4187	+ if ((phy_stat & (HDMI_PHY_RX_SENSE \| HDMI_PHY_HPD)) == 0) {
	4188	+ mutex_lock(&hdmi->cec_notifier_mutex);
	4189	+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
	4190	+ mutex_unlock(&hdmi->cec_notifier_mutex);
	4191	+ }
3336	4192	}
3337	4193
3338	4194	check_hdmi_irq(hdmi, intr_stat, phy_int_pol);
..	..	@@ -3456,6 +4312,7 @@
3456	4312	static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
3457	4313	.write = hdmi_writeb,
3458	4314	.read = hdmi_readb,
	4315	+ .mod = hdmi_modb,
3459	4316	.enable = dw_hdmi_cec_enable,
3460	4317	.disable = dw_hdmi_cec_disable,
3461	4318	};
..	..	@@ -3464,15 +4321,31 @@
3464	4321	.reg_bits = 32,
3465	4322	.val_bits = 8,
3466	4323	.reg_stride = 1,
3467		- .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
	4324	+ .max_register = HDMI_I2CM_SCDC_UPDATE1,
3468	4325	};
3469	4326
3470	4327	static const struct regmap_config hdmi_regmap_32bit_config = {
3471	4328	.reg_bits = 32,
3472	4329	.val_bits = 32,
3473	4330	.reg_stride = 4,
3474		- .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
	4331	+ .max_register = HDMI_I2CM_SCDC_UPDATE1 << 2,
3475	4332	};
	4333	+
	4334	+static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
	4335	+{
	4336	+ initialize_hdmi_ih_mutes(hdmi);
	4337	+
	4338	+ /*
	4339	+ * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
	4340	+ * Even if we are using a separate i2c adapter doing this doesn't
	4341	+ * hurt.
	4342	+ */
	4343	+ if (hdmi->i2c)
	4344	+ dw_hdmi_i2c_init(hdmi);
	4345	+
	4346	+ if (hdmi->phy.ops->setup_hpd)
	4347	+ hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
	4348	+}
3476	4349
3477	4350	static int dw_hdmi_status_show(struct seq_file s, void v)
3478	4351	{
..	..	@@ -3532,22 +4405,22 @@
3532	4405	}
3533	4406
3534	4407	val = hdmi_readb(hdmi, HDMI_FC_PACKET_TX_EN);
3535		- if (!(val & HDMI_FC_PACKET_DRM_TX_EN_MASK)) {
	4408	+ if (!(val & HDMI_FC_PACKET_TX_EN_DRM_MASK)) {
3536	4409	seq_puts(s, "Off\n");
3537	4410	return 0;
3538	4411	}
3539	4412
3540	4413	switch (hdmi_readb(hdmi, HDMI_FC_DRM_PB0)) {
3541		- case TRADITIONAL_GAMMA_SDR:
	4414	+ case HDMI_EOTF_TRADITIONAL_GAMMA_SDR:
3542	4415	seq_puts(s, "SDR");
3543	4416	break;
3544		- case TRADITIONAL_GAMMA_HDR:
	4417	+ case HDMI_EOTF_TRADITIONAL_GAMMA_HDR:
3545	4418	seq_puts(s, "HDR");
3546	4419	break;
3547		- case SMPTE_ST2084:
	4420	+ case HDMI_EOTF_SMPTE_ST2084:
3548	4421	seq_puts(s, "ST2084");
3549	4422	break;
3550		- case HLG:
	4423	+ case HDMI_EOTF_BT_2100_HLG:
3551	4424	seq_puts(s, "HLG");
3552	4425	break;
3553	4426	default:
..	..	@@ -3824,9 +4697,22 @@
3824	4697	return 0;
3825	4698	}
3826	4699
3827		-static struct dw_hdmi *
3828		-__dw_hdmi_probe(struct platform_device *pdev,
3829		- const struct dw_hdmi_plat_data *plat_data)
	4700	+void
	4701	+dw_hdmi_cec_wake_ops_register(struct dw_hdmi hdmi, const struct dw_hdmi_cec_wake_ops cec_ops)
	4702	+{
	4703	+ if (!cec_ops \|\| !hdmi)
	4704	+ return;
	4705	+
	4706	+ hdmi->cec_ops = cec_ops;
	4707	+}
	4708	+EXPORT_SYMBOL_GPL(dw_hdmi_cec_wake_ops_register);
	4709	+
	4710	+
	4711	+/* -----------------------------------------------------------------------------
	4712	+ * Probe/remove API, used from platforms based on the DRM bridge API.
	4713	+ */
	4714	+struct dw_hdmi dw_hdmi_probe(struct platform_device pdev,
	4715	+ const struct dw_hdmi_plat_data *plat_data)
3830	4716	{
3831	4717	struct device *dev = &pdev->dev;
3832	4718	struct device_node *np = dev->of_node;
..	..	@@ -3861,6 +4747,7 @@
3861	4747
3862	4748	mutex_init(&hdmi->mutex);
3863	4749	mutex_init(&hdmi->audio_mutex);
	4750	+ mutex_init(&hdmi->cec_notifier_mutex);
3864	4751	spin_lock_init(&hdmi->audio_lock);
3865	4752
3866	4753	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
..	..	@@ -3983,6 +4870,7 @@
3983	4870	if (ret)
3984	4871	goto err_iahb;
3985	4872
	4873	+ hdmi->logo_plug_out = false;
3986	4874	hdmi->initialized = false;
3987	4875	ret = hdmi_readb(hdmi, HDMI_PHY_STAT0);
3988	4876	if (((ret & HDMI_PHY_TX_PHY_LOCK) && (ret & HDMI_PHY_HPD) &&
..	..	@@ -3992,12 +4880,17 @@
3992	4880	hdmi->bridge_is_on = true;
3993	4881	hdmi->phy.enabled = true;
3994	4882	hdmi->initialized = true;
	4883	+ if (hdmi->plat_data->set_ddc_io)
	4884	+ hdmi->plat_data->set_ddc_io(hdmi->plat_data->phy_data, true);
	4885	+ if (hdmi->plat_data->dclk_set)
	4886	+ hdmi->plat_data->dclk_set(hdmi->plat_data->phy_data, true, 0);
3995	4887	} else if (ret & HDMI_PHY_TX_PHY_LOCK) {
3996	4888	hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
	4889	+ if (hdmi->plat_data->set_ddc_io)
	4890	+ hdmi->plat_data->set_ddc_io(hdmi->plat_data->phy_data, false);
3997	4891	}
3998	4892
3999	4893	init_hpd_work(hdmi);
4000		- initialize_hdmi_ih_mutes(hdmi);
4001	4894
4002	4895	irq = platform_get_irq(pdev, 0);
4003	4896	if (irq < 0) {
..	..	@@ -4007,16 +4900,10 @@
4007	4900
4008	4901	hdmi->irq = irq;
4009	4902	ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
4010		- dw_hdmi_irq, IRQF_SHARED,
	4903	+ dw_hdmi_irq, IRQF_SHARED \| IRQF_ONESHOT,
4011	4904	dev_name(dev), hdmi);
4012	4905	if (ret)
4013	4906	goto err_iahb;
4014		-
4015		- hdmi->cec_notifier = cec_notifier_get(dev);
4016		- if (!hdmi->cec_notifier) {
4017		- ret = -ENOMEM;
4018		- goto err_iahb;
4019		- }
4020	4907
4021	4908	/*
4022	4909	* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
..	..	@@ -4026,6 +4913,24 @@
4026	4913
4027	4914	/* If DDC bus is not specified, try to register HDMI I2C bus */
4028	4915	if (!hdmi->ddc) {
	4916	+ /* Look for (optional) stuff related to unwedging */
	4917	+ hdmi->pinctrl = devm_pinctrl_get(dev);
	4918	+ if (!IS_ERR(hdmi->pinctrl)) {
	4919	+ hdmi->unwedge_state =
	4920	+ pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
	4921	+ hdmi->default_state =
	4922	+ pinctrl_lookup_state(hdmi->pinctrl, "default");
	4923	+
	4924	+ if (IS_ERR(hdmi->default_state) \|\|
	4925	+ IS_ERR(hdmi->unwedge_state)) {
	4926	+ if (!IS_ERR(hdmi->unwedge_state))
	4927	+ dev_warn(dev,
	4928	+ "Unwedge requires default pinctrl\n");
	4929	+ hdmi->default_state = NULL;
	4930	+ hdmi->unwedge_state = NULL;
	4931	+ }
	4932	+ }
	4933	+
4029	4934	hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
4030	4935	if (IS_ERR(hdmi->ddc))
4031	4936	hdmi->ddc = NULL;
..	..	@@ -4041,8 +4946,12 @@
4041	4946	hdmi->i2c->scl_low_ns = 4916;
4042	4947	}
4043	4948
	4949	+ dw_hdmi_init_hw(hdmi);
	4950	+
4044	4951	hdmi->bridge.driver_private = hdmi;
4045	4952	hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
	4953	+ hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT \| DRM_BRIDGE_OP_EDID
	4954	+ \| DRM_BRIDGE_OP_HPD;
4046	4955	#ifdef CONFIG_OF
4047	4956	hdmi->bridge.of_node = pdev->dev.of_node;
4048	4957	#endif
..	..	@@ -4071,16 +4980,6 @@
4071	4980	hdmi->sink_has_audio = true;
4072	4981	}
4073	4982
4074		- dw_hdmi_setup_i2c(hdmi);
4075		- if (hdmi->phy.ops->setup_hpd)
4076		- hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
4077		-
4078		- if (hdmi->version >= 0x200a)
4079		- hdmi->connector.ycbcr_420_allowed =
4080		- hdmi->plat_data->ycbcr_420_allowed;
4081		- else
4082		- hdmi->connector.ycbcr_420_allowed = false;
4083		-
4084	4983	memset(&pdevinfo, 0, sizeof(pdevinfo));
4085	4984	pdevinfo.parent = dev;
4086	4985	pdevinfo.id = PLATFORM_DEVID_AUTO;
..	..	@@ -4095,7 +4994,7 @@
4095	4994	audio.base = hdmi->regs;
4096	4995	audio.irq = irq;
4097	4996	audio.hdmi = hdmi;
4098		- audio.eld = hdmi->connector.eld;
	4997	+ audio.get_eld = hdmi_audio_get_eld;
4099	4998	hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
4100	4999	hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
4101	5000
..	..	@@ -4108,9 +5007,9 @@
4108	5007	struct dw_hdmi_i2s_audio_data audio;
4109	5008
4110	5009	audio.hdmi = hdmi;
	5010	+ audio.get_eld = hdmi_audio_get_eld;
4111	5011	audio.write = hdmi_writeb;
4112	5012	audio.read = hdmi_readb;
4113		- audio.mod = hdmi_modb;
4114	5013	hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
4115	5014	hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
4116	5015
..	..	@@ -4126,6 +5025,12 @@
4126	5025	cec.ops = &dw_hdmi_cec_ops;
4127	5026	cec.irq = irq;
4128	5027
	5028	+ irq = platform_get_irq(pdev, 1);
	5029	+ if (irq < 0)
	5030	+ dev_dbg(hdmi->dev, "can't get cec wake up irq\n");
	5031	+
	5032	+ cec.wake_irq = irq;
	5033	+
4129	5034	pdevinfo.name = "dw-hdmi-cec";
4130	5035	pdevinfo.data = &cec;
4131	5036	pdevinfo.size_data = sizeof(cec);
..	..	@@ -4136,7 +5041,8 @@
4136	5041
4137	5042	hdmi->extcon = devm_extcon_dev_allocate(hdmi->dev, dw_hdmi_cable);
4138	5043	if (IS_ERR(hdmi->extcon)) {
4139		- dev_err(hdmi->dev, "allocate extcon failed\n");
	5044	+ ret = PTR_ERR(hdmi->extcon);
	5045	+ dev_err(hdmi->dev, "allocate extcon failed: %d\n", ret);
4140	5046	goto err_iahb;
4141	5047	}
4142	5048
..	..	@@ -4156,9 +5062,7 @@
4156	5062	goto err_iahb;
4157	5063	}
4158	5064
4159		- /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
4160		- if (hdmi->i2c)
4161		- dw_hdmi_i2c_init(hdmi);
	5065	+ drm_bridge_add(&hdmi->bridge);
4162	5066
4163	5067	dw_hdmi_register_debugfs(dev, hdmi);
4164	5068
..	..	@@ -4172,26 +5076,22 @@
4172	5076	return hdmi;
4173	5077
4174	5078	err_iahb:
4175		- if (hdmi->i2c) {
4176		- i2c_del_adapter(&hdmi->i2c->adap);
4177		- hdmi->ddc = NULL;
4178		- }
4179		-
4180		- if (hdmi->cec_notifier)
4181		- cec_notifier_put(hdmi->cec_notifier);
4182		-
4183	5079	clk_disable_unprepare(hdmi->iahb_clk);
4184	5080	if (hdmi->cec_clk)
4185	5081	clk_disable_unprepare(hdmi->cec_clk);
4186	5082	err_isfr:
4187	5083	clk_disable_unprepare(hdmi->isfr_clk);
4188	5084	err_res:
4189		- i2c_put_adapter(hdmi->ddc);
	5085	+ if (hdmi->i2c)
	5086	+ i2c_del_adapter(&hdmi->i2c->adap);
	5087	+ else
	5088	+ i2c_put_adapter(hdmi->ddc);
4190	5089
4191	5090	return ERR_PTR(ret);
4192	5091	}
	5092	+EXPORT_SYMBOL_GPL(dw_hdmi_probe);
4193	5093
4194		-static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
	5094	+void dw_hdmi_remove(struct dw_hdmi *hdmi)
4195	5095	{
4196	5096	if (hdmi->irq)
4197	5097	disable_irq(hdmi->irq);
..	..	@@ -4201,6 +5101,8 @@
4201	5101	destroy_workqueue(hdmi->workqueue);
4202	5102
4203	5103	debugfs_remove_recursive(hdmi->debugfs_dir);
	5104	+
	5105	+ drm_bridge_remove(&hdmi->bridge);
4204	5106
4205	5107	if (hdmi->audio && !IS_ERR(hdmi->audio))
4206	5108	platform_device_unregister(hdmi->audio);
..	..	@@ -4220,9 +5122,6 @@
4220	5122	if (hdmi->bridge.encoder)
4221	5123	hdmi->bridge.encoder->funcs->destroy(hdmi->bridge.encoder);
4222	5124
4223		- if (hdmi->cec_notifier)
4224		- cec_notifier_put(hdmi->cec_notifier);
4225		-
4226	5125	clk_disable_unprepare(hdmi->iahb_clk);
4227	5126	clk_disable_unprepare(hdmi->isfr_clk);
4228	5127	if (hdmi->cec_clk)
..	..	@@ -4232,31 +5131,6 @@
4232	5131	i2c_del_adapter(&hdmi->i2c->adap);
4233	5132	else
4234	5133	i2c_put_adapter(hdmi->ddc);
4235		-}
4236		-
4237		-/* -----------------------------------------------------------------------------
4238		- * Probe/remove API, used from platforms based on the DRM bridge API.
4239		- */
4240		-struct dw_hdmi dw_hdmi_probe(struct platform_device pdev,
4241		- const struct dw_hdmi_plat_data *plat_data)
4242		-{
4243		- struct dw_hdmi *hdmi;
4244		-
4245		- hdmi = __dw_hdmi_probe(pdev, plat_data);
4246		- if (IS_ERR(hdmi))
4247		- return hdmi;
4248		-
4249		- drm_bridge_add(&hdmi->bridge);
4250		-
4251		- return hdmi;
4252		-}
4253		-EXPORT_SYMBOL_GPL(dw_hdmi_probe);
4254		-
4255		-void dw_hdmi_remove(struct dw_hdmi *hdmi)
4256		-{
4257		- drm_bridge_remove(&hdmi->bridge);
4258		-
4259		- __dw_hdmi_remove(hdmi);
4260	5134	}
4261	5135	EXPORT_SYMBOL_GPL(dw_hdmi_remove);
4262	5136
..	..	@@ -4270,13 +5144,13 @@
4270	5144	struct dw_hdmi *hdmi;
4271	5145	int ret;
4272	5146
4273		- hdmi = __dw_hdmi_probe(pdev, plat_data);
	5147	+ hdmi = dw_hdmi_probe(pdev, plat_data);
4274	5148	if (IS_ERR(hdmi))
4275	5149	return hdmi;
4276	5150
4277		- ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
	5151	+ ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
4278	5152	if (ret) {
4279		- __dw_hdmi_remove(hdmi);
	5153	+ dw_hdmi_remove(hdmi);
4280	5154	DRM_ERROR("Failed to initialize bridge with drm\n");
4281	5155	return ERR_PTR(ret);
4282	5156	}
..	..	@@ -4290,7 +5164,7 @@
4290	5164
4291	5165	void dw_hdmi_unbind(struct dw_hdmi *hdmi)
4292	5166	{
4293		- __dw_hdmi_remove(hdmi);
	5167	+ dw_hdmi_remove(hdmi);
4294	5168	}
4295	5169	EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
4296	5170
..	..	@@ -4319,12 +5193,10 @@
4319	5193	}
4320	5194	}
4321	5195
4322		-void dw_hdmi_suspend(struct device dev, struct dw_hdmi hdmi)
	5196	+void dw_hdmi_suspend(struct dw_hdmi *hdmi)
4323	5197	{
4324		- if (!hdmi) {
4325		- dev_warn(dev, "Hdmi has not been initialized\n");
	5198	+ if (!hdmi)
4326	5199	return;
4327		- }
4328	5200
4329	5201	mutex_lock(&hdmi->mutex);
4330	5202
..	..	@@ -4345,18 +5217,16 @@
4345	5217	disable_irq(hdmi->irq);
4346	5218	cancel_delayed_work(&hdmi->work);
4347	5219	flush_workqueue(hdmi->workqueue);
4348		- pinctrl_pm_select_sleep_state(dev);
	5220	+ pinctrl_pm_select_sleep_state(hdmi->dev);
4349	5221	}
4350	5222	EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
4351	5223
4352		-void dw_hdmi_resume(struct device dev, struct dw_hdmi hdmi)
	5224	+void dw_hdmi_resume(struct dw_hdmi *hdmi)
4353	5225	{
4354		- if (!hdmi) {
4355		- dev_warn(dev, "Hdmi has not been initialized\n");
	5226	+ if (!hdmi)
4356	5227	return;
4357		- }
4358	5228
4359		- pinctrl_pm_select_default_state(dev);
	5229	+ pinctrl_pm_select_default_state(hdmi->dev);
4360	5230	mutex_lock(&hdmi->mutex);
4361	5231	dw_hdmi_reg_initial(hdmi);
4362	5232	if (hdmi->i2c)