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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
....@@ -1,13 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Analogix DP (Display port) core register interface driver.
34  *
45  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
56  * Author: Jingoo Han <jg1.han@samsung.com>
6
- *
7
- * This program is free software; you can redistribute it and/or modify it
8
- * under the terms of the GNU General Public License as published by the
9
- * Free Software Foundation; either version 2 of the License, or (at your
10
- * option) any later version.
117  */
128 
139 #include <linux/delay.h>
....@@ -18,14 +14,10 @@
1814 #include <linux/phy/phy.h>
1915 
2016 #include <drm/bridge/analogix_dp.h>
17
+#include <drm/drm_probe_helper.h>
2118 
2219 #include "analogix_dp_core.h"
2320 #include "analogix_dp_reg.h"
24
-
25
-#define COMMON_INT_MASK_1	0
26
-#define COMMON_INT_MASK_2	0
27
-#define COMMON_INT_MASK_3	0
28
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
2921 
3022 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val)
3123 {
....@@ -69,16 +61,13 @@
6961 	analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg);
7062 }
7163 
72
-void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
64
+static void analogix_dp_set_lane_map(struct analogix_dp_device *dp)
7365 {
74
-	u32 reg;
66
+	struct video_info *video_info = &dp->video_info;
67
+	u32 i, reg = 0;
7568 
76
-	if (enable)
77
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
78
-		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
79
-	else
80
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
81
-		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
69
+	for (i = 0; i < video_info->max_lane_count; i++)
70
+		reg |= video_info->lane_map[i] << (2 * i);
8271 
8372 	analogix_dp_write(dp, ANALOGIX_DP_LANE_MAP, reg);
8473 }
....@@ -95,8 +84,7 @@
9584 
9685 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
9786 		reg = REF_CLK_24M;
98
-		if (dp->plat_data->dev_type == RK3288_DP ||
99
-		    dp->plat_data->dev_type == RK3368_EDP)
87
+		if (dp->plat_data->dev_type == RK3288_DP)
10088 			reg ^= REF_CLK_MASK;
10189 
10290 		analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_1, reg);
....@@ -117,8 +105,6 @@
117105 	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
118106 		CH1_AMP_400_MV | CH0_AMP_400_MV;
119107 	analogix_dp_write(dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, reg);
120
-
121
-	analogix_dp_write(dp, ANALOGIX_DP_AUX, 0x4);
122108 }
123109 
124110 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
....@@ -165,7 +151,7 @@
165151 
166152 	usleep_range(20, 30);
167153 
168
-	analogix_dp_lane_swap(dp, 0);
154
+	analogix_dp_set_lane_map(dp);
169155 
170156 	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0);
171157 	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40);
....@@ -174,9 +160,6 @@
174160 
175161 	analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0);
176162 	analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0);
177
-
178
-	analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e);
179
-	analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a);
180163 
181164 	analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10);
182165 
....@@ -198,17 +181,10 @@
198181 
199182 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
200183 {
201
-	u32 reg;
202
-
203184 	/* 0: mask, 1: unmask */
204
-	reg = COMMON_INT_MASK_1;
205
-	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, reg);
206
-
207
-	reg = COMMON_INT_MASK_2;
208
-	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, reg);
209
-
210
-	reg = COMMON_INT_MASK_3;
211
-	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, reg);
185
+	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0);
186
+	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0);
187
+	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0);
212188 
213189 	if (dp->force_hpd || dp->hpd_gpiod)
214190 		analogix_dp_mute_hpd_interrupt(dp);
....@@ -222,7 +198,7 @@
222198 
223199 	/* 0: mask, 1: unmask */
224200 	reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4);
225
-	reg &= ~COMMON_INT_MASK_4;
201
+	reg &= ~HOTPLUG_CHG;
226202 	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg);
227203 
228204 	reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK);
....@@ -235,7 +211,8 @@
235211 	u32 reg;
236212 
237213 	/* 0: mask, 1: unmask */
238
-	reg = COMMON_INT_MASK_4;
214
+	reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_MASK_4);
215
+	reg |= HOTPLUG_CHG;
239216 	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, reg);
240217 
241218 	reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA_MASK);
....@@ -426,7 +403,8 @@
426403 	if (dp->hpd_gpiod)
427404 		return;
428405 
429
-	analogix_dp_clear_hotplug_interrupts(dp);
406
+	analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0xbb);
407
+	analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x80);
430408 
431409 	reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
432410 	reg &= ~(F_HPD | HPD_CTRL);
....@@ -442,23 +420,39 @@
442420 	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
443421 }
444422 
445
-enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
423
+static void analogix_dp_handle_hpd_event(struct analogix_dp_device *dp)
446424 {
425
+	bool changed = false;
447426 	u32 reg;
448427 
449
-	/* Parse hotplug interrupt status register */
428
+	reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
429
+	if (reg & INT_HPD) {
430
+		analogix_dp_write(dp, ANALOGIX_DP_INT_STA, INT_HPD);
431
+
432
+		memset(&dp->compliance, 0, sizeof(dp->compliance));
433
+
434
+		analogix_dp_check_device_service_irq(dp);
435
+
436
+		if (dp->compliance.test_active &&
437
+		    dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
438
+			analogix_dp_phy_test(dp);
439
+			return;
440
+		}
441
+	}
442
+
450443 	reg = analogix_dp_read(dp, ANALOGIX_DP_COMMON_INT_STA_4);
444
+	if (reg & HOTPLUG_CHG) {
445
+		analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, HOTPLUG_CHG);
446
+		changed = true;
447
+	}
451448 
452
-	if (reg & PLUG)
453
-		return DP_IRQ_TYPE_HP_CABLE_IN;
449
+	if (changed)
450
+		drm_helper_hpd_irq_event(dp->drm_dev);
451
+}
454452 
455
-	if (reg & HPD_LOST)
456
-		return DP_IRQ_TYPE_HP_CABLE_OUT;
457
-
458
-	if (reg & HOTPLUG_CHG)
459
-		return DP_IRQ_TYPE_HP_CHANGE;
460
-
461
-	return DP_IRQ_TYPE_UNKNOWN;
453
+void analogix_dp_irq_handler(struct analogix_dp_device *dp)
454
+{
455
+	analogix_dp_handle_hpd_event(dp);
462456 }
463457 
464458 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
....@@ -533,99 +527,12 @@
533527 	analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
534528 }
535529 
536
-int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
537
-{
538
-	int reg;
539
-	int retval = 0;
540
-	int timeout_loop = 0;
541
-
542
-	/* Enable AUX CH operation */
543
-	reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_CTL_2);
544
-	reg |= AUX_EN;
545
-	analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_2, reg);
546
-
547
-	/* Is AUX CH command reply received? */
548
-	reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
549
-	while (!(reg & RPLY_RECEIV)) {
550
-		timeout_loop++;
551
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
552
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
553
-			return -ETIMEDOUT;
554
-		}
555
-		reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
556
-		usleep_range(10, 11);
557
-	}
558
-
559
-	/* Clear interrupt source for AUX CH command reply */
560
-	analogix_dp_write(dp, ANALOGIX_DP_INT_STA, RPLY_RECEIV);
561
-
562
-	/* Clear interrupt source for AUX CH access error */
563
-	reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
564
-	if (reg & AUX_ERR) {
565
-		analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR);
566
-		return -EREMOTEIO;
567
-	}
568
-
569
-	/* Check AUX CH error access status */
570
-	reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA);
571
-	if ((reg & AUX_STATUS_MASK) != 0) {
572
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
573
-			reg & AUX_STATUS_MASK);
574
-		return -EREMOTEIO;
575
-	}
576
-
577
-	return retval;
578
-}
579
-
580
-int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
581
-				   unsigned int reg_addr,
582
-				   unsigned char data)
583
-{
584
-	u32 reg;
585
-	int i;
586
-	int retval;
587
-
588
-	for (i = 0; i < 3; i++) {
589
-		/* Clear AUX CH data buffer */
590
-		reg = BUF_CLR;
591
-		analogix_dp_write(dp, ANALOGIX_DP_BUFFER_DATA_CTL, reg);
592
-
593
-		/* Select DPCD device address */
594
-		reg = AUX_ADDR_7_0(reg_addr);
595
-		analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_7_0, reg);
596
-		reg = AUX_ADDR_15_8(reg_addr);
597
-		analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_15_8, reg);
598
-		reg = AUX_ADDR_19_16(reg_addr);
599
-		analogix_dp_write(dp, ANALOGIX_DP_AUX_ADDR_19_16, reg);
600
-
601
-		/* Write data buffer */
602
-		reg = (unsigned int)data;
603
-		analogix_dp_write(dp, ANALOGIX_DP_BUF_DATA_0, reg);
604
-
605
-		/*
606
-		 * Set DisplayPort transaction and write 1 byte
607
-		 * If bit 3 is 1, DisplayPort transaction.
608
-		 * If Bit 3 is 0, I2C transaction.
609
-		 */
610
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
611
-		analogix_dp_write(dp, ANALOGIX_DP_AUX_CH_CTL_1, reg);
612
-
613
-		/* Start AUX transaction */
614
-		retval = analogix_dp_start_aux_transaction(dp);
615
-		if (retval == 0)
616
-			break;
617
-
618
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
619
-	}
620
-
621
-	return retval;
622
-}
623
-
624530 static void analogix_dp_ssc_enable(struct analogix_dp_device *dp)
625531 {
626532 	u32 reg;
627533 
628
-	writel(0x17, dp->reg_base + ANALOGIX_DP_SSC_REG);
534
+	/* 4500ppm */
535
+	writel(0x19, dp->reg_base + ANALOIGX_DP_SSC_REG);
629536 	/*
630537 	 * To apply updated SSC parameters into SSC operation,
631538 	 * firmware must disable and enable this bit.
....@@ -660,17 +567,18 @@
660567 	analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, bwtype);
661568 
662569 	if (dp->phy) {
663
-		union phy_configure_opts phy_cfg;
570
+		union phy_configure_opts phy_cfg = {0};
664571 
665572 		phy_cfg.dp.lanes = dp->link_train.lane_count;
666
-		phy_cfg.dp.link_rate = drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
573
+		phy_cfg.dp.link_rate =
574
+			drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
667575 		phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);
668576 		phy_cfg.dp.set_lanes = false;
669577 		phy_cfg.dp.set_rate = true;
670578 		phy_cfg.dp.set_voltages = false;
671579 		ret = phy_configure(dp->phy, &phy_cfg);
672580 		if (ret && ret != -EOPNOTSUPP) {
673
-			dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
581
+			dev_err(dp->dev, "%s: phy_configure failed: %d\n",
674582 				__func__, ret);
675583 			return;
676584 		}
....@@ -707,7 +615,7 @@
707615 	analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg);
708616 
709617 	if (dp->phy) {
710
-		union phy_configure_opts phy_cfg;
618
+		union phy_configure_opts phy_cfg = {0};
711619 
712620 		phy_cfg.dp.lanes = dp->link_train.lane_count;
713621 		phy_cfg.dp.set_lanes = true;
....@@ -730,86 +638,6 @@
730638 	*count = reg;
731639 }
732640 
733
-struct swing_pre_emp_ctrl {
734
-	u8 amp;
735
-	u8 emp;
736
-};
737
-
738
-static const struct swing_pre_emp_ctrl swing_pre_emp_ctrl_rbr[4][4] = {
739
-	/* voltage swing 0, pre-emphasis 0->3 */
740
-	{
741
-		{ .amp = 0x50, .emp = 0x00 },
742
-		{ .amp = 0x6c, .emp = 0x28 },
743
-		{ .amp = 0x80, .emp = 0x60 },
744
-		{ .amp = 0xb0, .emp = 0xc4 },
745
-	},
746
-	/* voltage swing 1, pre-emphasis 0->3 */
747
-	{
748
-		{ .amp = 0x78, .emp = 0x00 },
749
-		{ .amp = 0xa4, .emp = 0x50 },
750
-		{ .amp = 0xcc, .emp = 0xa6 },
751
-	},
752
-	/* voltage swing 2, pre-emphasis 0->3 */
753
-	{
754
-		{ .amp = 0xa0, .emp = 0x00 },
755
-		{ .amp = 0xe4, .emp = 0x72 },
756
-	},
757
-	/* voltage swing 3, pre-emphasis 0->3 */
758
-	{
759
-		{ .amp = 0xf0, .emp = 0x00 },
760
-	},
761
-};
762
-
763
-static const struct swing_pre_emp_ctrl swing_pre_emp_ctrl_hbr[4][4] = {
764
-	/* voltage swing 0, pre-emphasis 0->3 */
765
-	{
766
-		{ .amp = 0x50, .emp = 0x00 },
767
-		{ .amp = 0x6c, .emp = 0x34 },
768
-		{ .amp = 0x80, .emp = 0x64 },
769
-		{ .amp = 0xb8, .emp = 0xdc },
770
-	},
771
-	/* voltage swing 1, pre-emphasis 0->3 */
772
-	{
773
-		{ .amp = 0x78, .emp = 0x00 },
774
-		{ .amp = 0xa8, .emp = 0x58 },
775
-		{ .amp = 0xcc, .emp = 0xa8 },
776
-	},
777
-	/* voltage swing 2, pre-emphasis 0->3 */
778
-	{
779
-		{ .amp = 0xa0, .emp = 0x00 },
780
-		{ .amp = 0xdd, .emp = 0x74 },
781
-	},
782
-	/* voltage swing 3, pre-emphasis 0->3 */
783
-	{
784
-		{ .amp = 0xf0, .emp = 0x00 },
785
-	},
786
-};
787
-
788
-static const struct swing_pre_emp_ctrl swing_pre_emp_ctrl_hbr2[4][4] = {
789
-	/* voltage swing 0, pre-emphasis 0->3 */
790
-	{
791
-		{ .amp = 0x64, .emp = 0x1c },
792
-		{ .amp = 0x90, .emp = 0x78 },
793
-		{ .amp = 0xc4, .emp = 0xe0 },
794
-		{ .amp = 0xa0, .emp = 0xa0 },
795
-	},
796
-	/* voltage swing 1, pre-emphasis 0->3 */
797
-	{
798
-		{ .amp = 0x9c, .emp = 0x3c },
799
-		{ .amp = 0xe8, .emp = 0xd0 },
800
-		{ .amp = 0xb4, .emp = 0x78 },
801
-	},
802
-	/* voltage swing 2, pre-emphasis 0->3 */
803
-	{
804
-		{ .amp = 0xe0, .emp = 0x68 },
805
-		{ .amp = 0xe8, .emp = 0xd0 },
806
-	},
807
-	/* voltage swing 3, pre-emphasis 0->3 */
808
-	{
809
-		{ .amp = 0xf0, .emp = 0x00 },
810
-	},
811
-};
812
-
813641 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)
814642 {
815643 	u8 lane;
....@@ -821,7 +649,7 @@
821649 				  dp->link_train.training_lane[lane]);
822650 
823651 	if (dp->phy) {
824
-		union phy_configure_opts phy_cfg;
652
+		union phy_configure_opts phy_cfg = {0};
825653 
826654 		for (lane = 0; lane < dp->link_train.lane_count; lane++) {
827655 			u8 training_lane = dp->link_train.training_lane[lane];
....@@ -836,6 +664,8 @@
836664 		}
837665 
838666 		phy_cfg.dp.lanes = dp->link_train.lane_count;
667
+		phy_cfg.dp.link_rate =
668
+			drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
839669 		phy_cfg.dp.set_lanes = false;
840670 		phy_cfg.dp.set_rate = false;
841671 		phy_cfg.dp.set_voltages = true;
....@@ -844,63 +674,6 @@
844674 			dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
845675 				__func__, ret);
846676 			return;
847
-		}
848
-	} else {
849
-		const struct swing_pre_emp_ctrl *ctrl;
850
-
851
-		for (lane = 0; lane < dp->link_train.lane_count; lane++) {
852
-			u8 training_lane = dp->link_train.training_lane[lane];
853
-			u8 vs, pe;
854
-			u32 reg;
855
-
856
-			vs = (training_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
857
-			     DP_TRAIN_VOLTAGE_SWING_SHIFT;
858
-			pe = (training_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
859
-			     DP_TRAIN_PRE_EMPHASIS_SHIFT;
860
-
861
-			switch (dp->link_train.link_rate) {
862
-			case DP_LINK_BW_1_62:
863
-				ctrl = &swing_pre_emp_ctrl_rbr[vs][pe];
864
-				break;
865
-			case DP_LINK_BW_2_7:
866
-				ctrl = &swing_pre_emp_ctrl_hbr[vs][pe];
867
-				break;
868
-			case DP_LINK_BW_5_4:
869
-			default:
870
-				ctrl = &swing_pre_emp_ctrl_hbr2[vs][pe];
871
-				break;
872
-			}
873
-
874
-			switch (lane) {
875
-			case 0:
876
-				reg = analogix_dp_read(dp, ANALOGIX_DP_ANALOG_CTL_42);
877
-				reg |= R_FORCE_CH0_AMP | R_FORCE_CH0_EMP;
878
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_42, reg);
879
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_36, ctrl->amp);
880
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_37, ctrl->emp);
881
-				break;
882
-			case 1:
883
-				reg = analogix_dp_read(dp, ANALOGIX_DP_ANALOG_CTL_42);
884
-				reg |= R_FORCE_CH1_AMP | R_FORCE_CH1_EMP;
885
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_42, reg);
886
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_39, ctrl->amp);
887
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_40, ctrl->emp);
888
-				break;
889
-			case 2:
890
-				reg = analogix_dp_read(dp, ANALOGIX_DP_ANALOG_CTL_49);
891
-				reg |= R_FORCE_CH2_AMP | R_FORCE_CH2_EMP;
892
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_49, reg);
893
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_43, ctrl->amp);
894
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_44, ctrl->emp);
895
-				break;
896
-			case 3:
897
-				reg = analogix_dp_read(dp, ANALOGIX_DP_ANALOG_CTL_49);
898
-				reg |= R_FORCE_CH3_AMP | R_FORCE_CH3_EMP;
899
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_49, reg);
900
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_46, ctrl->amp);
901
-				analogix_dp_write(dp, ANALOGIX_DP_ANALOG_CTL_47, ctrl->emp);
902
-				break;
903
-			}
904677 		}
905678 	}
906679 }
....@@ -927,6 +700,15 @@
927700 	}
928701 }
929702 
703
+bool analogix_dp_get_enhanced_mode(struct analogix_dp_device *dp)
704
+{
705
+	u32 reg;
706
+
707
+	reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_4);
708
+
709
+	return !!(reg & ENHANCED);
710
+}
711
+
930712 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
931713 				      enum pattern_set pattern)
932714 {
....@@ -951,6 +733,22 @@
951733 		break;
952734 	case TRAINING_PTN3:
953735 		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN3;
736
+		analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
737
+		break;
738
+	case TEST_PATTERN_80BIT:
739
+		reg = 0x3e0f83e0;
740
+		analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN0, reg);
741
+		reg = 0x0f83e0f8;
742
+		analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN1, reg);
743
+		reg = 0x0000f83e;
744
+		analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN2, reg);
745
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_80BIT;
746
+		analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
747
+		break;
748
+	case TEST_PATTERN_HBR2:
749
+		reg = 0xfb;
750
+		analogix_dp_write(dp, ANALOGIX_DP_TEST_HBR2_PATTERN, reg);
751
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_HBR2;
954752 		analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);
955753 		break;
956754 	case DP_NONE:
....@@ -992,8 +790,11 @@
992790 	reg = CHA_CRI(4) | CHA_CTRL;
993791 	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, reg);
994792 
995
-	reg = 0x0;
996
-	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
793
+	if (dp->video_info.force_stream_valid) {
794
+		reg = analogix_dp_read(dp, ANALOGIX_DP_SYS_CTL_3);
795
+		reg |= VALID_CTRL | F_VALID;
796
+		analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, reg);
797
+	}
997798 
998799 	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
999800 	analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_8, reg);
....@@ -1206,8 +1007,26 @@
12061007 	return status;
12071008 }
12081009 
1010
+static void analogix_dp_reuse_spd(struct analogix_dp_device *dp)
1011
+{
1012
+	u32 reg, val;
1013
+
1014
+	switch (dp->plat_data->dev_type) {
1015
+	case RK3588_EDP:
1016
+		reg = ANALOGIX_DP_SPDIF_AUDIO_CTL_0;
1017
+		break;
1018
+	default:
1019
+		reg = ANALOGIX_DP_VIDEO_CTL_3;
1020
+		break;
1021
+	}
1022
+
1023
+	val = analogix_dp_read(dp, reg);
1024
+	val |= REUSE_SPD_EN;
1025
+	analogix_dp_write(dp, reg, val);
1026
+}
1027
+
12091028 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
1210
-			     struct edp_vsc_psr *vsc, bool blocking)
1029
+			     struct dp_sdp *vsc, bool blocking)
12111030 {
12121031 	unsigned int val;
12131032 	int ret;
....@@ -1235,13 +1054,16 @@
12351054 	analogix_dp_write(dp, ANALOGIX_DP_SPD_PB3, 0x5D);
12361055 
12371056 	/* configure DB0 / DB1 values */
1238
-	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_DB0, vsc->DB0);
1239
-	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_DB1, vsc->DB1);
1057
+	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_DB0, vsc->db[0]);
1058
+	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_DB1, vsc->db[1]);
1059
+
1060
+	/* configure PB0 / PB1 values */
1061
+	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_PB0,
1062
+			  vsc->db[1] ? 0x8d : 0x00);
1063
+	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_PB1, 0x00);
12401064 
12411065 	/* set reuse spd inforframe */
1242
-	val = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_3);
1243
-	val |= REUSE_SPD_EN;
1244
-	analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_3, val);
1066
+	analogix_dp_reuse_spd(dp);
12451067 
12461068 	/* mark info frame update */
12471069 	val = analogix_dp_read(dp, ANALOGIX_DP_PKT_SEND_CTL);
....@@ -1256,11 +1078,21 @@
12561078 	if (!blocking)
12571079 		return 0;
12581080 
1081
+	/*
1082
+	 * db[1]!=0: entering PSR, wait for fully active remote frame buffer.
1083
+	 * db[1]==0: exiting PSR, wait for either
1084
+	 *  (a) ACTIVE_RESYNC - the sink "must display the
1085
+	 *      incoming active frames from the Source device with no visible
1086
+	 *      glitches and/or artifacts", even though timings may still be
1087
+	 *      re-synchronizing; or
1088
+	 *  (b) INACTIVE - the transition is fully complete.
1089
+	 */
12591090 	ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status,
12601091 		psr_status >= 0 &&
1261
-		((vsc->DB1 && psr_status == DP_PSR_SINK_ACTIVE_RFB) ||
1262
-		(!vsc->DB1 && psr_status == DP_PSR_SINK_INACTIVE)), 1500,
1263
-		DP_TIMEOUT_PSR_LOOP_MS * 1000);
1092
+		((vsc->db[1] && psr_status == DP_PSR_SINK_ACTIVE_RFB) ||
1093
+		(!vsc->db[1] && (psr_status == DP_PSR_SINK_ACTIVE_RESYNC ||
1094
+				 psr_status == DP_PSR_SINK_INACTIVE))),
1095
+		1500, DP_TIMEOUT_PSR_LOOP_MS * 1000);
12641096 	if (ret) {
12651097 		dev_warn(dp->dev, "Failed to apply PSR %d\n", ret);
12661098 		return ret;
....@@ -1268,31 +1100,46 @@
12681100 	return 0;
12691101 }
12701102 
1271
-void analogix_dp_phy_power_on(struct analogix_dp_device *dp)
1103
+int analogix_dp_phy_power_on(struct analogix_dp_device *dp)
12721104 {
1273
-	if (dp->phy_enabled)
1274
-		return;
1105
+	int ret;
12751106 
1276
-	phy_power_on(dp->phy);
1107
+	ret = phy_set_mode(dp->phy, PHY_MODE_DP);
1108
+	if (ret) {
1109
+		dev_err(dp->dev, "phy_set_mode failed: %d\n", ret);
1110
+		return ret;
1111
+	}
12771112 
1278
-	dp->phy_enabled = true;
1113
+	ret = phy_power_on(dp->phy);
1114
+	if (ret) {
1115
+		dev_err(dp->dev, "phy_power_on failed: %d\n", ret);
1116
+		return ret;
1117
+	}
1118
+
1119
+	return ret;
12791120 }
12801121 
12811122 void analogix_dp_phy_power_off(struct analogix_dp_device *dp)
12821123 {
1283
-	if (!dp->phy_enabled)
1284
-		return;
1285
-
12861124 	phy_power_off(dp->phy);
1287
-
1288
-	dp->phy_enabled = false;
12891125 }
1126
+
1127
+enum {
1128
+	AUX_STATUS_OK,
1129
+	AUX_STATUS_NACK_ERROR,
1130
+	AUX_STATUS_TIMEOUT_ERROR,
1131
+	AUX_STATUS_UNKNOWN_ERROR,
1132
+	AUX_STATUS_MUCH_DEFER_ERROR,
1133
+	AUX_STATUS_TX_SHORT_ERROR,
1134
+	AUX_STATUS_RX_SHORT_ERROR,
1135
+	AUX_STATUS_NACK_WITHOUT_M_ERROR,
1136
+	AUX_STATUS_I2C_NACK_ERROR
1137
+};
12901138 
12911139 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
12921140 			     struct drm_dp_aux_msg *msg)
12931141 {
12941142 	u32 reg;
1295
-	u32 status_reg;
12961143 	u8 *buffer = msg->buffer;
12971144 	unsigned int i;
12981145 	int num_transferred = 0;
....@@ -1301,12 +1148,6 @@
13011148 	/* Buffer size of AUX CH is 16 bytes */
13021149 	if (WARN_ON(msg->size > 16))
13031150 		return -E2BIG;
1304
-
1305
-	reg = analogix_dp_read(dp, ANALOGIX_DP_FUNC_EN_2);
1306
-	if (reg & AUX_FUNC_EN_N) {
1307
-		analogix_dp_phy_power_on(dp);
1308
-		analogix_dp_init_aux(dp);
1309
-	}
13101151 
13111152 	/* Clear AUX CH data buffer */
13121153 	reg = BUF_CLR;
....@@ -1385,18 +1226,19 @@
13851226 	/* Clear interrupt source for AUX CH command reply */
13861227 	analogix_dp_write(dp, ANALOGIX_DP_INT_STA, RPLY_RECEIV);
13871228 
1388
-	/* Clear interrupt source for AUX CH access error */
1389
-	reg = analogix_dp_read(dp, ANALOGIX_DP_INT_STA);
1390
-	status_reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA);
1391
-	if ((reg & AUX_ERR) || (status_reg & AUX_STATUS_MASK)) {
1392
-		analogix_dp_write(dp, ANALOGIX_DP_INT_STA, AUX_ERR);
1393
-
1394
-		dev_warn(dp->dev, "AUX CH error happened: %#x (%d)\n",
1395
-			 status_reg & AUX_STATUS_MASK, !!(reg & AUX_ERR));
1396
-		goto aux_error;
1397
-	}
1229
+	reg = analogix_dp_read(dp, ANALOGIX_DP_AUX_CH_STA);
1230
+	if ((reg & AUX_STATUS_MASK) == AUX_STATUS_TIMEOUT_ERROR)
1231
+		return -ETIMEDOUT;
13981232 
13991233 	if (msg->request & DP_AUX_I2C_READ) {
1234
+		size_t buf_data_count;
1235
+
1236
+		reg = analogix_dp_read(dp, ANALOGIX_DP_BUFFER_DATA_CTL);
1237
+		buf_data_count = BUF_DATA_COUNT(reg);
1238
+
1239
+		if (buf_data_count != msg->size)
1240
+			return -EBUSY;
1241
+
14001242 		for (i = 0; i < msg->size; i++) {
14011243 			reg = analogix_dp_read(dp, ANALOGIX_DP_BUF_DATA_0 +
14021244 					       4 * i);
....@@ -1542,3 +1384,11 @@
15421384 	reg |= AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N;
15431385 	analogix_dp_write(dp, ANALOGIX_DP_FUNC_EN_1, reg);
15441386 }
1387
+
1388
+void analogix_dp_init(struct analogix_dp_device *dp)
1389
+{
1390
+	analogix_dp_init_interrupt(dp);
1391
+	analogix_dp_config_interrupt(dp);
1392
+	analogix_dp_init_hpd(dp);
1393
+	analogix_dp_init_aux(dp);
1394
+}