add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/arm/malidp_regs.h
..
..
@@ -1,11 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /*
2
3
  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
3
4
  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
4
- *
5
- * This program is free software and is provided to you under the terms of the
6
- * GNU General Public License version 2 as published by the Free Software
7
- * Foundation, and any use by you of this program is subject to the terms
8
- * of such GNU licence.
9
5
  *
10
6
  * ARM Mali DP500/DP550/DP650 registers definition.
11
7
  */
..
..
@@ -198,10 +194,13 @@
198
194
 #define MALIDP500_LV_YUV2RGB		((s16)(-0xB8))
199
195
 #define MALIDP500_DE_LV_BASE		0x00100
200
196
 #define MALIDP500_DE_LV_PTR_BASE	0x00124
197
+#define MALIDP500_DE_LV_AD_CTRL		0x00400
201
198
 #define MALIDP500_DE_LG1_BASE		0x00200
202
199
 #define MALIDP500_DE_LG1_PTR_BASE	0x0021c
200
+#define MALIDP500_DE_LG1_AD_CTRL	0x0040c
203
201
 #define MALIDP500_DE_LG2_BASE		0x00300
204
202
 #define MALIDP500_DE_LG2_PTR_BASE	0x0031c
203
+#define MALIDP500_DE_LG2_AD_CTRL	0x00418
205
204
 #define MALIDP500_SE_BASE		0x00c00
206
205
 #define MALIDP500_SE_CONTROL		0x00c0c
207
206
 #define MALIDP500_SE_MEMWRITE_OUT_SIZE	0x00c2c
..
..
@@ -210,6 +209,16 @@
210
209
 #define MALIDP500_DC_IRQ_BASE		0x00f00
211
210
 #define MALIDP500_CONFIG_VALID		0x00f00
212
211
 #define MALIDP500_CONFIG_ID		0x00fd4
212
+
213
+/*
214
+ * The quality of service (QoS) register on the DP500. RQOS register values
215
+ * are driven by the ARQOS signal, using AXI transacations, dependent on the
216
+ * FIFO input level.
217
+ * The RQOS register can also set QoS levels for:
218
+ *    - RED_ARQOS   @ A 4-bit signal value for close to underflow conditions
219
+ *    - GREEN_ARQOS @ A 4-bit signal value for normal conditions
220
+ */
221
+#define MALIDP500_RQOS_QUALITY          0x00500
213
222
 
214
223
 /* register offsets and bits specific to DP550/DP650 */
215
224
 #define MALIDP550_ADDR_SPACE_SIZE	0x10000
..
..
@@ -228,10 +237,13 @@
228
237
 #define MALIDP550_LV_YUV2RGB		0x00084
229
238
 #define MALIDP550_DE_LV1_BASE		0x00100
230
239
 #define MALIDP550_DE_LV1_PTR_BASE	0x00124
240
+#define MALIDP550_DE_LV1_AD_CTRL	0x001B8
231
241
 #define MALIDP550_DE_LV2_BASE		0x00200
232
242
 #define MALIDP550_DE_LV2_PTR_BASE	0x00224
243
+#define MALIDP550_DE_LV2_AD_CTRL	0x002B8
233
244
 #define MALIDP550_DE_LG_BASE		0x00300
234
245
 #define MALIDP550_DE_LG_PTR_BASE	0x0031c
246
+#define MALIDP550_DE_LG_AD_CTRL		0x00330
235
247
 #define MALIDP550_DE_LS_BASE		0x00400
236
248
 #define MALIDP550_DE_LS_PTR_BASE	0x0042c
237
249
 #define MALIDP550_DE_PERF_BASE		0x00500
..
..
@@ -247,6 +259,31 @@
247
259
 #define MALIDP550_CONFIG_VALID		0x0c014
248
260
 #define MALIDP550_CONFIG_ID		0x0ffd4
249
261
 
262
+/* register offsets specific to DP650 */
263
+#define MALIDP650_DE_LV_MMU_CTRL	0x000D0
264
+#define MALIDP650_DE_LG_MMU_CTRL	0x00048
265
+#define MALIDP650_DE_LS_MMU_CTRL	0x00078
266
+
267
+/* bit masks to set the MMU control register */
268
+#define MALIDP_MMU_CTRL_EN		(1 << 0)
269
+#define MALIDP_MMU_CTRL_MODE		(1 << 4)
270
+#define MALIDP_MMU_CTRL_PX_PS(x)	(1 << (8 + (x)))
271
+#define MALIDP_MMU_CTRL_PP_NUM_REQ(x)	(((x) & 0x7f) << 12)
272
+
273
+/* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */
274
+/* The following register offsets are common for DP500, DP550 and DP650 */
275
+#define MALIDP_AD_CROP_H                0x4
276
+#define MALIDP_AD_CROP_V                0x8
277
+#define MALIDP_AD_END_PTR_LOW           0xc
278
+#define MALIDP_AD_END_PTR_HIGH          0x10
279
+
280
+/* AFBC decoder Registers */
281
+#define MALIDP_AD_EN                    BIT(0)
282
+#define MALIDP_AD_YTR                   BIT(4)
283
+#define MALIDP_AD_BS                    BIT(8)
284
+#define MALIDP_AD_CROP_RIGHT_OFFSET     16
285
+#define MALIDP_AD_CROP_BOTTOM_OFFSET    16
286
+
250
287
 /*
251
288
  * Starting with DP550 the register map blocks has been standardised to the
252
289
  * following layout: