forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
....@@ -42,20 +42,27 @@
4242 		int mpcc_id)
4343 {
4444 	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
45
+	struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
46
+	uint32_t bg_r_cr, bg_g_y, bg_b_cb;
47
+
48
+	/* find bottommost mpcc. */
49
+	while (bottommost_mpcc->mpcc_bot) {
50
+		bottommost_mpcc = bottommost_mpcc->mpcc_bot;
51
+	}
4552 
4653 	/* mpc color is 12 bit.  tg_color is 10 bit */
4754 	/* todo: might want to use 16 bit to represent color and have each
4855 	 * hw block translate to correct color depth.
4956 	 */
50
-	uint32_t bg_r_cr = bg_color->color_r_cr << 2;
51
-	uint32_t bg_g_y = bg_color->color_g_y << 2;
52
-	uint32_t bg_b_cb = bg_color->color_b_cb << 2;
57
+	bg_r_cr = bg_color->color_r_cr << 2;
58
+	bg_g_y = bg_color->color_g_y << 2;
59
+	bg_b_cb = bg_color->color_b_cb << 2;
5360 
54
-	REG_SET(MPCC_BG_R_CR[mpcc_id], 0,
61
+	REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
5562 			MPCC_BG_R_CR, bg_r_cr);
56
-	REG_SET(MPCC_BG_G_Y[mpcc_id], 0,
63
+	REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
5764 			MPCC_BG_G_Y, bg_g_y);
58
-	REG_SET(MPCC_BG_B_CB[mpcc_id], 0,
65
+	REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
5966 			MPCC_BG_B_CB, bg_b_cb);
6067 }
6168 
....@@ -118,6 +125,12 @@
118125 	while (tmp_mpcc != NULL) {
119126 		if (tmp_mpcc->dpp_id == dpp_id)
120127 			return tmp_mpcc;
128
+
129
+		/* avoid circular linked list */
130
+		ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);
131
+		if (tmp_mpcc == tmp_mpcc->mpcc_bot)
132
+			break;
133
+
121134 		tmp_mpcc = tmp_mpcc->mpcc_bot;
122135 	}
123136 	return NULL;
....@@ -211,10 +224,13 @@
211224 	} else {
212225 		new_mpcc->mpcc_bot = NULL;
213226 		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
214
-		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
227
+		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
215228 	}
216229 	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
217230 	REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
231
+
232
+	/* Configure VUPDATE lock set for this MPCC to map to the OPP */
233
+	REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
218234 
219235 	/* update mpc tree mux setting */
220236 	if (tree->opp_list == insert_above_mpcc) {
....@@ -311,6 +327,7 @@
311327 		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
312328 		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
313329 		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
330
+		REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
314331 
315332 		/* mark this mpcc as not in use */
316333 		mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
....@@ -321,6 +338,7 @@
321338 		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
322339 		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
323340 		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
341
+		REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
324342 	}
325343 }
326344 
....@@ -354,6 +372,7 @@
354372 		REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
355373 		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
356374 		REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
375
+		REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
357376 
358377 		mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
359378 	}
....@@ -363,6 +382,25 @@
363382 			REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
364383 	}
365384 }
385
+
386
+void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
387
+{
388
+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
389
+	int opp_id;
390
+
391
+	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
392
+
393
+	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
394
+	REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
395
+	REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
396
+	REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
397
+
398
+	mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
399
+
400
+	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
401
+		REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
402
+}
403
+
366404 
367405 void mpc1_init_mpcc_list_from_hw(
368406 	struct mpc *mpc,
....@@ -428,16 +466,29 @@
428466 			MPCC_BUSY, &s->busy);
429467 }
430468 
469
+void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
470
+{
471
+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
472
+
473
+	REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
474
+}
475
+
431476 static const struct mpc_funcs dcn10_mpc_funcs = {
432477 	.read_mpcc_state = mpc1_read_mpcc_state,
433478 	.insert_plane = mpc1_insert_plane,
434479 	.remove_mpcc = mpc1_remove_mpcc,
435480 	.mpc_init = mpc1_mpc_init,
481
+	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
436482 	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
437483 	.wait_for_idle = mpc1_assert_idle_mpcc,
438484 	.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
439485 	.init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
440486 	.update_blending = mpc1_update_blending,
487
+	.cursor_lock = mpc1_cursor_lock,
488
+	.set_denorm = NULL,
489
+	.set_denorm_clamp = NULL,
490
+	.set_output_csc = NULL,
491
+	.set_output_gamma = NULL,
441492 };
442493 
443494 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,