add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
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@@ -25,7 +25,7 @@
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 #include "dm_services.h"
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 #include "dc.h"
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 #include "core_types.h"
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-#include "hw_sequencer.h"
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+#include "clk_mgr.h"
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 #include "dce100_hw_sequencer.h"
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 #include "resource.h"
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@@ -105,73 +105,29 @@
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 		return false;
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 }
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-static void dce100_pplib_apply_display_requirements(
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-	struct dc *dc,
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-	struct dc_state *context)
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-{
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-	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
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-
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-	pp_display_cfg->avail_mclk_switch_time_us =
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-						dce110_get_min_vblank_time_us(context);
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-	/*pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
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-		/ MEMORY_TYPE_MULTIPLIER;*/
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-
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-	dce110_fill_display_configs(context, pp_display_cfg);
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-
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-	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
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-			struct dm_pp_display_configuration)) !=  0)
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-		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
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-
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-	dc->prev_display_config = *pp_display_cfg;
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-}
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-
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-/* unit: in_khz before mode set, get pixel clock from context. ASIC register
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- * may not be programmed yet
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- */
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-static uint32_t get_max_pixel_clock_for_all_paths(
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-	struct dc *dc,
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-	struct dc_state *context)
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-{
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-	uint32_t max_pix_clk = 0;
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-	int i;
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-
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-	for (i = 0; i < MAX_PIPES; i++) {
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-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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-
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-		if (pipe_ctx->stream == NULL)
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-			continue;
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-
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-		/* do not check under lay */
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-		if (pipe_ctx->top_pipe)
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-			continue;
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-
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-		if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
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-			max_pix_clk =
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-				pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
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-	}
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-	return max_pix_clk;
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-}
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-
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-void dce100_set_bandwidth(
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+void dce100_prepare_bandwidth(
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 		struct dc *dc,
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-		struct dc_state *context,
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-		bool decrease_allowed)
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+		struct dc_state *context)
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 {
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-	struct dc_clocks req_clks;
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-
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-	req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
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-	req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);
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-
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 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
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113
 
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-	dc->res_pool->dccg->funcs->update_clocks(
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-			dc->res_pool->dccg,
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-			&req_clks,
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-			decrease_allowed);
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-
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-	dce100_pplib_apply_display_requirements(dc, context);
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+	dc->clk_mgr->funcs->update_clocks(
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+			dc->clk_mgr,
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+			context,
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+			false);
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 }
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119
 
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+void dce100_optimize_bandwidth(
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+		struct dc *dc,
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+		struct dc_state *context)
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+{
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+	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
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+
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+	dc->clk_mgr->funcs->update_clocks(
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+			dc->clk_mgr,
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+			context,
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+			true);
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+}
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 /**************************************************************************/
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..
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@@ -179,9 +135,8 @@
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 {
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 	dce110_hw_sequencer_construct(dc);
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-	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
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-	dc->hwss.set_bandwidth = dce100_set_bandwidth;
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-	dc->hwss.pplib_apply_display_requirements =
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-			dce100_pplib_apply_display_requirements;
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+	dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
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+	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
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+	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
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 }
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