forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
....@@ -55,7 +55,66 @@
5555 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
5656 	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
5757 
58
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
58
+#define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
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+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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+		SRII(PHASE, DP_DTO, 0),\
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+		SRII(PHASE, DP_DTO, 1),\
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+		SRII(PHASE, DP_DTO, 2),\
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+		SRII(PHASE, DP_DTO, 3),\
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+		SRII(PHASE, DP_DTO, 4),\
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+		SRII(PHASE, DP_DTO, 5),\
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+		SRII(MODULO, DP_DTO, 0),\
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+		SRII(MODULO, DP_DTO, 1),\
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+		SRII(MODULO, DP_DTO, 2),\
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+		SRII(MODULO, DP_DTO, 3),\
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+		SRII(MODULO, DP_DTO, 4),\
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+		SRII(MODULO, DP_DTO, 5),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 0),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 1),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 2),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 3),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 4),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 5)
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+
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+#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
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+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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+		SRII(PHASE, DP_DTO, 0),\
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+		SRII(PHASE, DP_DTO, 1),\
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+		SRII(PHASE, DP_DTO, 2),\
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+		SRII(PHASE, DP_DTO, 3),\
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+		SRII(MODULO, DP_DTO, 0),\
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+		SRII(MODULO, DP_DTO, 1),\
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+		SRII(MODULO, DP_DTO, 2),\
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+		SRII(MODULO, DP_DTO, 3),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 0),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 1),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 2),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 3)
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+
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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+#define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
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+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
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+		SRII(PHASE, DP_DTO, 0),\
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+		SRII(PHASE, DP_DTO, 1),\
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+		SRII(PHASE, DP_DTO, 2),\
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+		SRII(PHASE, DP_DTO, 3),\
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+		SRII(MODULO, DP_DTO, 0),\
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+		SRII(MODULO, DP_DTO, 1),\
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+		SRII(MODULO, DP_DTO, 2),\
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+		SRII(MODULO, DP_DTO, 3),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 0),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 1),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 2),\
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+		SRII(PIXEL_RATE_CNTL, OTG, 3)
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+#endif
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+
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+#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
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+	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
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+	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
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+	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
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+	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
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+
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+#if defined(CONFIG_DRM_AMD_DC_DCN)
59118 
60119 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
61120 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
....@@ -125,6 +184,8 @@
125184 	uint32_t hdmi_ss_params_cnt;
126185 	struct spread_spectrum_data *dvi_ss_params;
127186 	uint32_t dvi_ss_params_cnt;
187
+	struct spread_spectrum_data *lvds_ss_params;
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+	uint32_t lvds_ss_params_cnt;
128189 
129190 	uint32_t ext_clk_khz;
130191 	uint32_t ref_freq_khz;
....@@ -142,4 +203,47 @@
142203 	const struct dce110_clk_src_shift *cs_shift,
143204 	const struct dce110_clk_src_mask *cs_mask);
144205 
206
+bool dce112_clk_src_construct(
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+	struct dce110_clk_src *clk_src,
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+	struct dc_context *ctx,
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+	struct dc_bios *bios,
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+	enum clock_source_id id,
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+	const struct dce110_clk_src_regs *regs,
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+	const struct dce110_clk_src_shift *cs_shift,
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+	const struct dce110_clk_src_mask *cs_mask);
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+
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+bool dcn20_clk_src_construct(
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+	struct dce110_clk_src *clk_src,
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+	struct dc_context *ctx,
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+	struct dc_bios *bios,
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+	enum clock_source_id id,
220
+	const struct dce110_clk_src_regs *regs,
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+	const struct dce110_clk_src_shift *cs_shift,
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+	const struct dce110_clk_src_mask *cs_mask);
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+
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
225
+bool dcn3_clk_src_construct(
226
+	struct dce110_clk_src *clk_src,
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+	struct dc_context *ctx,
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+	struct dc_bios *bios,
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+	enum clock_source_id id,
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+	const struct dce110_clk_src_regs *regs,
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+	const struct dce110_clk_src_shift *cs_shift,
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+	const struct dce110_clk_src_mask *cs_mask);
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+#endif
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+
235
+/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
236
+struct pixel_rate_range_table_entry {
237
+	unsigned int range_min_khz;
238
+	unsigned int range_max_khz;
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+	unsigned int target_pixel_rate_khz;
240
+	unsigned short mult_factor;
241
+	unsigned short div_factor;
242
+};
243
+
244
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
245
+extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
246
+const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
247
+		unsigned int pixel_rate_khz);
248
+#endif
145249 #endif