.. | .. |
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| 1 | +# SPDX-License-Identifier: MIT |
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1 | 2 | menu "Display Engine Configuration" |
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2 | 3 | depends on DRM && DRM_AMDGPU |
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3 | 4 | |
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4 | 5 | config DRM_AMD_DC |
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5 | 6 | bool "AMD DC - Enable new display engine" |
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6 | 7 | default y |
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7 | | - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) |
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| 8 | + depends on BROKEN || !CC_IS_CLANG || X86_64 || SPARC64 || ARM64 |
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| 9 | + select SND_HDA_COMPONENT if SND_HDA_CORE |
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| 10 | + select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) |
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8 | 11 | help |
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9 | 12 | Choose this option if you want to use the new display engine |
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10 | 13 | support for AMDGPU. This adds required support for Vega and |
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11 | 14 | Raven ASICs. |
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12 | 15 | |
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13 | | -config DRM_AMD_DC_DCN1_0 |
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| 16 | + calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64) |
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| 17 | + architectures built with Clang (all released versions), whereby the stack |
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| 18 | + frame gets blown up to well over 5k. This would cause an immediate kernel |
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| 19 | + panic on most architectures. We'll revert this when the following bug report |
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| 20 | + has been resolved: https://github.com/llvm/llvm-project/issues/41896. |
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| 21 | + |
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| 22 | +config DRM_AMD_DC_DCN |
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14 | 23 | def_bool n |
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15 | 24 | help |
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16 | | - RV family support for display engine |
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| 25 | + Raven, Navi and Renoir family support for display engine |
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| 26 | + |
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| 27 | +config DRM_AMD_DC_DCN3_0 |
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| 28 | + bool "DCN 3.0 family" |
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| 29 | + depends on DRM_AMD_DC && X86 |
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| 30 | + depends on DRM_AMD_DC_DCN |
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| 31 | + help |
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| 32 | + Choose this option if you want to have |
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| 33 | + sienna_cichlid support for display engine |
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| 34 | + |
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| 35 | +config DRM_AMD_DC_HDCP |
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| 36 | + bool "Enable HDCP support in DC" |
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| 37 | + depends on DRM_AMD_DC |
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| 38 | + help |
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| 39 | + Choose this option if you want to support HDCP authentication. |
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| 40 | + |
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| 41 | +config DRM_AMD_DC_SI |
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| 42 | + bool "AMD DC support for Southern Islands ASICs" |
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| 43 | + depends on DRM_AMDGPU_SI |
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| 44 | + depends on DRM_AMD_DC |
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| 45 | + default n |
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| 46 | + help |
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| 47 | + Choose this option to enable new AMD DC support for SI asics |
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| 48 | + by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. |
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| 49 | + Hainan is not supported by AMD DC and it has no physical DCE6. |
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17 | 50 | |
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18 | 51 | config DEBUG_KERNEL_DC |
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19 | 52 | bool "Enable kgdb break in DC" |
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20 | 53 | depends on DRM_AMD_DC |
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| 54 | + depends on KGDB |
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21 | 55 | help |
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22 | | - Choose this option |
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23 | | - if you want to hit |
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24 | | - kdgb_break in assert. |
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| 56 | + Choose this option if you want to hit kdgb_break in assert. |
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25 | 57 | |
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26 | 58 | endmenu |
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