.. | .. |
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27 | 27 | #include <linux/list.h> |
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28 | 28 | #include "kfd_crat.h" |
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29 | 29 | |
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30 | | -#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128 |
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| 30 | +#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32 |
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31 | 31 | |
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32 | 32 | #define HSA_CAP_HOT_PLUGGABLE 0x00000001 |
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33 | 33 | #define HSA_CAP_ATS_PRESENT 0x00000002 |
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41 | 41 | #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8 |
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42 | 42 | #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000 |
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43 | 43 | #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12 |
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44 | | -#define HSA_CAP_RESERVED 0xffffc000 |
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45 | 44 | |
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46 | 45 | #define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0 |
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47 | 46 | #define HSA_CAP_DOORBELL_TYPE_1_0 0x1 |
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48 | 47 | #define HSA_CAP_DOORBELL_TYPE_2_0 0x2 |
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49 | 48 | #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000 |
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50 | 49 | |
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| 50 | +#define HSA_CAP_SRAM_EDCSUPPORTED 0x00080000 |
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| 51 | +#define HSA_CAP_MEM_EDCSUPPORTED 0x00100000 |
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| 52 | +#define HSA_CAP_RASEVENTNOTIFY 0x00200000 |
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| 53 | +#define HSA_CAP_ASIC_REVISION_MASK 0x03c00000 |
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| 54 | +#define HSA_CAP_ASIC_REVISION_SHIFT 22 |
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| 55 | + |
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| 56 | +#define HSA_CAP_RESERVED 0xfc078000 |
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| 57 | + |
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51 | 58 | struct kfd_node_properties { |
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| 59 | + uint64_t hive_id; |
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| 60 | + uint64_t unique_id; |
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52 | 61 | uint32_t cpu_cores_count; |
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53 | 62 | uint32_t simd_count; |
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54 | 63 | uint32_t mem_banks_count; |
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60 | 69 | uint32_t max_waves_per_simd; |
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61 | 70 | uint32_t lds_size_in_kb; |
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62 | 71 | uint32_t gds_size_in_kb; |
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| 72 | + uint32_t num_gws; |
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63 | 73 | uint32_t wave_front_size; |
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64 | 74 | uint32_t array_count; |
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65 | 75 | uint32_t simd_arrays_per_engine; |
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70 | 80 | uint32_t vendor_id; |
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71 | 81 | uint32_t device_id; |
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72 | 82 | uint32_t location_id; |
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| 83 | + uint32_t domain; |
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73 | 84 | uint32_t max_engine_clk_fcompute; |
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74 | 85 | uint32_t max_engine_clk_ccompute; |
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75 | 86 | int32_t drm_render_minor; |
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76 | | - uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE]; |
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| 87 | + uint32_t num_sdma_engines; |
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| 88 | + uint32_t num_sdma_xgmi_engines; |
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| 89 | + uint32_t num_sdma_queues_per_engine; |
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| 90 | + uint32_t num_cp_queues; |
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| 91 | + char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE]; |
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77 | 92 | }; |
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78 | 93 | |
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79 | 94 | #define HSA_MEM_HEAP_TYPE_SYSTEM 0 |
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.. | .. |
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94 | 109 | uint32_t flags; |
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95 | 110 | uint32_t width; |
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96 | 111 | uint32_t mem_clk_max; |
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| 112 | + struct kfd_dev *gpu; |
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97 | 113 | struct kobject *kobj; |
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98 | 114 | struct attribute attr; |
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99 | 115 | }; |
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115 | 131 | uint32_t cache_latency; |
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116 | 132 | uint32_t cache_type; |
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117 | 133 | uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE]; |
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| 134 | + struct kfd_dev *gpu; |
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118 | 135 | struct kobject *kobj; |
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119 | 136 | struct attribute attr; |
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120 | 137 | }; |
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133 | 150 | uint32_t max_bandwidth; |
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134 | 151 | uint32_t rec_transfer_size; |
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135 | 152 | uint32_t flags; |
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| 153 | + struct kfd_dev *gpu; |
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136 | 154 | struct kobject *kobj; |
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137 | 155 | struct attribute attr; |
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138 | 156 | }; |
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