forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/vi.c
....@@ -20,8 +20,10 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  *
2222  */
23
+
24
+#include <linux/pci.h>
2325 #include <linux/slab.h>
24
-#include <drm/drmP.h>
26
+
2527 #include "amdgpu.h"
2628 #include "amdgpu_atombios.h"
2729 #include "amdgpu_ih.h"
....@@ -57,7 +59,6 @@
5759 
5860 #include "vid.h"
5961 #include "vi.h"
60
-#include "vi_dpm.h"
6162 #include "gmc_v8_0.h"
6263 #include "gmc_v7_0.h"
6364 #include "gfx_v8_0.h"
....@@ -87,9 +88,9 @@
8788 	u32 r;
8889 
8990 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
90
-	WREG32(mmPCIE_INDEX, reg);
91
-	(void)RREG32(mmPCIE_INDEX);
92
-	r = RREG32(mmPCIE_DATA);
91
+	WREG32_NO_KIQ(mmPCIE_INDEX, reg);
92
+	(void)RREG32_NO_KIQ(mmPCIE_INDEX);
93
+	r = RREG32_NO_KIQ(mmPCIE_DATA);
9394 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
9495 	return r;
9596 }
....@@ -99,10 +100,10 @@
99100 	unsigned long flags;
100101 
101102 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
102
-	WREG32(mmPCIE_INDEX, reg);
103
-	(void)RREG32(mmPCIE_INDEX);
104
-	WREG32(mmPCIE_DATA, v);
105
-	(void)RREG32(mmPCIE_DATA);
103
+	WREG32_NO_KIQ(mmPCIE_INDEX, reg);
104
+	(void)RREG32_NO_KIQ(mmPCIE_INDEX);
105
+	WREG32_NO_KIQ(mmPCIE_DATA, v);
106
+	(void)RREG32_NO_KIQ(mmPCIE_DATA);
106107 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
107108 }
108109 
....@@ -123,8 +124,8 @@
123124 	unsigned long flags;
124125 
125126 	spin_lock_irqsave(&adev->smc_idx_lock, flags);
126
-	WREG32(mmSMC_IND_INDEX_11, (reg));
127
-	WREG32(mmSMC_IND_DATA_11, (v));
127
+	WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
128
+	WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
128129 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
129130 }
130131 
....@@ -447,27 +448,6 @@
447448 	return true;
448449 }
449450 
450
-static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
451
-{
452
-	uint32_t reg = 0;
453
-
454
-	if (adev->asic_type == CHIP_TONGA ||
455
-	    adev->asic_type == CHIP_FIJI) {
456
-	       reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
457
-	       /* bit0: 0 means pf and 1 means vf */
458
-	       if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
459
-		       adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
460
-	       /* bit31: 0 means disable IOV and 1 means enable */
461
-	       if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
462
-		       adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
463
-	}
464
-
465
-	if (reg == 0) {
466
-		if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
467
-			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
468
-	}
469
-}
470
-
471451 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
472452 	{mmGRBM_STATUS},
473453 	{mmGRBM_STATUS2},
....@@ -689,6 +669,76 @@
689669 }
690670 
691671 /**
672
+ * vi_asic_pci_config_reset - soft reset GPU
673
+ *
674
+ * @adev: amdgpu_device pointer
675
+ *
676
+ * Use PCI Config method to reset the GPU.
677
+ *
678
+ * Returns 0 for success.
679
+ */
680
+static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
681
+{
682
+	int r;
683
+
684
+	amdgpu_atombios_scratch_regs_engine_hung(adev, true);
685
+
686
+	r = vi_gpu_pci_config_reset(adev);
687
+
688
+	amdgpu_atombios_scratch_regs_engine_hung(adev, false);
689
+
690
+	return r;
691
+}
692
+
693
+static bool vi_asic_supports_baco(struct amdgpu_device *adev)
694
+{
695
+	switch (adev->asic_type) {
696
+	case CHIP_FIJI:
697
+	case CHIP_TONGA:
698
+	case CHIP_POLARIS10:
699
+	case CHIP_POLARIS11:
700
+	case CHIP_POLARIS12:
701
+	case CHIP_TOPAZ:
702
+		return amdgpu_dpm_is_baco_supported(adev);
703
+	default:
704
+		return false;
705
+	}
706
+}
707
+
708
+static enum amd_reset_method
709
+vi_asic_reset_method(struct amdgpu_device *adev)
710
+{
711
+	bool baco_reset;
712
+
713
+	if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||
714
+	    amdgpu_reset_method == AMD_RESET_METHOD_BACO)
715
+		return amdgpu_reset_method;
716
+
717
+	if (amdgpu_reset_method != -1)
718
+		dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
719
+				  amdgpu_reset_method);
720
+
721
+	switch (adev->asic_type) {
722
+	case CHIP_FIJI:
723
+	case CHIP_TONGA:
724
+	case CHIP_POLARIS10:
725
+	case CHIP_POLARIS11:
726
+	case CHIP_POLARIS12:
727
+	case CHIP_TOPAZ:
728
+		baco_reset = amdgpu_dpm_is_baco_supported(adev);
729
+		break;
730
+	default:
731
+		baco_reset = false;
732
+		break;
733
+	}
734
+
735
+	if (baco_reset)
736
+		return AMD_RESET_METHOD_BACO;
737
+	else
738
+		return AMD_RESET_METHOD_LEGACY;
739
+}
740
+
741
+/**
692742  * vi_asic_reset - soft reset GPU
693743  *
694744  * @adev: amdgpu_device pointer
....@@ -701,11 +751,13 @@
701751 {
702752 	int r;
703753 
704
-	amdgpu_atombios_scratch_regs_engine_hung(adev, true);
705
-
706
-	r = vi_gpu_pci_config_reset(adev);
707
-
708
-	amdgpu_atombios_scratch_regs_engine_hung(adev, false);
754
+	if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
755
+		dev_info(adev->dev, "BACO reset\n");
756
+		r = amdgpu_dpm_baco_reset(adev);
757
+	} else {
758
+		dev_info(adev->dev, "PCI CONFIG reset\n");
759
+		r = vi_asic_pci_config_reset(adev);
760
+	}
709761 
710762 	return r;
711763 }
....@@ -941,12 +993,92 @@
941993 	}
942994 }
943995 
996
+static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
997
+			      uint64_t *count1)
998
+{
999
+	uint32_t perfctr = 0;
1000
+	uint64_t cnt0_of, cnt1_of;
1001
+	int tmp;
1002
+
1003
+	/* This reports 0 on APUs, so return to avoid writing/reading registers
1004
+	 * that may or may not be different from their GPU counterparts
1005
+	 */
1006
+	if (adev->flags & AMD_IS_APU)
1007
+		return;
1008
+
1009
+	/* Set the 2 events that we wish to watch, defined above */
1010
+	/* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1011
+	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1012
+	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1013
+
1014
+	/* Write to enable desired perf counters */
1015
+	WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1016
+	/* Zero out and enable the perf counters
1017
+	 * Write 0x5:
1018
+	 * Bit 0 = Start all counters(1)
1019
+	 * Bit 2 = Global counter reset enable(1)
1020
+	 */
1021
+	WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1022
+
1023
+	msleep(1000);
1024
+
1025
+	/* Load the shadow and disable the perf counters
1026
+	 * Write 0x2:
1027
+	 * Bit 0 = Stop counters(0)
1028
+	 * Bit 1 = Load the shadow counters(1)
1029
+	 */
1030
+	WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1031
+
1032
+	/* Read register values to get any >32bit overflow */
1033
+	tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1034
+	cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1035
+	cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1036
+
1037
+	/* Get the values and add the overflow */
1038
+	*count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1039
+	*count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1040
+}
1041
+
1042
+static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1043
+{
1044
+	uint64_t nak_r, nak_g;
1045
+
1046
+	/* Get the number of NAKs received and generated */
1047
+	nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1048
+	nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1049
+
1050
+	/* Add the total number of NAKs, i.e the number of replays */
1051
+	return (nak_r + nak_g);
1052
+}
1053
+
1054
+static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1055
+{
1056
+	u32 clock_cntl, pc;
1057
+
1058
+	if (adev->flags & AMD_IS_APU)
1059
+		return false;
1060
+
1061
+	/* check if the SMC is already running */
1062
+	clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1063
+	pc = RREG32_SMC(ixSMC_PC_C);
1064
+	if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1065
+	    (0x20100 <= pc))
1066
+		return true;
1067
+
1068
+	return false;
1069
+}
1070
+
1071
+static void vi_pre_asic_init(struct amdgpu_device *adev)
1072
+{
1073
+}
1074
+
9441075 static const struct amdgpu_asic_funcs vi_asic_funcs =
9451076 {
9461077 	.read_disabled_bios = &vi_read_disabled_bios,
9471078 	.read_bios_from_rom = &vi_read_bios_from_rom,
9481079 	.read_register = &vi_read_register,
9491080 	.reset = &vi_asic_reset,
1081
+	.reset_method = &vi_asic_reset_method,
9501082 	.set_vga_state = &vi_vga_set_state,
9511083 	.get_xclk = &vi_get_xclk,
9521084 	.set_uvd_clocks = &vi_set_uvd_clocks,
....@@ -955,6 +1087,12 @@
9551087 	.flush_hdp = &vi_flush_hdp,
9561088 	.invalidate_hdp = &vi_invalidate_hdp,
9571089 	.need_full_reset = &vi_need_full_reset,
1090
+	.init_doorbell_index = &legacy_doorbell_index_init,
1091
+	.get_pcie_usage = &vi_get_pcie_usage,
1092
+	.need_reset_on_init = &vi_need_reset_on_init,
1093
+	.get_pcie_replay_count = &vi_get_pcie_replay_count,
1094
+	.supports_baco = &vi_asic_supports_baco,
1095
+	.pre_asic_init = &vi_pre_asic_init,
9581096 };
9591097 
9601098 #define CZ_REV_BRISTOL(rev)	 \
....@@ -1376,8 +1514,7 @@
13761514 			       PP_BLOCK_SYS_MC,
13771515 			       pp_support_state,
13781516 			       pp_state);
1379
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1380
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1517
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
13811518 	}
13821519 
13831520 	if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
....@@ -1395,8 +1532,7 @@
13951532 			       PP_BLOCK_SYS_SDMA,
13961533 			       pp_support_state,
13971534 			       pp_state);
1398
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1399
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1535
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14001536 	}
14011537 
14021538 	if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
....@@ -1414,8 +1550,7 @@
14141550 			       PP_BLOCK_SYS_HDP,
14151551 			       pp_support_state,
14161552 			       pp_state);
1417
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1418
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1553
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14191554 	}
14201555 
14211556 
....@@ -1429,8 +1564,7 @@
14291564 			       PP_BLOCK_SYS_BIF,
14301565 			       PP_STATE_SUPPORT_LS,
14311566 			        pp_state);
1432
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1433
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1567
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14341568 	}
14351569 	if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
14361570 		if (state == AMD_CG_STATE_UNGATE)
....@@ -1442,8 +1576,7 @@
14421576 			       PP_BLOCK_SYS_BIF,
14431577 			       PP_STATE_SUPPORT_CG,
14441578 			       pp_state);
1445
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1446
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1579
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14471580 	}
14481581 
14491582 	if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
....@@ -1457,8 +1590,7 @@
14571590 			       PP_BLOCK_SYS_DRM,
14581591 			       PP_STATE_SUPPORT_LS,
14591592 			       pp_state);
1460
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1461
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1593
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14621594 	}
14631595 
14641596 	if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
....@@ -1472,8 +1604,7 @@
14721604 			       PP_BLOCK_SYS_ROM,
14731605 			       PP_STATE_SUPPORT_CG,
14741606 			       pp_state);
1475
-		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1476
-			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1607
+		amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
14771608 	}
14781609 	return 0;
14791610 }
....@@ -1582,30 +1713,31 @@
15821713 	.funcs = &vi_common_ip_funcs,
15831714 };
15841715 
1716
+void vi_set_virt_ops(struct amdgpu_device *adev)
1717
+{
1718
+	adev->virt.ops = &xgpu_vi_virt_ops;
1719
+}
1720
+
15851721 int vi_set_ip_blocks(struct amdgpu_device *adev)
15861722 {
1587
-	/* in early init stage, vbios code won't work */
1588
-	vi_detect_hw_virtualization(adev);
1589
-
1590
-	if (amdgpu_sriov_vf(adev))
1591
-		adev->virt.ops = &xgpu_vi_virt_ops;
1592
-
15931723 	switch (adev->asic_type) {
15941724 	case CHIP_TOPAZ:
15951725 		/* topaz has no DCE, UVD, VCE */
15961726 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
15971727 		amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
15981728 		amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1729
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1730
+		amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
15991731 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16001732 		if (adev->enable_virtual_display)
16011733 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1602
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1603
-		amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
16041734 		break;
16051735 	case CHIP_FIJI:
16061736 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16071737 		amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
16081738 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1739
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1740
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16091741 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16101742 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
16111743 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1615,8 +1747,6 @@
16151747 #endif
16161748 		else
16171749 			amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1618
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1619
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16201750 		if (!amdgpu_sriov_vf(adev)) {
16211751 			amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
16221752 			amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
....@@ -1626,6 +1756,8 @@
16261756 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16271757 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
16281758 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1759
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1760
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16291761 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16301762 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
16311763 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1635,8 +1767,6 @@
16351767 #endif
16361768 		else
16371769 			amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1638
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1639
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16401770 		if (!amdgpu_sriov_vf(adev)) {
16411771 			amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
16421772 			amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
....@@ -1649,6 +1779,8 @@
16491779 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16501780 		amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
16511781 		amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1782
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1783
+		amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
16521784 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16531785 		if (adev->enable_virtual_display)
16541786 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1658,8 +1790,6 @@
16581790 #endif
16591791 		else
16601792 			amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1661
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1662
-		amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
16631793 		amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
16641794 		amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
16651795 		break;
....@@ -1667,6 +1797,8 @@
16671797 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16681798 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
16691799 		amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1800
+		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1801
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16701802 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16711803 		if (adev->enable_virtual_display)
16721804 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1676,8 +1808,6 @@
16761808 #endif
16771809 		else
16781810 			amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1679
-		amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1680
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16811811 		amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
16821812 		amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
16831813 #if defined(CONFIG_DRM_AMD_ACP)
....@@ -1688,6 +1818,8 @@
16881818 		amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
16891819 		amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
16901820 		amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1821
+		amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1822
+		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
16911823 		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
16921824 		if (adev->enable_virtual_display)
16931825 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
....@@ -1697,8 +1829,6 @@
16971829 #endif
16981830 		else
16991831 			amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1700
-		amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1701
-		amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
17021832 		amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
17031833 		amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
17041834 #if defined(CONFIG_DRM_AMD_ACP)
....@@ -1712,3 +1842,21 @@
17121842 
17131843 	return 0;
17141844 }
1845
+
1846
+void legacy_doorbell_index_init(struct amdgpu_device *adev)
1847
+{
1848
+	adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1849
+	adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1850
+	adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1851
+	adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1852
+	adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1853
+	adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1854
+	adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1855
+	adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1856
+	adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1857
+	adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
1858
+	adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1859
+	adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
1860
+	adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1861
+	adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1862
+}