forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
....@@ -25,7 +25,7 @@
2525  */
2626 
2727 #include <linux/firmware.h>
28
-#include <drm/drmP.h>
28
+
2929 #include "amdgpu.h"
3030 #include "amdgpu_vce.h"
3131 #include "soc15.h"
....@@ -244,13 +244,18 @@
244244 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
245245 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
246246 
247
+		offset = AMDGPU_VCE_FIRMWARE_OFFSET;
247248 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
249
+			uint32_t low = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo;
250
+			uint32_t hi = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi;
251
+			uint64_t tmr_mc_addr = (uint64_t)(hi) << 32 | low;
252
+
248253 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
249
-						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
250
-						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
254
+						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), tmr_mc_addr >> 8);
251255 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
252256 						mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
253
-						(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff);
257
+						(tmr_mc_addr >> 40) & 0xff);
258
+			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
254259 		} else {
255260 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
256261 						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
....@@ -258,6 +263,9 @@
258263 			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
259264 						mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
260265 						(adev->vce.gpu_addr >> 40) & 0xff);
266
+			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
267
+						offset & ~0x0f000000);
268
+
261269 		}
262270 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,
263271 						mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
....@@ -272,10 +280,7 @@
272280 						mmVCE_LMI_VCPU_CACHE_64BIT_BAR2),
273281 						(adev->vce.gpu_addr >> 40) & 0xff);
274282 
275
-		offset = AMDGPU_VCE_FIRMWARE_OFFSET;
276283 		size = VCE_V4_0_FW_SIZE;
277
-		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
278
-					offset & ~0x0f000000);
279284 		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
280285 
281286 		offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0;
....@@ -382,6 +387,7 @@
382387 static int vce_v4_0_stop(struct amdgpu_device *adev)
383388 {
384389 
390
+	/* Disable VCPU */
385391 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);
386392 
387393 	/* hold on ECPU */
....@@ -389,8 +395,8 @@
389395 			VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
390396 			~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
391397 
392
-	/* clear BUSY flag */
393
-	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);
398
+	/* clear VCE_STATUS */
399
+	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0);
394400 
395401 	/* Set Clock-Gating off */
396402 	/* if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
....@@ -466,11 +472,12 @@
466472 			 * so set unused location for other unused rings.
467473 			 */
468474 			if (i == 0)
469
-				ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING0_1 * 2;
475
+				ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring0_1 * 2;
470476 			else
471
-				ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1;
477
+				ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring2_3 * 2 + 1;
472478 		}
473
-		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
479
+		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
480
+				     AMDGPU_RING_PRIO_DEFAULT);
474481 		if (r)
475482 			return r;
476483 	}
....@@ -519,15 +526,10 @@
519526 	if (r)
520527 		return r;
521528 
522
-	for (i = 0; i < adev->vce.num_rings; i++)
523
-		adev->vce.ring[i].ready = false;
524
-
525529 	for (i = 0; i < adev->vce.num_rings; i++) {
526
-		r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
530
+		r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
527531 		if (r)
528532 			return r;
529
-		else
530
-			adev->vce.ring[i].ready = true;
531533 	}
532534 
533535 	DRM_INFO("VCE initialized successfully.\n");
....@@ -538,7 +540,6 @@
538540 static int vce_v4_0_hw_fini(void *handle)
539541 {
540542 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
541
-	int i;
542543 
543544 	if (!amdgpu_sriov_vf(adev)) {
544545 		/* vce_v4_0_wait_for_idle(handle); */
....@@ -547,9 +548,6 @@
547548 		/* full access mode, so don't touch any VCE register */
548549 		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
549550 	}
550
-
551
-	for (i = 0; i < adev->vce.num_rings; i++)
552
-		adev->vce.ring[i].ready = false;
553551 
554552 	return 0;
555553 }
....@@ -601,6 +599,7 @@
601599 static void vce_v4_0_mc_resume(struct amdgpu_device *adev)
602600 {
603601 	uint32_t offset, size;
602
+	uint64_t tmr_mc_addr;
604603 
605604 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16));
606605 	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);
....@@ -613,21 +612,25 @@
613612 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
614613 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
615614 
615
+	offset = AMDGPU_VCE_FIRMWARE_OFFSET;
616
+
616617 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
618
+		tmr_mc_addr = (uint64_t)(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi) << 32 |
619
+										adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo;
617620 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
618
-			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8));
621
+			(tmr_mc_addr >> 8));
619622 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
620
-			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff);
623
+			(tmr_mc_addr >> 40) & 0xff);
624
+		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
621625 	} else {
622626 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
623627 			(adev->vce.gpu_addr >> 8));
624628 		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),
625629 			(adev->vce.gpu_addr >> 40) & 0xff);
630
+		WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);
626631 	}
627632 
628
-	offset = AMDGPU_VCE_FIRMWARE_OFFSET;
629633 	size = VCE_V4_0_FW_SIZE;
630
-	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);
631634 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);
632635 
633636 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));
....@@ -881,7 +884,7 @@
881884 					  enum amd_clockgating_state state)
882885 {
883886 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
884
-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
887
+	bool enable = (state == AMD_CG_STATE_GATE);
885888 	int i;
886889 
887890 	if ((adev->asic_type == CHIP_POLARIS10) ||
....@@ -922,6 +925,7 @@
922925 
923926 	return 0;
924927 }
928
+#endif
925929 
926930 static int vce_v4_0_set_powergating_state(void *handle,
927931 					  enum amd_powergating_state state)
....@@ -935,20 +939,17 @@
935939 	 */
936940 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
937941 
938
-	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
939
-		return 0;
940
-
941942 	if (state == AMD_PG_STATE_GATE)
942
-		/* XXX do we need a vce_v4_0_stop()? */
943
-		return 0;
943
+		return vce_v4_0_stop(adev);
944944 	else
945945 		return vce_v4_0_start(adev);
946946 }
947
-#endif
948947 
949
-static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
950
-		struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
948
+static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
949
+					struct amdgpu_ib *ib, uint32_t flags)
951950 {
951
+	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
952
+
952953 	amdgpu_ring_write(ring, VCE_CMD_IB_VM);
953954 	amdgpu_ring_write(ring, vmid);
954955 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
....@@ -990,7 +991,8 @@
990991 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
991992 
992993 	/* wait for reg writes */
993
-	vce_v4_0_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
994
+	vce_v4_0_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
995
+			       vmid * hub->ctx_addr_distance,
994996 			       lower_32_bits(pd_addr), 0xffffffff);
995997 }
996998 
....@@ -1057,7 +1059,7 @@
10571059 	.soft_reset = NULL /* vce_v4_0_soft_reset */,
10581060 	.post_soft_reset = NULL /* vce_v4_0_post_soft_reset */,
10591061 	.set_clockgating_state = vce_v4_0_set_clockgating_state,
1060
-	.set_powergating_state = NULL /* vce_v4_0_set_powergating_state */,
1062
+	.set_powergating_state = vce_v4_0_set_powergating_state,
10611063 };
10621064 
10631065 static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
....@@ -1065,7 +1067,8 @@
10651067 	.align_mask = 0x3f,
10661068 	.nop = VCE_CMD_NO_OP,
10671069 	.support_64bit_ptrs = false,
1068
-	.vmhub = AMDGPU_MMHUB,
1070
+	.no_user_fence = true,
1071
+	.vmhub = AMDGPU_MMHUB_0,
10691072 	.get_rptr = vce_v4_0_ring_get_rptr,
10701073 	.get_wptr = vce_v4_0_ring_get_wptr,
10711074 	.set_wptr = vce_v4_0_ring_set_wptr,