add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
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@@ -26,7 +26,7 @@
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  */
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 #include <linux/firmware.h>
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-#include <drm/drmP.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_vce.h"
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 #include "cikd.h"
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@@ -283,7 +283,7 @@
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 	}
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 	if (vce_v2_0_wait_for_idle(adev)) {
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-		DRM_INFO("VCE is busy, Can't set clock gateing");
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+		DRM_INFO("VCE is busy, Can't set clock gating");
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 		return 0;
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 	}
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@@ -417,7 +417,7 @@
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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 	/* VCE */
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-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
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+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);
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 	if (r)
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 		return r;
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@@ -434,7 +434,8 @@
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 		ring = &adev->vce.ring[i];
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 		sprintf(ring->name, "vce%d", i);
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 		r = amdgpu_ring_init(adev, ring, 512,
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-				     &adev->vce.irq, 0);
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+				     &adev->vce.irq, 0,
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+				     AMDGPU_RING_PRIO_DEFAULT);
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 		if (r)
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 			return r;
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 	}
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@@ -463,15 +464,11 @@
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 	amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
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 	vce_v2_0_enable_mgcg(adev, true, false);
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-	for (i = 0; i < adev->vce.num_rings; i++)
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-		adev->vce.ring[i].ready = false;
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 	for (i = 0; i < adev->vce.num_rings; i++) {
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-		r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
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+		r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
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 		if (r)
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 			return r;
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-		else
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-			adev->vce.ring[i].ready = true;
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 	}
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 	DRM_INFO("VCE initialized successfully.\n");
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@@ -609,6 +606,7 @@
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 	.align_mask = 0xf,
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 	.nop = VCE_CMD_NO_OP,
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 	.support_64bit_ptrs = false,
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+	.no_user_fence = true,
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 	.get_rptr = vce_v2_0_ring_get_rptr,
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 	.get_wptr = vce_v2_0_ring_get_wptr,
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 	.set_wptr = vce_v2_0_ring_set_wptr,