forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
....@@ -23,7 +23,7 @@
2323  */
2424 
2525 #include <linux/firmware.h>
26
-#include <drm/drmP.h>
26
+
2727 #include "amdgpu.h"
2828 #include "amdgpu_uvd.h"
2929 #include "vid.h"
....@@ -175,11 +175,8 @@
175175 	int r;
176176 
177177 	r = amdgpu_ring_alloc(ring, 16);
178
-	if (r) {
179
-		DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
180
-			  ring->idx, r);
178
+	if (r)
181179 		return r;
182
-	}
183180 
184181 	rptr = amdgpu_ring_get_rptr(ring);
185182 
....@@ -189,17 +186,11 @@
189186 	for (i = 0; i < adev->usec_timeout; i++) {
190187 		if (amdgpu_ring_get_rptr(ring) != rptr)
191188 			break;
192
-		DRM_UDELAY(1);
189
+		udelay(1);
193190 	}
194191 
195
-	if (i < adev->usec_timeout) {
196
-		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
197
-			 ring->idx, i);
198
-	} else {
199
-		DRM_ERROR("amdgpu: ring %d test failed\n",
200
-			  ring->idx);
192
+	if (i >= adev->usec_timeout)
201193 		r = -ETIMEDOUT;
202
-	}
203194 
204195 	return r;
205196 }
....@@ -215,29 +206,31 @@
215206  * Open up a stream for HW test
216207  */
217208 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
209
+				       struct amdgpu_bo *bo,
218210 				       struct dma_fence **fence)
219211 {
220212 	const unsigned ib_size_dw = 16;
221213 	struct amdgpu_job *job;
222214 	struct amdgpu_ib *ib;
223215 	struct dma_fence *f = NULL;
224
-	uint64_t dummy;
216
+	uint64_t addr;
225217 	int i, r;
226218 
227
-	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
219
+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
220
+					AMDGPU_IB_POOL_DIRECT, &job);
228221 	if (r)
229222 		return r;
230223 
231224 	ib = &job->ibs[0];
232
-	dummy = ib->gpu_addr + 1024;
225
+	addr = amdgpu_bo_gpu_offset(bo);
233226 
234227 	ib->length_dw = 0;
235228 	ib->ptr[ib->length_dw++] = 0x00000018;
236229 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
237230 	ib->ptr[ib->length_dw++] = handle;
238231 	ib->ptr[ib->length_dw++] = 0x00010000;
239
-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
240
-	ib->ptr[ib->length_dw++] = dummy;
232
+	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
233
+	ib->ptr[ib->length_dw++] = addr;
241234 
242235 	ib->ptr[ib->length_dw++] = 0x00000014;
243236 	ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
....@@ -277,29 +270,31 @@
277270  */
278271 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
279272 					uint32_t handle,
280
-					bool direct, struct dma_fence **fence)
273
+					struct amdgpu_bo *bo,
274
+					struct dma_fence **fence)
281275 {
282276 	const unsigned ib_size_dw = 16;
283277 	struct amdgpu_job *job;
284278 	struct amdgpu_ib *ib;
285279 	struct dma_fence *f = NULL;
286
-	uint64_t dummy;
280
+	uint64_t addr;
287281 	int i, r;
288282 
289
-	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
283
+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
284
+					AMDGPU_IB_POOL_DIRECT, &job);
290285 	if (r)
291286 		return r;
292287 
293288 	ib = &job->ibs[0];
294
-	dummy = ib->gpu_addr + 1024;
289
+	addr = amdgpu_bo_gpu_offset(bo);
295290 
296291 	ib->length_dw = 0;
297292 	ib->ptr[ib->length_dw++] = 0x00000018;
298293 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
299294 	ib->ptr[ib->length_dw++] = handle;
300295 	ib->ptr[ib->length_dw++] = 0x00010000;
301
-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
302
-	ib->ptr[ib->length_dw++] = dummy;
296
+	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
297
+	ib->ptr[ib->length_dw++] = addr;
303298 
304299 	ib->ptr[ib->length_dw++] = 0x00000014;
305300 	ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
....@@ -313,11 +308,7 @@
313308 	for (i = ib->length_dw; i < ib_size_dw; ++i)
314309 		ib->ptr[i] = 0x0;
315310 
316
-	if (direct)
317
-		r = amdgpu_job_submit_direct(job, ring, &f);
318
-	else
319
-		r = amdgpu_job_submit(job, &ring->adev->vce.entity,
320
-				      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
311
+	r = amdgpu_job_submit_direct(job, ring, &f);
321312 	if (r)
322313 		goto err;
323314 
....@@ -340,34 +331,37 @@
340331 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
341332 {
342333 	struct dma_fence *fence = NULL;
334
+	struct amdgpu_bo *bo = NULL;
343335 	long r;
344336 
345
-	r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
346
-	if (r) {
347
-		DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
348
-		goto error;
349
-	}
337
+	r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
338
+				      AMDGPU_GEM_DOMAIN_VRAM,
339
+				      &bo, NULL, NULL);
340
+	if (r)
341
+		return r;
350342 
351
-	r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
352
-	if (r) {
353
-		DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
343
+	r = uvd_v6_0_enc_get_create_msg(ring, 1, bo, NULL);
344
+	if (r)
354345 		goto error;
355
-	}
346
+
347
+	r = uvd_v6_0_enc_get_destroy_msg(ring, 1, bo, &fence);
348
+	if (r)
349
+		goto error;
356350 
357351 	r = dma_fence_wait_timeout(fence, false, timeout);
358
-	if (r == 0) {
359
-		DRM_ERROR("amdgpu: IB test timed out.\n");
352
+	if (r == 0)
360353 		r = -ETIMEDOUT;
361
-	} else if (r < 0) {
362
-		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
363
-	} else {
364
-		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
354
+	else if (r > 0)
365355 		r = 0;
366
-	}
356
+
367357 error:
368358 	dma_fence_put(fence);
359
+	amdgpu_bo_unpin(bo);
360
+	amdgpu_bo_unreserve(bo);
361
+	amdgpu_bo_unref(&bo);
369362 	return r;
370363 }
364
+
371365 static int uvd_v6_0_early_init(void *handle)
372366 {
373367 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
....@@ -396,14 +390,14 @@
396390 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
397391 
398392 	/* UVD TRAP */
399
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
393
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
400394 	if (r)
401395 		return r;
402396 
403397 	/* UVD ENC TRAP */
404398 	if (uvd_v6_0_enc_support(adev)) {
405399 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
406
-			r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
400
+			r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
407401 			if (r)
408402 				return r;
409403 		}
....@@ -425,7 +419,8 @@
425419 
426420 	ring = &adev->uvd.inst->ring;
427421 	sprintf(ring->name, "uvd");
428
-	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
422
+	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
423
+			     AMDGPU_RING_PRIO_DEFAULT);
429424 	if (r)
430425 		return r;
431426 
....@@ -437,7 +432,9 @@
437432 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
438433 			ring = &adev->uvd.inst->ring_enc[i];
439434 			sprintf(ring->name, "uvd_enc%d", i);
440
-			r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
435
+			r = amdgpu_ring_init(adev, ring, 512,
436
+					     &adev->uvd.inst->irq, 0,
437
+					     AMDGPU_RING_PRIO_DEFAULT);
441438 			if (r)
442439 				return r;
443440 		}
....@@ -483,12 +480,9 @@
483480 	uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
484481 	uvd_v6_0_enable_mgcg(adev, true);
485482 
486
-	ring->ready = true;
487
-	r = amdgpu_ring_test_ring(ring);
488
-	if (r) {
489
-		ring->ready = false;
483
+	r = amdgpu_ring_test_helper(ring);
484
+	if (r)
490485 		goto done;
491
-	}
492486 
493487 	r = amdgpu_ring_alloc(ring, 10);
494488 	if (r) {
....@@ -520,12 +514,9 @@
520514 	if (uvd_v6_0_enc_support(adev)) {
521515 		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
522516 			ring = &adev->uvd.inst->ring_enc[i];
523
-			ring->ready = true;
524
-			r = amdgpu_ring_test_ring(ring);
525
-			if (r) {
526
-				ring->ready = false;
517
+			r = amdgpu_ring_test_helper(ring);
518
+			if (r)
527519 				goto done;
528
-			}
529520 		}
530521 	}
531522 
....@@ -550,12 +541,9 @@
550541 static int uvd_v6_0_hw_fini(void *handle)
551542 {
552543 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
553
-	struct amdgpu_ring *ring = &adev->uvd.inst->ring;
554544 
555545 	if (RREG32(mmUVD_STATUS) != 0)
556546 		uvd_v6_0_stop(adev);
557
-
558
-	ring->ready = false;
559547 
560548 	return 0;
561549 }
....@@ -596,7 +584,7 @@
596584 	uint64_t offset;
597585 	uint32_t size;
598586 
599
-	/* programm memory controller bits 0-27 */
587
+	/* program memory controller bits 0-27 */
600588 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
601589 			lower_32_bits(adev->uvd.inst->gpu_addr));
602590 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
....@@ -838,7 +826,7 @@
838826 	/* set the wb address */
839827 	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
840828 
841
-	/* programm the RB_BASE for ring buffer */
829
+	/* program the RB_BASE for ring buffer */
842830 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
843831 			lower_32_bits(ring->gpu_addr));
844832 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
....@@ -976,11 +964,9 @@
976964 
977965 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
978966 	r = amdgpu_ring_alloc(ring, 3);
979
-	if (r) {
980
-		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
981
-			  ring->idx, r);
967
+	if (r)
982968 		return r;
983
-	}
969
+
984970 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
985971 	amdgpu_ring_write(ring, 0xDEADBEEF);
986972 	amdgpu_ring_commit(ring);
....@@ -988,17 +974,12 @@
988974 		tmp = RREG32(mmUVD_CONTEXT_ID);
989975 		if (tmp == 0xDEADBEEF)
990976 			break;
991
-		DRM_UDELAY(1);
977
+		udelay(1);
992978 	}
993979 
994
-	if (i < adev->usec_timeout) {
995
-		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
996
-			 ring->idx, i);
997
-	} else {
998
-		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
999
-			  ring->idx, tmp);
1000
-		r = -EINVAL;
1001
-	}
980
+	if (i >= adev->usec_timeout)
981
+		r = -ETIMEDOUT;
982
+
1002983 	return r;
1003984 }
1004985 
....@@ -1011,9 +992,12 @@
1011992  * Write ring commands to execute the indirect buffer
1012993  */
1013994 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
995
+				  struct amdgpu_job *job,
1014996 				  struct amdgpu_ib *ib,
1015
-				  unsigned vmid, bool ctx_switch)
997
+				  uint32_t flags)
1016998 {
999
+	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1000
+
10171001 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
10181002 	amdgpu_ring_write(ring, vmid);
10191003 
....@@ -1034,8 +1018,12 @@
10341018  * Write enc ring commands to execute the indirect buffer
10351019  */
10361020 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1037
-		struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1021
+					struct amdgpu_job *job,
1022
+					struct amdgpu_ib *ib,
1023
+					uint32_t flags)
10381024 {
1025
+	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1026
+
10391027 	amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
10401028 	amdgpu_ring_write(ring, vmid);
10411029 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
....@@ -1253,8 +1241,8 @@
12531241 		break;
12541242 	}
12551243 
1256
-	if (false == int_handled)
1257
-			DRM_ERROR("Unhandled interrupt: %d %d\n",
1244
+	if (!int_handled)
1245
+		DRM_ERROR("Unhandled interrupt: %d %d\n",
12581246 			  entry->src_id, entry->src_data[0]);
12591247 
12601248 	return 0;
....@@ -1436,7 +1424,7 @@
14361424 					  enum amd_clockgating_state state)
14371425 {
14381426 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1439
-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1427
+	bool enable = (state == AMD_CG_STATE_GATE);
14401428 
14411429 	if (enable) {
14421430 		/* wait for STATUS to clear */
....@@ -1531,6 +1519,7 @@
15311519 	.type = AMDGPU_RING_TYPE_UVD,
15321520 	.align_mask = 0xf,
15331521 	.support_64bit_ptrs = false,
1522
+	.no_user_fence = true,
15341523 	.get_rptr = uvd_v6_0_ring_get_rptr,
15351524 	.get_wptr = uvd_v6_0_ring_get_wptr,
15361525 	.set_wptr = uvd_v6_0_ring_set_wptr,
....@@ -1556,6 +1545,7 @@
15561545 	.type = AMDGPU_RING_TYPE_UVD,
15571546 	.align_mask = 0xf,
15581547 	.support_64bit_ptrs = false,
1548
+	.no_user_fence = true,
15591549 	.get_rptr = uvd_v6_0_ring_get_rptr,
15601550 	.get_wptr = uvd_v6_0_ring_get_wptr,
15611551 	.set_wptr = uvd_v6_0_ring_set_wptr,
....@@ -1584,6 +1574,7 @@
15841574 	.align_mask = 0x3f,
15851575 	.nop = HEVC_ENC_CMD_NO_OP,
15861576 	.support_64bit_ptrs = false,
1577
+	.no_user_fence = true,
15871578 	.get_rptr = uvd_v6_0_enc_ring_get_rptr,
15881579 	.get_wptr = uvd_v6_0_enc_ring_get_wptr,
15891580 	.set_wptr = uvd_v6_0_enc_ring_set_wptr,