add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
..
..
@@ -22,8 +22,9 @@
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  * Authors: Christian König <christian.koenig@amd.com>
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  */
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+#include <linux/delay.h>
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 #include <linux/firmware.h>
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-#include <drm/drmP.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_uvd.h"
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 #include "vid.h"
..
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@@ -105,7 +106,7 @@
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 	int r;
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 	/* UVD TRAP */
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-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
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+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
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 	if (r)
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 		return r;
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..
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@@ -115,7 +116,8 @@
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 	ring = &adev->uvd.inst->ring;
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 	sprintf(ring->name, "uvd");
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-	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
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+	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
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+			     AMDGPU_RING_PRIO_DEFAULT);
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 	if (r)
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 		return r;
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..
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@@ -158,12 +160,9 @@
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 	uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
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 	uvd_v5_0_enable_mgcg(adev, true);
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-	ring->ready = true;
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-	r = amdgpu_ring_test_ring(ring);
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-	if (r) {
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-		ring->ready = false;
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+	r = amdgpu_ring_test_helper(ring);
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+	if (r)
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 		goto done;
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-	}
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 	r = amdgpu_ring_alloc(ring, 10);
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 	if (r) {
..
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@@ -210,12 +209,9 @@
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 static int uvd_v5_0_hw_fini(void *handle)
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 {
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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-	struct amdgpu_ring *ring = &adev->uvd.inst->ring;
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212
 
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 	if (RREG32(mmUVD_STATUS) != 0)
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 		uvd_v5_0_stop(adev);
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-
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-	ring->ready = false;
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215
 
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 	return 0;
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 }
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@@ -257,7 +253,7 @@
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 	uint64_t offset;
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 	uint32_t size;
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-	/* programm memory controller bits 0-27 */
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+	/* program memory controller bits 0-27 */
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 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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 			lower_32_bits(adev->uvd.inst->gpu_addr));
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 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
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@@ -408,7 +404,7 @@
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 	/* set the wb address */
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 	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
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406
 
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-	/* programm the RB_BASE for ring buffer */
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+	/* program the RB_BASE for ring buffer */
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 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
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 			lower_32_bits(ring->gpu_addr));
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 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
..
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@@ -500,11 +496,8 @@
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 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
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 	r = amdgpu_ring_alloc(ring, 3);
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-	if (r) {
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-		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
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-			  ring->idx, r);
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+	if (r)
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 		return r;
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-	}
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 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
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 	amdgpu_ring_write(ring, 0xDEADBEEF);
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 	amdgpu_ring_commit(ring);
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@@ -512,17 +505,12 @@
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 		tmp = RREG32(mmUVD_CONTEXT_ID);
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 		if (tmp == 0xDEADBEEF)
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 			break;
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-		DRM_UDELAY(1);
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+		udelay(1);
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509
 	}
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510
 
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-	if (i < adev->usec_timeout) {
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-		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
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-			 ring->idx, i);
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-	} else {
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-		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
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-			  ring->idx, tmp);
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-		r = -EINVAL;
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-	}
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+	if (i >= adev->usec_timeout)
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+		r = -ETIMEDOUT;
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+
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 	return r;
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 }
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..
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@@ -535,8 +523,9 @@
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  * Write ring commands to execute the indirect buffer
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  */
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 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
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+				  struct amdgpu_job *job,
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 				  struct amdgpu_ib *ib,
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-				  unsigned vmid, bool ctx_switch)
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+				  uint32_t flags)
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 {
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 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
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 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
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@@ -772,7 +761,7 @@
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 					  enum amd_clockgating_state state)
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 {
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
764
+	bool enable = (state == AMD_CG_STATE_GATE);
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765
 
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 	if (enable) {
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 		/* wait for STATUS to clear */
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@@ -859,6 +848,7 @@
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 	.type = AMDGPU_RING_TYPE_UVD,
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 	.align_mask = 0xf,
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 	.support_64bit_ptrs = false,
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+	.no_user_fence = true,
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 	.get_rptr = uvd_v5_0_ring_get_rptr,
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 	.get_wptr = uvd_v5_0_ring_get_wptr,
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 	.set_wptr = uvd_v5_0_ring_set_wptr,