add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
..
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@@ -23,7 +23,7 @@
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  */
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 #include <linux/firmware.h>
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-#include <drm/drmP.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_uvd.h"
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 #include "cikd.h"
..
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@@ -108,7 +108,7 @@
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 	int r;
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 	/* UVD TRAP */
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-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
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+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
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 	if (r)
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 		return r;
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..
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@@ -118,7 +118,8 @@
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 	ring = &adev->uvd.inst->ring;
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 	sprintf(ring->name, "uvd");
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-	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
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+	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
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+			     AMDGPU_RING_PRIO_DEFAULT);
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 	if (r)
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 		return r;
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..
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@@ -162,12 +163,9 @@
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 	uvd_v4_2_enable_mgcg(adev, true);
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 	amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
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-	ring->ready = true;
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-	r = amdgpu_ring_test_ring(ring);
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-	if (r) {
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-		ring->ready = false;
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+	r = amdgpu_ring_test_helper(ring);
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+	if (r)
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 		goto done;
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-	}
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169
 
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 	r = amdgpu_ring_alloc(ring, 10);
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 	if (r) {
..
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@@ -213,12 +211,9 @@
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 static int uvd_v4_2_hw_fini(void *handle)
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 {
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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-	struct amdgpu_ring *ring = &adev->uvd.inst->ring;
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214
 
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 	if (RREG32(mmUVD_STATUS) != 0)
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 		uvd_v4_2_stop(adev);
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-
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-	ring->ready = false;
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 	return 0;
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 }
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@@ -353,7 +348,7 @@
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 	/* Set the write pointer delay */
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 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
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350
 
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-	/* programm the 4GB memory segment for rptr and ring buffer */
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+	/* program the 4GB memory segment for rptr and ring buffer */
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 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
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 				   (0x7 << 16) | (0x1 << 31));
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354
 
..
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@@ -484,11 +479,9 @@
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 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
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 	r = amdgpu_ring_alloc(ring, 3);
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-	if (r) {
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-		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
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-			  ring->idx, r);
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+	if (r)
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 		return r;
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-	}
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+
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 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
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 	amdgpu_ring_write(ring, 0xDEADBEEF);
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 	amdgpu_ring_commit(ring);
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@@ -496,17 +489,12 @@
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 		tmp = RREG32(mmUVD_CONTEXT_ID);
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 		if (tmp == 0xDEADBEEF)
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 			break;
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-		DRM_UDELAY(1);
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+		udelay(1);
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493
 	}
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494
 
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-	if (i < adev->usec_timeout) {
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-		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
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-			 ring->idx, i);
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-	} else {
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-		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
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-			  ring->idx, tmp);
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-		r = -EINVAL;
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-	}
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+	if (i >= adev->usec_timeout)
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+		r = -ETIMEDOUT;
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+
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 	return r;
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 }
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..
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@@ -519,8 +507,9 @@
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  * Write ring commands to execute the indirect buffer
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  */
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 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
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+				  struct amdgpu_job *job,
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 				  struct amdgpu_ib *ib,
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-				  unsigned vmid, bool ctx_switch)
512
+				  uint32_t flags)
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 {
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 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
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 	amdgpu_ring_write(ring, ib->gpu_addr);
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@@ -552,7 +541,7 @@
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541
 	uint64_t addr;
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 	uint32_t size;
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543
 
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-	/* programm the VCPU memory controller bits 0-27 */
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+	/* program the VCPU memory controller bits 0-27 */
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 	addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
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 	size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
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 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
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@@ -750,6 +739,7 @@
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 	.type = AMDGPU_RING_TYPE_UVD,
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 	.align_mask = 0xf,
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741
 	.support_64bit_ptrs = false,
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+	.no_user_fence = true,
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 	.get_rptr = uvd_v4_2_ring_get_rptr,
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 	.get_wptr = uvd_v4_2_ring_get_wptr,
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 	.set_wptr = uvd_v4_2_ring_set_wptr,