add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
..
..
@@ -20,7 +20,9 @@
20
20
  * OTHER DEALINGS IN THE SOFTWARE.
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21
  *
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22
  */
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-#include <drm/drmP.h>
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+
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+#include <linux/pci.h>
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+
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26
 #include "amdgpu.h"
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27
 #include "amdgpu_ih.h"
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28
 #include "vid.h"
..
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@@ -99,9 +101,9 @@
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  */
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 static int tonga_ih_irq_init(struct amdgpu_device *adev)
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103
 {
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-	int rb_bufsz;
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104
 	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
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-	u64 wptr_off;
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+	struct amdgpu_ih_ring *ih = &adev->irq.ih;
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+	int rb_bufsz;
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107
 
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 	/* disable irqs */
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 	tonga_ih_disable_interrupts(adev);
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..
@@ -118,10 +120,7 @@
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 	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
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121
 
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 	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
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-	if (adev->irq.ih.use_bus_addr)
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-		WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
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-	else
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-		WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
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+	WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
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124
 
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 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
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 	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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@@ -136,12 +135,8 @@
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 	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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136
 
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 	/* set the writeback address whether it's enabled or not */
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-	if (adev->irq.ih.use_bus_addr)
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-		wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
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-	else
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-		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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-	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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-	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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+	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
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+	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
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140
 
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 	/* set rptr, wptr to 0 */
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 	WREG32(mmIH_RB_RPTR, 0);
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@@ -193,57 +188,38 @@
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  * Used by cz_irq_process(VI).
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  * Returns the value of the wptr.
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  */
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-static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
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+static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
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+			     struct amdgpu_ih_ring *ih)
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 {
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 	u32 wptr, tmp;
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195
 
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-	if (adev->irq.ih.use_bus_addr)
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-		wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
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-	else
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-		wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
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+	wptr = le32_to_cpu(*ih->wptr_cpu);
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197
 
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-	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
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-		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
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-		/* When a ring buffer overflow happen start parsing interrupt
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-		 * from the last not overwritten vector (wptr + 16). Hopefully
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-		 * this should allow us to catchup.
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-		 */
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-		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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-			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
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-		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
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-		tmp = RREG32(mmIH_RB_CNTL);
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-		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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-		WREG32(mmIH_RB_CNTL, tmp);
217
-	}
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-	return (wptr & adev->irq.ih.ptr_mask);
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-}
198
+	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
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+		goto out;
220
200
 
221
-/**
222
- * tonga_ih_prescreen_iv - prescreen an interrupt vector
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- *
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- * @adev: amdgpu_device pointer
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- *
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- * Returns true if the interrupt vector should be further processed.
227
- */
228
-static bool tonga_ih_prescreen_iv(struct amdgpu_device *adev)
229
-{
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-	u32 ring_index = adev->irq.ih.rptr >> 2;
231
-	u16 pasid;
201
+	/* Double check that the overflow wasn't already cleared. */
202
+	wptr = RREG32(mmIH_RB_WPTR);
232
203
 
233
-	switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
234
-	case 146:
235
-	case 147:
236
-		pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
237
-		if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
238
-			return true;
239
-		break;
240
-	default:
241
-		/* Not a VM fault */
242
-		return true;
243
-	}
204
+	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
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+		goto out;
244
206
 
245
-	adev->irq.ih.rptr += 16;
246
-	return false;
207
+	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
208
+
209
+	/* When a ring buffer overflow happen start parsing interrupt
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+	 * from the last not overwritten vector (wptr + 16). Hopefully
211
+	 * this should allow us to catchup.
212
+	 */
213
+
214
+	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
215
+		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
216
+	ih->rptr = (wptr + 16) & ih->ptr_mask;
217
+	tmp = RREG32(mmIH_RB_CNTL);
218
+	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
219
+	WREG32(mmIH_RB_CNTL, tmp);
220
+
221
+out:
222
+	return (wptr & ih->ptr_mask);
247
223
 }
248
224
 
249
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 /**
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@@ -255,18 +231,19 @@
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231
  * position and also advance the position.
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232
  */
257
233
 static void tonga_ih_decode_iv(struct amdgpu_device *adev,
258
-				 struct amdgpu_iv_entry *entry)
234
+			       struct amdgpu_ih_ring *ih,
235
+			       struct amdgpu_iv_entry *entry)
259
236
 {
260
237
 	/* wptr/rptr are in bytes! */
261
-	u32 ring_index = adev->irq.ih.rptr >> 2;
238
+	u32 ring_index = ih->rptr >> 2;
262
239
 	uint32_t dw[4];
263
240
 
264
-	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
265
-	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
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-	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
267
-	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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+	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
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+	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
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+	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
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+	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
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245
 
269
-	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
246
+	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
270
247
 	entry->src_id = dw[0] & 0xff;
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248
 	entry->src_data[0] = dw[1] & 0xfffffff;
272
249
 	entry->ring_id = dw[2] & 0xff;
..
..
@@ -274,7 +251,7 @@
274
251
 	entry->pasid = (dw[2] >> 16) & 0xffff;
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252
 
276
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 	/* wptr/rptr are in bytes! */
277
-	adev->irq.ih.rptr += 16;
254
+	ih->rptr += 16;
278
255
 }
279
256
 
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 /**
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@@ -284,17 +261,15 @@
284
261
  *
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262
  * Set the IH ring buffer rptr.
286
263
  */
287
-static void tonga_ih_set_rptr(struct amdgpu_device *adev)
264
+static void tonga_ih_set_rptr(struct amdgpu_device *adev,
265
+			      struct amdgpu_ih_ring *ih)
288
266
 {
289
-	if (adev->irq.ih.use_doorbell) {
267
+	if (ih->use_doorbell) {
290
268
 		/* XXX check if swapping is necessary on BE */
291
-		if (adev->irq.ih.use_bus_addr)
292
-			adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
293
-		else
294
-			adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
295
-		WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
269
+		*ih->rptr_cpu = ih->rptr;
270
+		WDOORBELL32(ih->doorbell_index, ih->rptr);
296
271
 	} else {
297
-		WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
272
+		WREG32(mmIH_RB_RPTR, ih->rptr);
298
273
 	}
299
274
 }
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275
 
..
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@@ -317,12 +292,12 @@
317
292
 	int r;
318
293
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
319
294
 
320
-	r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
295
+	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
321
296
 	if (r)
322
297
 		return r;
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298
 
324
299
 	adev->irq.ih.use_doorbell = true;
325
-	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;
300
+	adev->irq.ih.doorbell_index = adev->doorbell_index.ih;
326
301
 
327
302
 	r = amdgpu_irq_init(adev);
328
303
 
..
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@@ -334,7 +309,7 @@
334
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
335
310
 
336
311
 	amdgpu_irq_fini(adev);
337
-	amdgpu_ih_ring_fini(adev);
312
+	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
338
313
 	amdgpu_irq_remove_domain(adev);
339
314
 
340
315
 	return 0;
..
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@@ -506,15 +481,13 @@
506
481
 
507
482
 static const struct amdgpu_ih_funcs tonga_ih_funcs = {
508
483
 	.get_wptr = tonga_ih_get_wptr,
509
-	.prescreen_iv = tonga_ih_prescreen_iv,
510
484
 	.decode_iv = tonga_ih_decode_iv,
511
485
 	.set_rptr = tonga_ih_set_rptr
512
486
 };
513
487
 
514
488
 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
515
489
 {
516
-	if (adev->irq.ih_funcs == NULL)
517
-		adev->irq.ih_funcs = &tonga_ih_funcs;
490
+	adev->irq.ih_funcs = &tonga_ih_funcs;
518
491
 }
519
492
 
520
493
 const struct amdgpu_ip_block_version tonga_ih_ip_block =