add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/si_ih.c
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@@ -20,11 +20,15 @@
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  * OTHER DEALINGS IN THE SOFTWARE.
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  *
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  */
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-#include <drm/drmP.h>
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+
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+#include <linux/pci.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_ih.h"
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 #include "sid.h"
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 #include "si_ih.h"
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+#include "oss/oss_1_0_d.h"
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+#include "oss/oss_1_0_sh_mask.h"
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32
 
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 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
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@@ -57,9 +61,9 @@
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61
 
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 static int si_ih_irq_init(struct amdgpu_device *adev)
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 {
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+	struct amdgpu_ih_ring *ih = &adev->irq.ih;
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 	int rb_bufsz;
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 	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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-	u64 wptr_off;
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 	si_ih_disable_interrupts(adev);
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 	/* set dummy read address to dummy page address */
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@@ -77,9 +81,8 @@
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 		     (rb_bufsz << 1) |
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 		     IH_WPTR_WRITEBACK_ENABLE;
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-	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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-	WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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-	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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+	WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
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+	WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
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 	WREG32(IH_RB_CNTL, ih_rb_cntl);
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 	WREG32(IH_RB_RPTR, 0);
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 	WREG32(IH_RB_WPTR, 0);
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@@ -101,60 +104,50 @@
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 	mdelay(1);
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 }
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-static u32 si_ih_get_wptr(struct amdgpu_device *adev)
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+static u32 si_ih_get_wptr(struct amdgpu_device *adev,
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+			  struct amdgpu_ih_ring *ih)
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 {
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 	u32 wptr, tmp;
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-	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
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+	wptr = le32_to_cpu(*ih->wptr_cpu);
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 	if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
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 		wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
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 		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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-			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
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-		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
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+			wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
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+		ih->rptr = (wptr + 16) & ih->ptr_mask;
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 		tmp = RREG32(IH_RB_CNTL);
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 		tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
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 		WREG32(IH_RB_CNTL, tmp);
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 	}
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-	return (wptr & adev->irq.ih.ptr_mask);
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-}
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-
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-/**
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- * si_ih_prescreen_iv - prescreen an interrupt vector
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- *
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- * @adev: amdgpu_device pointer
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- *
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- * Returns true if the interrupt vector should be further processed.
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- */
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-static bool si_ih_prescreen_iv(struct amdgpu_device *adev)
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-{
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-	/* Process all interrupts */
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-	return true;
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+	return (wptr & ih->ptr_mask);
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 }
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 static void si_ih_decode_iv(struct amdgpu_device *adev,
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-			     struct amdgpu_iv_entry *entry)
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+			    struct amdgpu_ih_ring *ih,
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+			    struct amdgpu_iv_entry *entry)
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 {
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-	u32 ring_index = adev->irq.ih.rptr >> 2;
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+	u32 ring_index = ih->rptr >> 2;
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 	uint32_t dw[4];
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-	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
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-	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
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-	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
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-	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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+	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
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+	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
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+	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
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+	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
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-	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
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+	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
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 	entry->src_id = dw[0] & 0xff;
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 	entry->src_data[0] = dw[1] & 0xfffffff;
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 	entry->ring_id = dw[2] & 0xff;
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 	entry->vmid = (dw[2] >> 8) & 0xff;
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-	adev->irq.ih.rptr += 16;
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+	ih->rptr += 16;
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 }
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-static void si_ih_set_rptr(struct amdgpu_device *adev)
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+static void si_ih_set_rptr(struct amdgpu_device *adev,
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+			   struct amdgpu_ih_ring *ih)
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 {
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-	WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
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+	WREG32(IH_RB_RPTR, ih->rptr);
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 }
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 static int si_ih_early_init(void *handle)
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@@ -171,7 +164,7 @@
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 	int r;
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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-	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
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+	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
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 	if (r)
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 		return r;
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@@ -183,7 +176,7 @@
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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 	amdgpu_irq_fini(adev);
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-	amdgpu_ih_ring_fini(adev);
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+	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
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 	return 0;
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 }
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@@ -302,15 +295,13 @@
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 static const struct amdgpu_ih_funcs si_ih_funcs = {
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 	.get_wptr = si_ih_get_wptr,
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-	.prescreen_iv = si_ih_prescreen_iv,
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 	.decode_iv = si_ih_decode_iv,
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 	.set_rptr = si_ih_set_rptr
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 };
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 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
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 {
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-	if (adev->irq.ih_funcs == NULL)
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-		adev->irq.ih_funcs = &si_ih_funcs;
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+	adev->irq.ih_funcs = &si_ih_funcs;
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 }
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 const struct amdgpu_ip_block_version si_ih_ip_block =