~hc/RK356X_SDK_RELEASE.git

..	..	@@ -24,7 +24,8 @@
24	24	#include <linux/firmware.h>
25	25	#include <linux/slab.h>
26	26	#include <linux/module.h>
27		-#include <drm/drmP.h>
	27	+#include <linux/pci.h>
	28	+
28	29	#include "amdgpu.h"
29	30	#include "amdgpu_atombios.h"
30	31	#include "amdgpu_ih.h"
..	..	@@ -40,13 +41,18 @@
40	41	#include "si_dma.h"
41	42	#include "dce_v6_0.h"
42	43	#include "si.h"
	44	+#include "uvd_v3_1.h"
43	45	#include "dce_virtual.h"
44	46	#include "gca/gfx_6_0_d.h"
45	47	#include "oss/oss_1_0_d.h"
	48	+#include "oss/oss_1_0_sh_mask.h"
46	49	#include "gmc/gmc_6_0_d.h"
47	50	#include "dce/dce_6_0_d.h"
48	51	#include "uvd/uvd_4_0_d.h"
49	52	#include "bif/bif_3_0_d.h"
	53	+#include "bif/bif_3_0_sh_mask.h"
	54	+
	55	+#include "amdgpu_dm.h"
50	56
51	57	static const u32 tahiti_golden_registers[] =
52	58	{
..	..	@@ -971,8 +977,41 @@
971	977	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
972	978	}
973	979
	980	+static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
	981	+{
	982	+ unsigned long flags;
	983	+ u32 r;
	984	+
	985	+ spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
	986	+ WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
	987	+ r = RREG32(mmUVD_CTX_DATA);
	988	+ spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
	989	+ return r;
	990	+}
	991	+
	992	+static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
	993	+{
	994	+ unsigned long flags;
	995	+
	996	+ spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
	997	+ WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
	998	+ WREG32(mmUVD_CTX_DATA, (v));
	999	+ spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
	1000	+}
	1001	+
974	1002	static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
975	1003	{GRBM_STATUS},
	1004	+ {mmGRBM_STATUS2},
	1005	+ {mmGRBM_STATUS_SE0},
	1006	+ {mmGRBM_STATUS_SE1},
	1007	+ {mmSRBM_STATUS},
	1008	+ {mmSRBM_STATUS2},
	1009	+ {DMA_STATUS_REG + DMA0_REGISTER_OFFSET},
	1010	+ {DMA_STATUS_REG + DMA1_REGISTER_OFFSET},
	1011	+ {mmCP_STAT},
	1012	+ {mmCP_STALLED_STAT1},
	1013	+ {mmCP_STALLED_STAT2},
	1014	+ {mmCP_STALLED_STAT3},
976	1015	{GB_ADDR_CONFIG},
977	1016	{MC_ARB_RAMCFG},
978	1017	{GB_TILE_MODE0},
..	..	@@ -1178,10 +1217,116 @@
1178	1217	return true;
1179	1218	}
1180	1219
1181		-//xxx: not implemented
	1220	+static void si_set_clk_bypass_mode(struct amdgpu_device *adev)
	1221	+{
	1222	+ u32 tmp, i;
	1223	+
	1224	+ tmp = RREG32(CG_SPLL_FUNC_CNTL);
	1225	+ tmp \|= SPLL_BYPASS_EN;
	1226	+ WREG32(CG_SPLL_FUNC_CNTL, tmp);
	1227	+
	1228	+ tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
	1229	+ tmp \|= SPLL_CTLREQ_CHG;
	1230	+ WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
	1231	+
	1232	+ for (i = 0; i < adev->usec_timeout; i++) {
	1233	+ if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
	1234	+ break;
	1235	+ udelay(1);
	1236	+ }
	1237	+
	1238	+ tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
	1239	+ tmp &= ~(SPLL_CTLREQ_CHG \| SCLK_MUX_UPDATE);
	1240	+ WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
	1241	+
	1242	+ tmp = RREG32(MPLL_CNTL_MODE);
	1243	+ tmp &= ~MPLL_MCLK_SEL;
	1244	+ WREG32(MPLL_CNTL_MODE, tmp);
	1245	+}
	1246	+
	1247	+static void si_spll_powerdown(struct amdgpu_device *adev)
	1248	+{
	1249	+ u32 tmp;
	1250	+
	1251	+ tmp = RREG32(SPLL_CNTL_MODE);
	1252	+ tmp \|= SPLL_SW_DIR_CONTROL;
	1253	+ WREG32(SPLL_CNTL_MODE, tmp);
	1254	+
	1255	+ tmp = RREG32(CG_SPLL_FUNC_CNTL);
	1256	+ tmp \|= SPLL_RESET;
	1257	+ WREG32(CG_SPLL_FUNC_CNTL, tmp);
	1258	+
	1259	+ tmp = RREG32(CG_SPLL_FUNC_CNTL);
	1260	+ tmp \|= SPLL_SLEEP;
	1261	+ WREG32(CG_SPLL_FUNC_CNTL, tmp);
	1262	+
	1263	+ tmp = RREG32(SPLL_CNTL_MODE);
	1264	+ tmp &= ~SPLL_SW_DIR_CONTROL;
	1265	+ WREG32(SPLL_CNTL_MODE, tmp);
	1266	+}
	1267	+
	1268	+static int si_gpu_pci_config_reset(struct amdgpu_device *adev)
	1269	+{
	1270	+ u32 i;
	1271	+ int r = -EINVAL;
	1272	+
	1273	+ dev_info(adev->dev, "GPU pci config reset\n");
	1274	+
	1275	+ /* set mclk/sclk to bypass */
	1276	+ si_set_clk_bypass_mode(adev);
	1277	+ /* powerdown spll */
	1278	+ si_spll_powerdown(adev);
	1279	+ /* disable BM */
	1280	+ pci_clear_master(adev->pdev);
	1281	+ /* reset */
	1282	+ amdgpu_device_pci_config_reset(adev);
	1283	+
	1284	+ udelay(100);
	1285	+
	1286	+ /* wait for asic to come out of reset */
	1287	+ for (i = 0; i < adev->usec_timeout; i++) {
	1288	+ if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
	1289	+ /* enable BM */
	1290	+ pci_set_master(adev->pdev);
	1291	+ adev->has_hw_reset = true;
	1292	+ r = 0;
	1293	+ break;
	1294	+ }
	1295	+ udelay(1);
	1296	+ }
	1297	+
	1298	+ return r;
	1299	+}
	1300	+
1182	1301	static int si_asic_reset(struct amdgpu_device *adev)
1183	1302	{
1184		- return 0;
	1303	+ int r;
	1304	+
	1305	+ dev_info(adev->dev, "PCI CONFIG reset\n");
	1306	+
	1307	+ amdgpu_atombios_scratch_regs_engine_hung(adev, true);
	1308	+
	1309	+ r = si_gpu_pci_config_reset(adev);
	1310	+
	1311	+ amdgpu_atombios_scratch_regs_engine_hung(adev, false);
	1312	+
	1313	+ return r;
	1314	+}
	1315	+
	1316	+static bool si_asic_supports_baco(struct amdgpu_device *adev)
	1317	+{
	1318	+ return false;
	1319	+}
	1320	+
	1321	+static enum amd_reset_method
	1322	+si_asic_reset_method(struct amdgpu_device *adev)
	1323	+{
	1324	+ if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY &&
	1325	+ amdgpu_reset_method != -1)
	1326	+ dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
	1327	+ amdgpu_reset_method);
	1328	+
	1329	+ return AMD_RESET_METHOD_LEGACY;
1185	1330	}
1186	1331
1187	1332	static u32 si_get_config_memsize(struct amdgpu_device *adev)
..	..	@@ -1194,7 +1339,7 @@
1194	1339	uint32_t temp;
1195	1340
1196	1341	temp = RREG32(CONFIG_CNTL);
1197		- if (state == false) {
	1342	+ if (!state) {
1198	1343	temp &= ~(1<<0);
1199	1344	temp \|= (1<<1);
1200	1345	} else {
..	..	@@ -1217,18 +1362,6 @@
1217	1362	return reference_clock / 4;
1218	1363
1219	1364	return reference_clock;
1220		-}
1221		-
1222		-//xxx:not implemented
1223		-static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1224		-{
1225		- return 0;
1226		-}
1227		-
1228		-static void si_detect_hw_virtualization(struct amdgpu_device *adev)
1229		-{
1230		- if (is_virtual_machine()) /* passthrough mode */
1231		- adev->virt.caps \|= AMDGPU_PASSTHROUGH_MODE;
1232	1365	}
1233	1366
1234	1367	static void si_flush_hdp(struct amdgpu_device adev, struct amdgpu_ring ring)
..	..	@@ -1256,6 +1389,11 @@
1256	1389	{
1257	1390	/* change this when we support soft reset */
1258	1391	return true;
	1392	+}
	1393	+
	1394	+static bool si_need_reset_on_init(struct amdgpu_device *adev)
	1395	+{
	1396	+ return false;
1259	1397	}
1260	1398
1261	1399	static int si_get_pcie_lanes(struct amdgpu_device *adev)
..	..	@@ -1323,22 +1461,442 @@
1323	1461	WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1324	1462	}
1325	1463
	1464	+static void si_get_pcie_usage(struct amdgpu_device adev, uint64_t count0,
	1465	+ uint64_t *count1)
	1466	+{
	1467	+ uint32_t perfctr = 0;
	1468	+ uint64_t cnt0_of, cnt1_of;
	1469	+ int tmp;
	1470	+
	1471	+ /* This reports 0 on APUs, so return to avoid writing/reading registers
	1472	+ * that may or may not be different from their GPU counterparts
	1473	+ */
	1474	+ if (adev->flags & AMD_IS_APU)
	1475	+ return;
	1476	+
	1477	+ /* Set the 2 events that we wish to watch, defined above */
	1478	+ /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
	1479	+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
	1480	+ perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
	1481	+
	1482	+ /* Write to enable desired perf counters */
	1483	+ WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
	1484	+ /* Zero out and enable the perf counters
	1485	+ * Write 0x5:
	1486	+ * Bit 0 = Start all counters(1)
	1487	+ * Bit 2 = Global counter reset enable(1)
	1488	+ */
	1489	+ WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
	1490	+
	1491	+ msleep(1000);
	1492	+
	1493	+ /* Load the shadow and disable the perf counters
	1494	+ * Write 0x2:
	1495	+ * Bit 0 = Stop counters(0)
	1496	+ * Bit 1 = Load the shadow counters(1)
	1497	+ */
	1498	+ WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
	1499	+
	1500	+ /* Read register values to get any >32bit overflow */
	1501	+ tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
	1502	+ cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
	1503	+ cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
	1504	+
	1505	+ /* Get the values and add the overflow */
	1506	+ *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) \| (cnt0_of << 32);
	1507	+ *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) \| (cnt1_of << 32);
	1508	+}
	1509	+
	1510	+static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev)
	1511	+{
	1512	+ uint64_t nak_r, nak_g;
	1513	+
	1514	+ /* Get the number of NAKs received and generated */
	1515	+ nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
	1516	+ nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
	1517	+
	1518	+ /* Add the total number of NAKs, i.e the number of replays */
	1519	+ return (nak_r + nak_g);
	1520	+}
	1521	+
	1522	+static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev,
	1523	+ unsigned cg_upll_func_cntl)
	1524	+{
	1525	+ unsigned i;
	1526	+
	1527	+ /* Make sure UPLL_CTLREQ is deasserted */
	1528	+ WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
	1529	+
	1530	+ mdelay(10);
	1531	+
	1532	+ /* Assert UPLL_CTLREQ */
	1533	+ WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
	1534	+
	1535	+ /* Wait for CTLACK and CTLACK2 to get asserted */
	1536	+ for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {
	1537	+ uint32_t mask = UPLL_CTLACK_MASK \| UPLL_CTLACK2_MASK;
	1538	+
	1539	+ if ((RREG32(cg_upll_func_cntl) & mask) == mask)
	1540	+ break;
	1541	+ mdelay(10);
	1542	+ }
	1543	+
	1544	+ /* Deassert UPLL_CTLREQ */
	1545	+ WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
	1546	+
	1547	+ if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) {
	1548	+ DRM_ERROR("Timeout setting UVD clocks!\n");
	1549	+ return -ETIMEDOUT;
	1550	+ }
	1551	+
	1552	+ return 0;
	1553	+}
	1554	+
	1555	+static unsigned si_uvd_calc_upll_post_div(unsigned vco_freq,
	1556	+ unsigned target_freq,
	1557	+ unsigned pd_min,
	1558	+ unsigned pd_even)
	1559	+{
	1560	+ unsigned post_div = vco_freq / target_freq;
	1561	+
	1562	+ /* Adjust to post divider minimum value */
	1563	+ if (post_div < pd_min)
	1564	+ post_div = pd_min;
	1565	+
	1566	+ /* We alway need a frequency less than or equal the target */
	1567	+ if ((vco_freq / post_div) > target_freq)
	1568	+ post_div += 1;
	1569	+
	1570	+ /* Post dividers above a certain value must be even */
	1571	+ if (post_div > pd_even && post_div % 2)
	1572	+ post_div += 1;
	1573	+
	1574	+ return post_div;
	1575	+}
	1576	+
	1577	+/**
	1578	+ * si_calc_upll_dividers - calc UPLL clock dividers
	1579	+ *
	1580	+ * @adev: amdgpu_device pointer
	1581	+ * @vclk: wanted VCLK
	1582	+ * @dclk: wanted DCLK
	1583	+ * @vco_min: minimum VCO frequency
	1584	+ * @vco_max: maximum VCO frequency
	1585	+ * @fb_factor: factor to multiply vco freq with
	1586	+ * @fb_mask: limit and bitmask for feedback divider
	1587	+ * @pd_min: post divider minimum
	1588	+ * @pd_max: post divider maximum
	1589	+ * @pd_even: post divider must be even above this value
	1590	+ * @optimal_fb_div: resulting feedback divider
	1591	+ * @optimal_vclk_div: resulting vclk post divider
	1592	+ * @optimal_dclk_div: resulting dclk post divider
	1593	+ *
	1594	+ * Calculate dividers for UVDs UPLL (except APUs).
	1595	+ * Returns zero on success; -EINVAL on error.
	1596	+ */
	1597	+static int si_calc_upll_dividers(struct amdgpu_device *adev,
	1598	+ unsigned vclk, unsigned dclk,
	1599	+ unsigned vco_min, unsigned vco_max,
	1600	+ unsigned fb_factor, unsigned fb_mask,
	1601	+ unsigned pd_min, unsigned pd_max,
	1602	+ unsigned pd_even,
	1603	+ unsigned *optimal_fb_div,
	1604	+ unsigned *optimal_vclk_div,
	1605	+ unsigned *optimal_dclk_div)
	1606	+{
	1607	+ unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq;
	1608	+
	1609	+ /* Start off with something large */
	1610	+ unsigned optimal_score = ~0;
	1611	+
	1612	+ /* Loop through vco from low to high */
	1613	+ vco_min = max(max(vco_min, vclk), dclk);
	1614	+ for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
	1615	+ uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
	1616	+ unsigned vclk_div, dclk_div, score;
	1617	+
	1618	+ do_div(fb_div, ref_freq);
	1619	+
	1620	+ /* fb div out of range ? */
	1621	+ if (fb_div > fb_mask)
	1622	+ break; /* It can oly get worse */
	1623	+
	1624	+ fb_div &= fb_mask;
	1625	+
	1626	+ /* Calc vclk divider with current vco freq */
	1627	+ vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk,
	1628	+ pd_min, pd_even);
	1629	+ if (vclk_div > pd_max)
	1630	+ break; /* vco is too big, it has to stop */
	1631	+
	1632	+ /* Calc dclk divider with current vco freq */
	1633	+ dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk,
	1634	+ pd_min, pd_even);
	1635	+ if (dclk_div > pd_max)
	1636	+ break; /* vco is too big, it has to stop */
	1637	+
	1638	+ /* Calc score with current vco freq */
	1639	+ score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
	1640	+
	1641	+ /* Determine if this vco setting is better than current optimal settings */
	1642	+ if (score < optimal_score) {
	1643	+ *optimal_fb_div = fb_div;
	1644	+ *optimal_vclk_div = vclk_div;
	1645	+ *optimal_dclk_div = dclk_div;
	1646	+ optimal_score = score;
	1647	+ if (optimal_score == 0)
	1648	+ break; /* It can't get better than this */
	1649	+ }
	1650	+ }
	1651	+
	1652	+ /* Did we found a valid setup ? */
	1653	+ if (optimal_score == ~0)
	1654	+ return -EINVAL;
	1655	+
	1656	+ return 0;
	1657	+}
	1658	+
	1659	+static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
	1660	+{
	1661	+ unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
	1662	+ int r;
	1663	+
	1664	+ /* Bypass vclk and dclk with bclk */
	1665	+ WREG32_P(CG_UPLL_FUNC_CNTL_2,
	1666	+ VCLK_SRC_SEL(1) \| DCLK_SRC_SEL(1),
	1667	+ ~(VCLK_SRC_SEL_MASK \| DCLK_SRC_SEL_MASK));
	1668	+
	1669	+ /* Put PLL in bypass mode */
	1670	+ WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
	1671	+
	1672	+ if (!vclk \|\| !dclk) {
	1673	+ /* Keep the Bypass mode */
	1674	+ return 0;
	1675	+ }
	1676	+
	1677	+ r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000,
	1678	+ 16384, 0x03FFFFFF, 0, 128, 5,
	1679	+ &fb_div, &vclk_div, &dclk_div);
	1680	+ if (r)
	1681	+ return r;
	1682	+
	1683	+ /* Set RESET_ANTI_MUX to 0 */
	1684	+ WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
	1685	+
	1686	+ /* Set VCO_MODE to 1 */
	1687	+ WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
	1688	+
	1689	+ /* Disable sleep mode */
	1690	+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
	1691	+
	1692	+ /* Deassert UPLL_RESET */
	1693	+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
	1694	+
	1695	+ mdelay(1);
	1696	+
	1697	+ r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
	1698	+ if (r)
	1699	+ return r;
	1700	+
	1701	+ /* Assert UPLL_RESET again */
	1702	+ WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
	1703	+
	1704	+ /* Disable spread spectrum. */
	1705	+ WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
	1706	+
	1707	+ /* Set feedback divider */
	1708	+ WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
	1709	+
	1710	+ /* Set ref divider to 0 */
	1711	+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
	1712	+
	1713	+ if (fb_div < 307200)
	1714	+ WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
	1715	+ else
	1716	+ WREG32_P(CG_UPLL_FUNC_CNTL_4,
	1717	+ UPLL_SPARE_ISPARE9,
	1718	+ ~UPLL_SPARE_ISPARE9);
	1719	+
	1720	+ /* Set PDIV_A and PDIV_B */
	1721	+ WREG32_P(CG_UPLL_FUNC_CNTL_2,
	1722	+ UPLL_PDIV_A(vclk_div) \| UPLL_PDIV_B(dclk_div),
	1723	+ ~(UPLL_PDIV_A_MASK \| UPLL_PDIV_B_MASK));
	1724	+
	1725	+ /* Give the PLL some time to settle */
	1726	+ mdelay(15);
	1727	+
	1728	+ /* Deassert PLL_RESET */
	1729	+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
	1730	+
	1731	+ mdelay(15);
	1732	+
	1733	+ /* Switch from bypass mode to normal mode */
	1734	+ WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
	1735	+
	1736	+ r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
	1737	+ if (r)
	1738	+ return r;
	1739	+
	1740	+ /* Switch VCLK and DCLK selection */
	1741	+ WREG32_P(CG_UPLL_FUNC_CNTL_2,
	1742	+ VCLK_SRC_SEL(2) \| DCLK_SRC_SEL(2),
	1743	+ ~(VCLK_SRC_SEL_MASK \| DCLK_SRC_SEL_MASK));
	1744	+
	1745	+ mdelay(100);
	1746	+
	1747	+ return 0;
	1748	+}
	1749	+
	1750	+static int si_vce_send_vcepll_ctlreq(struct amdgpu_device *adev)
	1751	+{
	1752	+ unsigned i;
	1753	+
	1754	+ /* Make sure VCEPLL_CTLREQ is deasserted */
	1755	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
	1756	+
	1757	+ mdelay(10);
	1758	+
	1759	+ /* Assert UPLL_CTLREQ */
	1760	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
	1761	+
	1762	+ /* Wait for CTLACK and CTLACK2 to get asserted */
	1763	+ for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {
	1764	+ uint32_t mask = UPLL_CTLACK_MASK \| UPLL_CTLACK2_MASK;
	1765	+
	1766	+ if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
	1767	+ break;
	1768	+ mdelay(10);
	1769	+ }
	1770	+
	1771	+ /* Deassert UPLL_CTLREQ */
	1772	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
	1773	+
	1774	+ if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) {
	1775	+ DRM_ERROR("Timeout setting UVD clocks!\n");
	1776	+ return -ETIMEDOUT;
	1777	+ }
	1778	+
	1779	+ return 0;
	1780	+}
	1781	+
	1782	+static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
	1783	+{
	1784	+ unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;
	1785	+ int r;
	1786	+
	1787	+ /* Bypass evclk and ecclk with bclk */
	1788	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
	1789	+ EVCLK_SRC_SEL(1) \| ECCLK_SRC_SEL(1),
	1790	+ ~(EVCLK_SRC_SEL_MASK \| ECCLK_SRC_SEL_MASK));
	1791	+
	1792	+ /* Put PLL in bypass mode */
	1793	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
	1794	+ ~VCEPLL_BYPASS_EN_MASK);
	1795	+
	1796	+ if (!evclk \|\| !ecclk) {
	1797	+ /* Keep the Bypass mode, put PLL to sleep */
	1798	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
	1799	+ ~VCEPLL_SLEEP_MASK);
	1800	+ return 0;
	1801	+ }
	1802	+
	1803	+ r = si_calc_upll_dividers(adev, evclk, ecclk, 125000, 250000,
	1804	+ 16384, 0x03FFFFFF, 0, 128, 5,
	1805	+ &fb_div, &evclk_div, &ecclk_div);
	1806	+ if (r)
	1807	+ return r;
	1808	+
	1809	+ /* Set RESET_ANTI_MUX to 0 */
	1810	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
	1811	+
	1812	+ /* Set VCO_MODE to 1 */
	1813	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
	1814	+ ~VCEPLL_VCO_MODE_MASK);
	1815	+
	1816	+ /* Toggle VCEPLL_SLEEP to 1 then back to 0 */
	1817	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
	1818	+ ~VCEPLL_SLEEP_MASK);
	1819	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
	1820	+
	1821	+ /* Deassert VCEPLL_RESET */
	1822	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
	1823	+
	1824	+ mdelay(1);
	1825	+
	1826	+ r = si_vce_send_vcepll_ctlreq(adev);
	1827	+ if (r)
	1828	+ return r;
	1829	+
	1830	+ /* Assert VCEPLL_RESET again */
	1831	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
	1832	+
	1833	+ /* Disable spread spectrum. */
	1834	+ WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
	1835	+
	1836	+ /* Set feedback divider */
	1837	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3,
	1838	+ VCEPLL_FB_DIV(fb_div),
	1839	+ ~VCEPLL_FB_DIV_MASK);
	1840	+
	1841	+ /* Set ref divider to 0 */
	1842	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
	1843	+
	1844	+ /* Set PDIV_A and PDIV_B */
	1845	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
	1846	+ VCEPLL_PDIV_A(evclk_div) \| VCEPLL_PDIV_B(ecclk_div),
	1847	+ ~(VCEPLL_PDIV_A_MASK \| VCEPLL_PDIV_B_MASK));
	1848	+
	1849	+ /* Give the PLL some time to settle */
	1850	+ mdelay(15);
	1851	+
	1852	+ /* Deassert PLL_RESET */
	1853	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
	1854	+
	1855	+ mdelay(15);
	1856	+
	1857	+ /* Switch from bypass mode to normal mode */
	1858	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);
	1859	+
	1860	+ r = si_vce_send_vcepll_ctlreq(adev);
	1861	+ if (r)
	1862	+ return r;
	1863	+
	1864	+ /* Switch VCLK and DCLK selection */
	1865	+ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
	1866	+ EVCLK_SRC_SEL(16) \| ECCLK_SRC_SEL(16),
	1867	+ ~(EVCLK_SRC_SEL_MASK \| ECCLK_SRC_SEL_MASK));
	1868	+
	1869	+ mdelay(100);
	1870	+
	1871	+ return 0;
	1872	+}
	1873	+
	1874	+static void si_pre_asic_init(struct amdgpu_device *adev)
	1875	+{
	1876	+}
	1877	+
1326	1878	static const struct amdgpu_asic_funcs si_asic_funcs =
1327	1879	{
1328	1880	.read_disabled_bios = &si_read_disabled_bios,
1329	1881	.read_bios_from_rom = &si_read_bios_from_rom,
1330	1882	.read_register = &si_read_register,
1331	1883	.reset = &si_asic_reset,
	1884	+ .reset_method = &si_asic_reset_method,
1332	1885	.set_vga_state = &si_vga_set_state,
1333	1886	.get_xclk = &si_get_xclk,
1334	1887	.set_uvd_clocks = &si_set_uvd_clocks,
1335		- .set_vce_clocks = NULL,
	1888	+ .set_vce_clocks = &si_set_vce_clocks,
1336	1889	.get_pcie_lanes = &si_get_pcie_lanes,
1337	1890	.set_pcie_lanes = &si_set_pcie_lanes,
1338	1891	.get_config_memsize = &si_get_config_memsize,
1339	1892	.flush_hdp = &si_flush_hdp,
1340	1893	.invalidate_hdp = &si_invalidate_hdp,
1341	1894	.need_full_reset = &si_need_full_reset,
	1895	+ .get_pcie_usage = &si_get_pcie_usage,
	1896	+ .need_reset_on_init = &si_need_reset_on_init,
	1897	+ .get_pcie_replay_count = &si_get_pcie_replay_count,
	1898	+ .supports_baco = &si_asic_supports_baco,
	1899	+ .pre_asic_init = &si_pre_asic_init,
1342	1900	};
1343	1901
1344	1902	static uint32_t si_get_rev_id(struct amdgpu_device *adev)
..	..	@@ -1357,8 +1915,8 @@
1357	1915	adev->pcie_wreg = &si_pcie_wreg;
1358	1916	adev->pciep_rreg = &si_pciep_rreg;
1359	1917	adev->pciep_wreg = &si_pciep_wreg;
1360		- adev->uvd_ctx_rreg = NULL;
1361		- adev->uvd_ctx_wreg = NULL;
	1918	+ adev->uvd_ctx_rreg = si_uvd_ctx_rreg;
	1919	+ adev->uvd_ctx_wreg = si_uvd_ctx_wreg;
1362	1920	adev->didt_rreg = NULL;
1363	1921	adev->didt_wreg = NULL;
1364	1922
..	..	@@ -1382,7 +1940,7 @@
1382	1940	AMD_CG_SUPPORT_UVD_MGCG \|
1383	1941	AMD_CG_SUPPORT_HDP_LS \|
1384	1942	AMD_CG_SUPPORT_HDP_MGCG;
1385		- adev->pg_flags = 0;
	1943	+ adev->pg_flags = 0;
1386	1944	adev->external_rev_id = (adev->rev_id == 0) ? 1 :
1387	1945	(adev->rev_id == 1) ? 5 : 6;
1388	1946	break;
..	..	@@ -1558,7 +2116,6 @@
1558	2116	static void si_pcie_gen3_enable(struct amdgpu_device *adev)
1559	2117	{
1560	2118	struct pci_dev *root = adev->pdev->bus->self;
1561		- int bridge_pos, gpu_pos;
1562	2119	u32 speed_cntl, current_data_rate;
1563	2120	int i;
1564	2121	u16 tmp16;
..	..	@@ -1593,12 +2150,7 @@
1593	2150	DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1594	2151	}
1595	2152
1596		- bridge_pos = pci_pcie_cap(root);
1597		- if (!bridge_pos)
1598		- return;
1599		-
1600		- gpu_pos = pci_pcie_cap(adev->pdev);
1601		- if (!gpu_pos)
	2153	+ if (!pci_is_pcie(root) \|\| !pci_is_pcie(adev->pdev))
1602	2154	return;
1603	2155
1604	2156	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
..	..	@@ -1607,14 +2159,17 @@
1607	2159	u16 bridge_cfg2, gpu_cfg2;
1608	2160	u32 max_lw, current_lw, tmp;
1609	2161
1610		- pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1611		- pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
	2162	+ pcie_capability_read_word(root, PCI_EXP_LNKCTL,
	2163	+ &bridge_cfg);
	2164	+ pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
	2165	+ &gpu_cfg);
1612	2166
1613	2167	tmp16 = bridge_cfg \| PCI_EXP_LNKCTL_HAWD;
1614		- pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
	2168	+ pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
1615	2169
1616	2170	tmp16 = gpu_cfg \| PCI_EXP_LNKCTL_HAWD;
1617		- pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
	2171	+ pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
	2172	+ tmp16);
1618	2173
1619	2174	tmp = RREG32_PCIE(PCIE_LC_STATUS1);
1620	2175	max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
..	..	@@ -1631,15 +2186,23 @@
1631	2186	}
1632	2187
1633	2188	for (i = 0; i < 10; i++) {
1634		- pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
	2189	+ pcie_capability_read_word(adev->pdev,
	2190	+ PCI_EXP_DEVSTA,
	2191	+ &tmp16);
1635	2192	if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1636	2193	break;
1637	2194
1638		- pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1639		- pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
	2195	+ pcie_capability_read_word(root, PCI_EXP_LNKCTL,
	2196	+ &bridge_cfg);
	2197	+ pcie_capability_read_word(adev->pdev,
	2198	+ PCI_EXP_LNKCTL,
	2199	+ &gpu_cfg);
1640	2200
1641		- pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1642		- pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
	2201	+ pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
	2202	+ &bridge_cfg2);
	2203	+ pcie_capability_read_word(adev->pdev,
	2204	+ PCI_EXP_LNKCTL2,
	2205	+ &gpu_cfg2);
1643	2206
1644	2207	tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1645	2208	tmp \|= LC_SET_QUIESCE;
..	..	@@ -1651,25 +2214,44 @@
1651	2214
1652	2215	mdelay(100);
1653	2216
1654		- pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
	2217	+ pcie_capability_read_word(root, PCI_EXP_LNKCTL,
	2218	+ &tmp16);
1655	2219	tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1656	2220	tmp16 \|= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1657		- pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
	2221	+ pcie_capability_write_word(root, PCI_EXP_LNKCTL,
	2222	+ tmp16);
1658	2223
1659		- pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
	2224	+ pcie_capability_read_word(adev->pdev,
	2225	+ PCI_EXP_LNKCTL,
	2226	+ &tmp16);
1660	2227	tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1661	2228	tmp16 \|= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1662		- pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
	2229	+ pcie_capability_write_word(adev->pdev,
	2230	+ PCI_EXP_LNKCTL,
	2231	+ tmp16);
1663	2232
1664		- pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1665		- tmp16 &= ~((1 << 4) \| (7 << 9));
1666		- tmp16 \|= (bridge_cfg2 & ((1 << 4) \| (7 << 9)));
1667		- pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
	2233	+ pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
	2234	+ &tmp16);
	2235	+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP \|
	2236	+ PCI_EXP_LNKCTL2_TX_MARGIN);
	2237	+ tmp16 \|= (bridge_cfg2 &
	2238	+ (PCI_EXP_LNKCTL2_ENTER_COMP \|
	2239	+ PCI_EXP_LNKCTL2_TX_MARGIN));
	2240	+ pcie_capability_write_word(root,
	2241	+ PCI_EXP_LNKCTL2,
	2242	+ tmp16);
1668	2243
1669		- pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1670		- tmp16 &= ~((1 << 4) \| (7 << 9));
1671		- tmp16 \|= (gpu_cfg2 & ((1 << 4) \| (7 << 9)));
1672		- pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
	2244	+ pcie_capability_read_word(adev->pdev,
	2245	+ PCI_EXP_LNKCTL2,
	2246	+ &tmp16);
	2247	+ tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP \|
	2248	+ PCI_EXP_LNKCTL2_TX_MARGIN);
	2249	+ tmp16 \|= (gpu_cfg2 &
	2250	+ (PCI_EXP_LNKCTL2_ENTER_COMP \|
	2251	+ PCI_EXP_LNKCTL2_TX_MARGIN));
	2252	+ pcie_capability_write_word(adev->pdev,
	2253	+ PCI_EXP_LNKCTL2,
	2254	+ tmp16);
1673	2255
1674	2256	tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
1675	2257	tmp &= ~LC_SET_QUIESCE;
..	..	@@ -1682,15 +2264,16 @@
1682	2264	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
1683	2265	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
1684	2266
1685		- pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1686		- tmp16 &= ~0xf;
	2267	+ pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
	2268	+ tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
	2269	+
1687	2270	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1688		- tmp16 \|= 3;
	2271	+ tmp16 \|= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
1689	2272	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1690		- tmp16 \|= 2;
	2273	+ tmp16 \|= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
1691	2274	else
1692		- tmp16 \|= 1;
1693		- pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
	2275	+ tmp16 \|= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
	2276	+ pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
1694	2277
1695	2278	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1696	2279	speed_cntl \|= LC_INITIATE_LINK_SPEED_CHANGE;
..	..	@@ -2048,8 +2631,6 @@
2048	2631
2049	2632	int si_set_ip_blocks(struct amdgpu_device *adev)
2050	2633	{
2051		- si_detect_hw_virtualization(adev);
2052		-
2053	2634	switch (adev->asic_type) {
2054	2635	case CHIP_VERDE:
2055	2636	case CHIP_TAHITI:
..	..	@@ -2057,39 +2638,47 @@
2057	2638	amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2058	2639	amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2059	2640	amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
	2641	+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
	2642	+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2060	2643	amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2061	2644	if (adev->enable_virtual_display)
2062	2645	amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
	2646	+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
	2647	+ else if (amdgpu_device_has_dc_support(adev))
	2648	+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
	2649	+#endif
2063	2650	else
2064	2651	amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
2065		- amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2066		- amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2067		- /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
	2652	+ amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
2068	2653	/* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
2069	2654	break;
2070	2655	case CHIP_OLAND:
2071	2656	amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2072	2657	amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2073	2658	amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
	2659	+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
	2660	+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2074	2661	amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2075	2662	if (adev->enable_virtual_display)
2076	2663	amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
	2664	+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
	2665	+ else if (amdgpu_device_has_dc_support(adev))
	2666	+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
	2667	+#endif
2077	2668	else
2078	2669	amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
2079		- amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2080		- amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2081		- /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
	2670	+ amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
2082	2671	/* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
2083	2672	break;
2084	2673	case CHIP_HAINAN:
2085	2674	amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2086	2675	amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2087	2676	amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
	2677	+ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
	2678	+ amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2088	2679	amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2089	2680	if (adev->enable_virtual_display)
2090	2681	amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
2091		- amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2092		- amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2093	2682	break;
2094	2683	default:
2095	2684	BUG();