forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
....@@ -24,7 +24,9 @@
2424  */
2525 
2626 #include <linux/firmware.h>
27
-#include <drm/drmP.h>
27
+#include <linux/module.h>
28
+#include <linux/pci.h>
29
+
2830 #include "amdgpu.h"
2931 #include "amdgpu_psp.h"
3032 #include "amdgpu_ucode.h"
....@@ -37,76 +39,25 @@
3739 #include "sdma0/sdma0_4_0_offset.h"
3840 #include "nbio/nbio_6_1_offset.h"
3941 
42
+#include "oss/osssys_4_0_offset.h"
43
+#include "oss/osssys_4_0_sh_mask.h"
44
+
4045 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
4146 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
4247 MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
4348 MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
44
-MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
45
-MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
4649 
4750 
4851 #define smnMP1_FIRMWARE_FLAGS 0x3010028
4952 
50
-static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554};
51
-
52
-static int
53
-psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
54
-{
55
-	switch(ucode->ucode_id) {
56
-	case AMDGPU_UCODE_ID_SDMA0:
57
-		*type = GFX_FW_TYPE_SDMA0;
58
-		break;
59
-	case AMDGPU_UCODE_ID_SDMA1:
60
-		*type = GFX_FW_TYPE_SDMA1;
61
-		break;
62
-	case AMDGPU_UCODE_ID_CP_CE:
63
-		*type = GFX_FW_TYPE_CP_CE;
64
-		break;
65
-	case AMDGPU_UCODE_ID_CP_PFP:
66
-		*type = GFX_FW_TYPE_CP_PFP;
67
-		break;
68
-	case AMDGPU_UCODE_ID_CP_ME:
69
-		*type = GFX_FW_TYPE_CP_ME;
70
-		break;
71
-	case AMDGPU_UCODE_ID_CP_MEC1:
72
-		*type = GFX_FW_TYPE_CP_MEC;
73
-		break;
74
-	case AMDGPU_UCODE_ID_CP_MEC1_JT:
75
-		*type = GFX_FW_TYPE_CP_MEC_ME1;
76
-		break;
77
-	case AMDGPU_UCODE_ID_CP_MEC2:
78
-		*type = GFX_FW_TYPE_CP_MEC;
79
-		break;
80
-	case AMDGPU_UCODE_ID_CP_MEC2_JT:
81
-		*type = GFX_FW_TYPE_CP_MEC_ME2;
82
-		break;
83
-	case AMDGPU_UCODE_ID_RLC_G:
84
-		*type = GFX_FW_TYPE_RLC_G;
85
-		break;
86
-	case AMDGPU_UCODE_ID_SMC:
87
-		*type = GFX_FW_TYPE_SMU;
88
-		break;
89
-	case AMDGPU_UCODE_ID_UVD:
90
-		*type = GFX_FW_TYPE_UVD;
91
-		break;
92
-	case AMDGPU_UCODE_ID_VCE:
93
-		*type = GFX_FW_TYPE_VCE;
94
-		break;
95
-	case AMDGPU_UCODE_ID_MAXIMUM:
96
-	default:
97
-		return -EINVAL;
98
-	}
99
-
100
-	return 0;
101
-}
53
+static int psp_v3_1_ring_stop(struct psp_context *psp,
54
+			      enum psp_ring_type ring_type);
10255 
10356 static int psp_v3_1_init_microcode(struct psp_context *psp)
10457 {
10558 	struct amdgpu_device *adev = psp->adev;
10659 	const char *chip_name;
107
-	char fw_name[30];
10860 	int err = 0;
109
-	const struct psp_firmware_header_v1_0 *hdr;
11061 
11162 	DRM_DEBUG("\n");
11263 
....@@ -120,55 +71,15 @@
12071 	default: BUG();
12172 	}
12273 
123
-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
124
-	err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
74
+	err = psp_init_sos_microcode(psp, chip_name);
12575 	if (err)
126
-		goto out;
76
+		return err;
12777 
128
-	err = amdgpu_ucode_validate(adev->psp.sos_fw);
78
+	err = psp_init_asd_microcode(psp, chip_name);
12979 	if (err)
130
-		goto out;
131
-
132
-	hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
133
-	adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
134
-	adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
135
-	adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
136
-	adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
137
-					le32_to_cpu(hdr->sos_size_bytes);
138
-	adev->psp.sys_start_addr = (uint8_t *)hdr +
139
-				le32_to_cpu(hdr->header.ucode_array_offset_bytes);
140
-	adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
141
-				le32_to_cpu(hdr->sos_offset_bytes);
142
-
143
-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
144
-	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
145
-	if (err)
146
-		goto out;
147
-
148
-	err = amdgpu_ucode_validate(adev->psp.asd_fw);
149
-	if (err)
150
-		goto out;
151
-
152
-	hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
153
-	adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
154
-	adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
155
-	adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
156
-	adev->psp.asd_start_addr = (uint8_t *)hdr +
157
-				le32_to_cpu(hdr->header.ucode_array_offset_bytes);
80
+		return err;
15881 
15982 	return 0;
160
-out:
161
-	if (err) {
162
-		dev_err(adev->dev,
163
-			"psp v3.1: Failed to load firmware \"%s\"\n",
164
-			fw_name);
165
-		release_firmware(adev->psp.sos_fw);
166
-		adev->psp.sos_fw = NULL;
167
-		release_firmware(adev->psp.asd_fw);
168
-		adev->psp.asd_fw = NULL;
169
-	}
170
-
171
-	return err;
17283 }
17384 
17485 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
....@@ -196,10 +107,10 @@
196107 	/* Copy PSP System Driver binary to memory */
197108 	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
198109 
199
-	/* Provide the sys driver to bootrom */
110
+	/* Provide the sys driver to bootloader */
200111 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
201112 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
202
-	psp_gfxdrv_command_reg = 1 << 16;
113
+	psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
203114 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
204115 	       psp_gfxdrv_command_reg);
205116 
....@@ -212,31 +123,12 @@
212123 	return ret;
213124 }
214125 
215
-static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver)
216
-{
217
-	int i;
218
-
219
-	if (ver == adev->psp.sos_fw_version)
220
-		return true;
221
-
222
-	/*
223
-	 * Double check if the latest four legacy versions.
224
-	 * If yes, it is still the right version.
225
-	 */
226
-	for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) {
227
-		if (sos_old_versions[i] == adev->psp.sos_fw_version)
228
-			return true;
229
-	}
230
-
231
-	return false;
232
-}
233
-
234126 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
235127 {
236128 	int ret;
237129 	unsigned int psp_gfxdrv_command_reg = 0;
238130 	struct amdgpu_device *adev = psp->adev;
239
-	uint32_t sol_reg, ver;
131
+	uint32_t sol_reg;
240132 
241133 	/* Check sOS sign of life register to confirm sys driver and sOS
242134 	 * are already been loaded.
....@@ -256,10 +148,10 @@
256148 	/* Copy Secure OS binary to PSP memory */
257149 	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
258150 
259
-	/* Provide the PSP secure OS to bootrom */
151
+	/* Provide the PSP secure OS to bootloader */
260152 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
261153 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
262
-	psp_gfxdrv_command_reg = 2 << 16;
154
+	psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
263155 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
264156 	       psp_gfxdrv_command_reg);
265157 
....@@ -268,31 +160,6 @@
268160 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
269161 			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
270162 			   0, true);
271
-
272
-	ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
273
-	if (!psp_v3_1_match_version(adev, ver))
274
-		DRM_WARN("SOS version doesn't match\n");
275
-
276
-	return ret;
277
-}
278
-
279
-static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
280
-				 struct psp_gfx_cmd_resp *cmd)
281
-{
282
-	int ret;
283
-	uint64_t fw_mem_mc_addr = ucode->mc_addr;
284
-
285
-	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
286
-
287
-	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
288
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
289
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
290
-	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
291
-
292
-	ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
293
-	if (ret)
294
-		DRM_ERROR("Unknown firmware type\n");
295
-
296163 	return ret;
297164 }
298165 
....@@ -322,6 +189,37 @@
322189 	return 0;
323190 }
324191 
192
+static void psp_v3_1_reroute_ih(struct psp_context *psp)
193
+{
194
+	struct amdgpu_device *adev = psp->adev;
195
+	uint32_t tmp;
196
+
197
+	/* Change IH ring for VMC */
198
+	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
199
+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
200
+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
201
+
202
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
203
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
204
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
205
+
206
+	mdelay(20);
207
+	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
208
+		     0x80000000, 0x8000FFFF, false);
209
+
210
+	/* Change IH ring for UMC */
211
+	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
212
+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
213
+
214
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
215
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
216
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
217
+
218
+	mdelay(20);
219
+	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
220
+		     0x80000000, 0x8000FFFF, false);
221
+}
222
+
325223 static int psp_v3_1_ring_create(struct psp_context *psp,
326224 				enum psp_ring_type ring_type)
327225 {
....@@ -330,27 +228,59 @@
330228 	struct psp_ring *ring = &psp->km_ring;
331229 	struct amdgpu_device *adev = psp->adev;
332230 
333
-	/* Write low address of the ring to C2PMSG_69 */
334
-	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
335
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
336
-	/* Write high address of the ring to C2PMSG_70 */
337
-	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
338
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
339
-	/* Write size of ring to C2PMSG_71 */
340
-	psp_ring_reg = ring->ring_size;
341
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
342
-	/* Write the ring initialization command to C2PMSG_64 */
343
-	psp_ring_reg = ring_type;
344
-	psp_ring_reg = psp_ring_reg << 16;
345
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
231
+	psp_v3_1_reroute_ih(psp);
346232 
347
-	/* there might be handshake issue with hardware which needs delay */
348
-	mdelay(20);
233
+	if (amdgpu_sriov_vf(adev)) {
234
+		ret = psp_v3_1_ring_stop(psp, ring_type);
235
+		if (ret) {
236
+			DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
237
+			return ret;
238
+		}
349239 
350
-	/* Wait for response flag (bit 31) in C2PMSG_64 */
351
-	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
352
-			   0x80000000, 0x8000FFFF, false);
240
+		/* Write low address of the ring to C2PMSG_102 */
241
+		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
242
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
243
+		/* Write high address of the ring to C2PMSG_103 */
244
+		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
245
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
246
+		/* No size initialization for sriov  */
247
+		/* Write the ring initialization command to C2PMSG_101 */
248
+		psp_ring_reg = ring_type;
249
+		psp_ring_reg = psp_ring_reg << 16;
250
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
353251 
252
+		/* there might be hardware handshake issue which needs delay */
253
+		mdelay(20);
254
+
255
+		/* Wait for response flag (bit 31) in C2PMSG_101 */
256
+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
257
+					mmMP0_SMN_C2PMSG_101), 0x80000000,
258
+					0x8000FFFF, false);
259
+	} else {
260
+
261
+		/* Write low address of the ring to C2PMSG_69 */
262
+		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
263
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
264
+		/* Write high address of the ring to C2PMSG_70 */
265
+		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
266
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
267
+		/* Write size of ring to C2PMSG_71 */
268
+		psp_ring_reg = ring->ring_size;
269
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
270
+		/* Write the ring initialization command to C2PMSG_64 */
271
+		psp_ring_reg = ring_type;
272
+		psp_ring_reg = psp_ring_reg << 16;
273
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
274
+
275
+		/* there might be hardware handshake issue which needs delay */
276
+		mdelay(20);
277
+
278
+		/* Wait for response flag (bit 31) in C2PMSG_64 */
279
+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
280
+					mmMP0_SMN_C2PMSG_64), 0x80000000,
281
+					0x8000FFFF, false);
282
+
283
+	}
354284 	return ret;
355285 }
356286 
....@@ -358,22 +288,26 @@
358288 			      enum psp_ring_type ring_type)
359289 {
360290 	int ret = 0;
361
-	struct psp_ring *ring;
362
-	unsigned int psp_ring_reg = 0;
363291 	struct amdgpu_device *adev = psp->adev;
364292 
365
-	ring = &psp->km_ring;
366
-
367
-	/* Write the ring destroy command to C2PMSG_64 */
368
-	psp_ring_reg = 3 << 16;
369
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
293
+	/* Write the ring destroy command*/
294
+	if (amdgpu_sriov_vf(adev))
295
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
296
+				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
297
+	else
298
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
299
+				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
370300 
371301 	/* there might be handshake issue with hardware which needs delay */
372302 	mdelay(20);
373303 
374
-	/* Wait for response flag (bit 31) in C2PMSG_64 */
375
-	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
376
-			   0x80000000, 0x80000000, false);
304
+	/* Wait for response flag (bit 31) */
305
+	if (amdgpu_sriov_vf(adev))
306
+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
307
+				   0x80000000, 0x80000000, false);
308
+	else
309
+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
310
+				   0x80000000, 0x80000000, false);
377311 
378312 	return ret;
379313 }
....@@ -396,186 +330,12 @@
396330 	return ret;
397331 }
398332 
399
-static int psp_v3_1_cmd_submit(struct psp_context *psp,
400
-			       struct amdgpu_firmware_info *ucode,
401
-			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
402
-			       int index)
403
-{
404
-	unsigned int psp_write_ptr_reg = 0;
405
-	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
406
-	struct psp_ring *ring = &psp->km_ring;
407
-	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
408
-	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
409
-		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
410
-	struct amdgpu_device *adev = psp->adev;
411
-	uint32_t ring_size_dw = ring->ring_size / 4;
412
-	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
413
-
414
-	/* KM (GPCOM) prepare write pointer */
415
-	psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
416
-
417
-	/* Update KM RB frame pointer to new frame */
418
-	/* write_frame ptr increments by size of rb_frame in bytes */
419
-	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
420
-	if ((psp_write_ptr_reg % ring_size_dw) == 0)
421
-		write_frame = ring_buffer_start;
422
-	else
423
-		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
424
-	/* Check invalid write_frame ptr address */
425
-	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
426
-		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
427
-			  ring_buffer_start, ring_buffer_end, write_frame);
428
-		DRM_ERROR("write_frame is pointing to address out of bounds\n");
429
-		return -EINVAL;
430
-	}
431
-
432
-	/* Initialize KM RB frame */
433
-	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
434
-
435
-	/* Update KM RB frame */
436
-	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
437
-	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
438
-	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
439
-	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
440
-	write_frame->fence_value = index;
441
-
442
-	/* Update the write Pointer in DWORDs */
443
-	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
444
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
445
-
446
-	return 0;
447
-}
448
-
449
-static int
450
-psp_v3_1_sram_map(struct amdgpu_device *adev,
451
-		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
452
-		  unsigned int *sram_data_reg_offset,
453
-		  enum AMDGPU_UCODE_ID ucode_id)
454
-{
455
-	int ret = 0;
456
-
457
-	switch(ucode_id) {
458
-/* TODO: needs to confirm */
459
-#if 0
460
-	case AMDGPU_UCODE_ID_SMC:
461
-		*sram_offset = 0;
462
-		*sram_addr_reg_offset = 0;
463
-		*sram_data_reg_offset = 0;
464
-		break;
465
-#endif
466
-
467
-	case AMDGPU_UCODE_ID_CP_CE:
468
-		*sram_offset = 0x0;
469
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
470
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
471
-		break;
472
-
473
-	case AMDGPU_UCODE_ID_CP_PFP:
474
-		*sram_offset = 0x0;
475
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
476
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
477
-		break;
478
-
479
-	case AMDGPU_UCODE_ID_CP_ME:
480
-		*sram_offset = 0x0;
481
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
482
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
483
-		break;
484
-
485
-	case AMDGPU_UCODE_ID_CP_MEC1:
486
-		*sram_offset = 0x10000;
487
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
488
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
489
-		break;
490
-
491
-	case AMDGPU_UCODE_ID_CP_MEC2:
492
-		*sram_offset = 0x10000;
493
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
494
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
495
-		break;
496
-
497
-	case AMDGPU_UCODE_ID_RLC_G:
498
-		*sram_offset = 0x2000;
499
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
500
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
501
-		break;
502
-
503
-	case AMDGPU_UCODE_ID_SDMA0:
504
-		*sram_offset = 0x0;
505
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
506
-		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
507
-		break;
508
-
509
-/* TODO: needs to confirm */
510
-#if 0
511
-	case AMDGPU_UCODE_ID_SDMA1:
512
-		*sram_offset = ;
513
-		*sram_addr_reg_offset = ;
514
-		break;
515
-
516
-	case AMDGPU_UCODE_ID_UVD:
517
-		*sram_offset = ;
518
-		*sram_addr_reg_offset = ;
519
-		break;
520
-
521
-	case AMDGPU_UCODE_ID_VCE:
522
-		*sram_offset = ;
523
-		*sram_addr_reg_offset = ;
524
-		break;
525
-#endif
526
-
527
-	case AMDGPU_UCODE_ID_MAXIMUM:
528
-	default:
529
-		ret = -EINVAL;
530
-		break;
531
-	}
532
-
533
-	return ret;
534
-}
535
-
536
-static bool psp_v3_1_compare_sram_data(struct psp_context *psp,
537
-				       struct amdgpu_firmware_info *ucode,
538
-				       enum AMDGPU_UCODE_ID ucode_type)
539
-{
540
-	int err = 0;
541
-	unsigned int fw_sram_reg_val = 0;
542
-	unsigned int fw_sram_addr_reg_offset = 0;
543
-	unsigned int fw_sram_data_reg_offset = 0;
544
-	unsigned int ucode_size;
545
-	uint32_t *ucode_mem = NULL;
546
-	struct amdgpu_device *adev = psp->adev;
547
-
548
-	err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
549
-				&fw_sram_data_reg_offset, ucode_type);
550
-	if (err)
551
-		return false;
552
-
553
-	WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
554
-
555
-	ucode_size = ucode->ucode_size;
556
-	ucode_mem = (uint32_t *)ucode->kaddr;
557
-	while (ucode_size) {
558
-		fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
559
-
560
-		if (*ucode_mem != fw_sram_reg_val)
561
-			return false;
562
-
563
-		ucode_mem++;
564
-		/* 4 bytes */
565
-		ucode_size -= 4;
566
-	}
567
-
568
-	return true;
569
-}
570
-
571333 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
572334 {
573335 	struct amdgpu_device *adev = psp->adev;
574336 	uint32_t reg;
575337 
576
-	reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;
577
-	WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg);
578
-	reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);
338
+	reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
579339 	return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
580340 }
581341 
....@@ -595,9 +355,9 @@
595355 	}
596356 
597357 	/*send the mode 1 reset command*/
598
-	WREG32(offset, 0x70000);
358
+	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
599359 
600
-	mdelay(1000);
360
+	msleep(500);
601361 
602362 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
603363 
....@@ -613,19 +373,44 @@
613373 	return 0;
614374 }
615375 
376
+static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
377
+{
378
+	uint32_t data;
379
+	struct amdgpu_device *adev = psp->adev;
380
+
381
+	if (amdgpu_sriov_vf(adev))
382
+		data = psp->km_ring.ring_wptr;
383
+	else
384
+		data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
385
+	return data;
386
+}
387
+
388
+static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
389
+{
390
+	struct amdgpu_device *adev = psp->adev;
391
+
392
+	if (amdgpu_sriov_vf(adev)) {
393
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
394
+		/* send interrupt to PSP for SRIOV ring write pointer update */
395
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
396
+			GFX_CTRL_CMD_ID_CONSUME_CMD);
397
+		psp->km_ring.ring_wptr = value;
398
+	} else
399
+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
400
+}
401
+
616402 static const struct psp_funcs psp_v3_1_funcs = {
617403 	.init_microcode = psp_v3_1_init_microcode,
618404 	.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
619405 	.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
620
-	.prep_cmd_buf = psp_v3_1_prep_cmd_buf,
621406 	.ring_init = psp_v3_1_ring_init,
622407 	.ring_create = psp_v3_1_ring_create,
623408 	.ring_stop = psp_v3_1_ring_stop,
624409 	.ring_destroy = psp_v3_1_ring_destroy,
625
-	.cmd_submit = psp_v3_1_cmd_submit,
626
-	.compare_sram_data = psp_v3_1_compare_sram_data,
627410 	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
628411 	.mode1_reset = psp_v3_1_mode1_reset,
412
+	.ring_get_wptr = psp_v3_1_ring_get_wptr,
413
+	.ring_set_wptr = psp_v3_1_ring_set_wptr,
629414 };
630415 
631416 void psp_v3_1_set_psp_funcs(struct psp_context *psp)