add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
..
..
@@ -24,6 +24,9 @@
24
24
  */
25
25
 
26
26
 #include <linux/firmware.h>
27
+#include <linux/module.h>
28
+#include <linux/pci.h>
29
+
27
30
 #include "amdgpu.h"
28
31
 #include "amdgpu_psp.h"
29
32
 #include "amdgpu_ucode.h"
..
..
@@ -35,69 +38,11 @@
35
38
 #include "sdma0/sdma0_4_1_offset.h"
36
39
 
37
40
 MODULE_FIRMWARE("amdgpu/raven_asd.bin");
38
-
39
-static int
40
-psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
41
-{
42
-	switch(ucode->ucode_id) {
43
-	case AMDGPU_UCODE_ID_SDMA0:
44
-		*type = GFX_FW_TYPE_SDMA0;
45
-		break;
46
-	case AMDGPU_UCODE_ID_SDMA1:
47
-		*type = GFX_FW_TYPE_SDMA1;
48
-		break;
49
-	case AMDGPU_UCODE_ID_CP_CE:
50
-		*type = GFX_FW_TYPE_CP_CE;
51
-		break;
52
-	case AMDGPU_UCODE_ID_CP_PFP:
53
-		*type = GFX_FW_TYPE_CP_PFP;
54
-		break;
55
-	case AMDGPU_UCODE_ID_CP_ME:
56
-		*type = GFX_FW_TYPE_CP_ME;
57
-		break;
58
-	case AMDGPU_UCODE_ID_CP_MEC1:
59
-		*type = GFX_FW_TYPE_CP_MEC;
60
-		break;
61
-	case AMDGPU_UCODE_ID_CP_MEC1_JT:
62
-		*type = GFX_FW_TYPE_CP_MEC_ME1;
63
-		break;
64
-	case AMDGPU_UCODE_ID_CP_MEC2:
65
-		*type = GFX_FW_TYPE_CP_MEC;
66
-		break;
67
-	case AMDGPU_UCODE_ID_CP_MEC2_JT:
68
-		*type = GFX_FW_TYPE_CP_MEC_ME2;
69
-		break;
70
-	case AMDGPU_UCODE_ID_RLC_G:
71
-		*type = GFX_FW_TYPE_RLC_G;
72
-		break;
73
-	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
74
-		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
75
-		break;
76
-	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
77
-		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
78
-		break;
79
-	case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
80
-		*type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
81
-		break;
82
-	case AMDGPU_UCODE_ID_SMC:
83
-		*type = GFX_FW_TYPE_SMU;
84
-		break;
85
-	case AMDGPU_UCODE_ID_UVD:
86
-		*type = GFX_FW_TYPE_UVD;
87
-		break;
88
-	case AMDGPU_UCODE_ID_VCE:
89
-		*type = GFX_FW_TYPE_VCE;
90
-		break;
91
-	case AMDGPU_UCODE_ID_VCN:
92
-		*type = GFX_FW_TYPE_VCN;
93
-		break;
94
-	case AMDGPU_UCODE_ID_MAXIMUM:
95
-	default:
96
-		return -EINVAL;
97
-	}
98
-
99
-	return 0;
100
-}
41
+MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
42
+MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
43
+MODULE_FIRMWARE("amdgpu/picasso_ta.bin");
44
+MODULE_FIRMWARE("amdgpu/raven2_ta.bin");
45
+MODULE_FIRMWARE("amdgpu/raven_ta.bin");
101
46
 
102
47
 static int psp_v10_0_init_microcode(struct psp_context *psp)
103
48
 {
..
..
@@ -105,64 +50,72 @@
105
50
 	const char *chip_name;
106
51
 	char fw_name[30];
107
52
 	int err = 0;
108
-	const struct psp_firmware_header_v1_0 *hdr;
109
-
53
+	const struct ta_firmware_header_v1_0 *ta_hdr;
110
54
 	DRM_DEBUG("\n");
111
55
 
112
56
 	switch (adev->asic_type) {
113
57
 	case CHIP_RAVEN:
114
-		chip_name = "raven";
58
+		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
59
+			chip_name = "raven2";
60
+		else if (adev->apu_flags & AMD_APU_IS_PICASSO)
61
+			chip_name = "picasso";
62
+		else
63
+			chip_name = "raven";
115
64
 		break;
116
65
 	default: BUG();
117
66
 	}
118
67
 
119
-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
120
-	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
68
+	err = psp_init_asd_microcode(psp, chip_name);
121
69
 	if (err)
122
70
 		goto out;
123
71
 
124
-	err = amdgpu_ucode_validate(adev->psp.asd_fw);
125
-	if (err)
126
-		goto out;
72
+	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
73
+	err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
74
+	if (err) {
75
+		release_firmware(adev->psp.ta_fw);
76
+		adev->psp.ta_fw = NULL;
77
+		dev_info(adev->dev,
78
+			 "psp v10.0: Failed to load firmware \"%s\"\n",
79
+			 fw_name);
80
+	} else {
81
+		err = amdgpu_ucode_validate(adev->psp.ta_fw);
82
+		if (err)
83
+			goto out2;
127
84
 
128
-	hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
129
-	adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
130
-	adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
131
-	adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
132
-	adev->psp.asd_start_addr = (uint8_t *)hdr +
133
-				le32_to_cpu(hdr->header.ucode_array_offset_bytes);
85
+		ta_hdr = (const struct ta_firmware_header_v1_0 *)
86
+				 adev->psp.ta_fw->data;
87
+		adev->psp.ta_hdcp_ucode_version =
88
+			le32_to_cpu(ta_hdr->ta_hdcp_ucode_version);
89
+		adev->psp.ta_hdcp_ucode_size =
90
+			le32_to_cpu(ta_hdr->ta_hdcp_size_bytes);
91
+		adev->psp.ta_hdcp_start_addr =
92
+			(uint8_t *)ta_hdr +
93
+			le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
94
+
95
+		adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
96
+
97
+		adev->psp.ta_dtm_ucode_version =
98
+			le32_to_cpu(ta_hdr->ta_dtm_ucode_version);
99
+		adev->psp.ta_dtm_ucode_size =
100
+			le32_to_cpu(ta_hdr->ta_dtm_size_bytes);
101
+		adev->psp.ta_dtm_start_addr =
102
+			(uint8_t *)adev->psp.ta_hdcp_start_addr +
103
+			le32_to_cpu(ta_hdr->ta_dtm_offset_bytes);
104
+	}
134
105
 
135
106
 	return 0;
107
+
108
+out2:
109
+	release_firmware(adev->psp.ta_fw);
110
+	adev->psp.ta_fw = NULL;
136
111
 out:
137
112
 	if (err) {
138
113
 		dev_err(adev->dev,
139
114
 			"psp v10.0: Failed to load firmware \"%s\"\n",
140
115
 			fw_name);
141
-		release_firmware(adev->psp.asd_fw);
142
-		adev->psp.asd_fw = NULL;
143
116
 	}
144
117
 
145
118
 	return err;
146
-}
147
-
148
-static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
149
-				  struct psp_gfx_cmd_resp *cmd)
150
-{
151
-	int ret;
152
-	uint64_t fw_mem_mc_addr = ucode->mc_addr;
153
-
154
-	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
155
-
156
-	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
157
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
158
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
159
-	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
160
-
161
-	ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
162
-	if (ret)
163
-		DRM_ERROR("Unknown firmware type\n");
164
-
165
-	return ret;
166
119
 }
167
120
 
168
121
 static int psp_v10_0_ring_init(struct psp_context *psp,
..
..
@@ -227,11 +180,8 @@
227
180
 			       enum psp_ring_type ring_type)
228
181
 {
229
182
 	int ret = 0;
230
-	struct psp_ring *ring;
231
183
 	unsigned int psp_ring_reg = 0;
232
184
 	struct amdgpu_device *adev = psp->adev;
233
-
234
-	ring = &psp->km_ring;
235
185
 
236
186
 	/* Write the ring destroy command to C2PMSG_64 */
237
187
 	psp_ring_reg = 3 << 16;
..
..
@@ -265,193 +215,35 @@
265
215
 	return ret;
266
216
 }
267
217
 
268
-static int psp_v10_0_cmd_submit(struct psp_context *psp,
269
-				struct amdgpu_firmware_info *ucode,
270
-				uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
271
-				int index)
272
-{
273
-	unsigned int psp_write_ptr_reg = 0;
274
-	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
275
-	struct psp_ring *ring = &psp->km_ring;
276
-	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
277
-	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
278
-		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
279
-	struct amdgpu_device *adev = psp->adev;
280
-	uint32_t ring_size_dw = ring->ring_size / 4;
281
-	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
282
-
283
-	/* KM (GPCOM) prepare write pointer */
284
-	psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
285
-
286
-	/* Update KM RB frame pointer to new frame */
287
-	if ((psp_write_ptr_reg % ring_size_dw) == 0)
288
-		write_frame = ring_buffer_start;
289
-	else
290
-		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
291
-	/* Check invalid write_frame ptr address */
292
-	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
293
-		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
294
-			  ring_buffer_start, ring_buffer_end, write_frame);
295
-		DRM_ERROR("write_frame is pointing to address out of bounds\n");
296
-		return -EINVAL;
297
-	}
298
-
299
-	/* Initialize KM RB frame */
300
-	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
301
-
302
-	/* Update KM RB frame */
303
-	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
304
-	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
305
-	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
306
-	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
307
-	write_frame->fence_value = index;
308
-
309
-	/* Update the write Pointer in DWORDs */
310
-	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
311
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
312
-
313
-	return 0;
314
-}
315
-
316
-static int
317
-psp_v10_0_sram_map(struct amdgpu_device *adev,
318
-		   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
319
-		   unsigned int *sram_data_reg_offset,
320
-		   enum AMDGPU_UCODE_ID ucode_id)
321
-{
322
-	int ret = 0;
323
-
324
-	switch(ucode_id) {
325
-/* TODO: needs to confirm */
326
-#if 0
327
-	case AMDGPU_UCODE_ID_SMC:
328
-		*sram_offset = 0;
329
-		*sram_addr_reg_offset = 0;
330
-		*sram_data_reg_offset = 0;
331
-		break;
332
-#endif
333
-
334
-	case AMDGPU_UCODE_ID_CP_CE:
335
-		*sram_offset = 0x0;
336
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
337
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
338
-		break;
339
-
340
-	case AMDGPU_UCODE_ID_CP_PFP:
341
-		*sram_offset = 0x0;
342
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
343
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
344
-		break;
345
-
346
-	case AMDGPU_UCODE_ID_CP_ME:
347
-		*sram_offset = 0x0;
348
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
349
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
350
-		break;
351
-
352
-	case AMDGPU_UCODE_ID_CP_MEC1:
353
-		*sram_offset = 0x10000;
354
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
355
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
356
-		break;
357
-
358
-	case AMDGPU_UCODE_ID_CP_MEC2:
359
-		*sram_offset = 0x10000;
360
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
361
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
362
-		break;
363
-
364
-	case AMDGPU_UCODE_ID_RLC_G:
365
-		*sram_offset = 0x2000;
366
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
367
-		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
368
-		break;
369
-
370
-	case AMDGPU_UCODE_ID_SDMA0:
371
-		*sram_offset = 0x0;
372
-		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
373
-		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
374
-		break;
375
-
376
-/* TODO: needs to confirm */
377
-#if 0
378
-	case AMDGPU_UCODE_ID_SDMA1:
379
-		*sram_offset = ;
380
-		*sram_addr_reg_offset = ;
381
-		break;
382
-
383
-	case AMDGPU_UCODE_ID_UVD:
384
-		*sram_offset = ;
385
-		*sram_addr_reg_offset = ;
386
-		break;
387
-
388
-	case AMDGPU_UCODE_ID_VCE:
389
-		*sram_offset = ;
390
-		*sram_addr_reg_offset = ;
391
-		break;
392
-#endif
393
-
394
-	case AMDGPU_UCODE_ID_MAXIMUM:
395
-	default:
396
-		ret = -EINVAL;
397
-		break;
398
-	}
399
-
400
-	return ret;
401
-}
402
-
403
-static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
404
-					struct amdgpu_firmware_info *ucode,
405
-					enum AMDGPU_UCODE_ID ucode_type)
406
-{
407
-	int err = 0;
408
-	unsigned int fw_sram_reg_val = 0;
409
-	unsigned int fw_sram_addr_reg_offset = 0;
410
-	unsigned int fw_sram_data_reg_offset = 0;
411
-	unsigned int ucode_size;
412
-	uint32_t *ucode_mem = NULL;
413
-	struct amdgpu_device *adev = psp->adev;
414
-
415
-	err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
416
-				&fw_sram_data_reg_offset, ucode_type);
417
-	if (err)
418
-		return false;
419
-
420
-	WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
421
-
422
-	ucode_size = ucode->ucode_size;
423
-	ucode_mem = (uint32_t *)ucode->kaddr;
424
-	while (!ucode_size) {
425
-		fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
426
-
427
-		if (*ucode_mem != fw_sram_reg_val)
428
-			return false;
429
-
430
-		ucode_mem++;
431
-		/* 4 bytes */
432
-		ucode_size -= 4;
433
-	}
434
-
435
-	return true;
436
-}
437
-
438
-
439
218
 static int psp_v10_0_mode1_reset(struct psp_context *psp)
440
219
 {
441
220
 	DRM_INFO("psp mode 1 reset not supported now! \n");
442
221
 	return -EINVAL;
443
222
 }
444
223
 
224
+static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
225
+{
226
+	struct amdgpu_device *adev = psp->adev;
227
+
228
+	return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
229
+}
230
+
231
+static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
232
+{
233
+	struct amdgpu_device *adev = psp->adev;
234
+
235
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
236
+}
237
+
445
238
 static const struct psp_funcs psp_v10_0_funcs = {
446
239
 	.init_microcode = psp_v10_0_init_microcode,
447
-	.prep_cmd_buf = psp_v10_0_prep_cmd_buf,
448
240
 	.ring_init = psp_v10_0_ring_init,
449
241
 	.ring_create = psp_v10_0_ring_create,
450
242
 	.ring_stop = psp_v10_0_ring_stop,
451
243
 	.ring_destroy = psp_v10_0_ring_destroy,
452
-	.cmd_submit = psp_v10_0_cmd_submit,
453
-	.compare_sram_data = psp_v10_0_compare_sram_data,
454
244
 	.mode1_reset = psp_v10_0_mode1_reset,
245
+	.ring_get_wptr = psp_v10_0_ring_get_wptr,
246
+	.ring_set_wptr = psp_v10_0_ring_set_wptr,
455
247
 };
456
248
 
457
249
 void psp_v10_0_set_psp_funcs(struct psp_context *psp)