add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
..
..
@@ -37,7 +37,6 @@
37
37
 #include "gmc/gmc_8_2_sh_mask.h"
38
38
 #include "oss/oss_3_0_d.h"
39
39
 #include "oss/oss_3_0_sh_mask.h"
40
-#include "gca/gfx_8_0_sh_mask.h"
41
40
 #include "dce/dce_10_0_d.h"
42
41
 #include "dce/dce_10_0_sh_mask.h"
43
42
 #include "smu/smu_7_1_3_d.h"
..
..
@@ -516,12 +515,13 @@
516
515
 
517
516
 	/* wait until RCV_MSG become 3 */
518
517
 	if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
519
-		pr_err("failed to recieve FLR_CMPL\n");
518
+		pr_err("failed to receive FLR_CMPL\n");
520
519
 		return;
521
520
 	}
522
521
 
523
522
 	/* Trigger recovery due to world switch failure */
524
-	amdgpu_device_gpu_recover(adev, NULL, false);
523
+	if (amdgpu_device_should_recover_gpu(adev))
524
+		amdgpu_device_gpu_recover(adev, NULL);
525
525
 }
526
526
 
527
527
 static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
..
..
@@ -579,11 +579,11 @@
579
579
 {
580
580
 	int r;
581
581
 
582
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
582
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
583
583
 	if (r)
584
584
 		return r;
585
585
 
586
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
586
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
587
587
 	if (r) {
588
588
 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
589
589
 		return r;