.. | .. |
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26 | 26 | |
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27 | 27 | #define AI_MAILBOX_POLL_ACK_TIMEDOUT 500 |
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28 | 28 | #define AI_MAILBOX_POLL_MSG_TIMEDOUT 12000 |
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29 | | -#define AI_MAILBOX_POLL_FLR_TIMEDOUT 500 |
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| 29 | +#define AI_MAILBOX_POLL_FLR_TIMEDOUT 5000 |
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30 | 30 | |
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31 | 31 | enum idh_request { |
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32 | 32 | IDH_REQ_GPU_INIT_ACCESS = 1, |
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.. | .. |
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43 | 43 | IDH_READY_TO_ACCESS_GPU, |
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44 | 44 | IDH_FLR_NOTIFICATION, |
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45 | 45 | IDH_FLR_NOTIFICATION_CMPL, |
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46 | | - IDH_EVENT_MAX |
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| 46 | + IDH_SUCCESS, |
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| 47 | + IDH_FAIL, |
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| 48 | + IDH_QUERY_ALIVE, |
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| 49 | + |
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| 50 | + IDH_TEXT_MESSAGE = 255, |
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47 | 51 | }; |
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48 | 52 | |
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49 | 53 | extern const struct amdgpu_virt_ops xgpu_ai_virt_ops; |
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