add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
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@@ -29,7 +29,14 @@
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 static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
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-static void df_v1_7_init (struct amdgpu_device *adev)
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+static void df_v1_7_sw_init(struct amdgpu_device *adev)
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+{
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+	adev->df.hash_status.hash_64k = false;
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+	adev->df.hash_status.hash_2m = false;
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+	adev->df.hash_status.hash_1g = false;
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+}
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+
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+static void df_v1_7_sw_fini(struct amdgpu_device *adev)
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 {
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 }
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@@ -62,7 +69,7 @@
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 {
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 	int fb_channel_number;
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-	fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
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+	fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
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 	return df_v1_7_channel_number[fb_channel_number];
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 }
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@@ -73,7 +80,7 @@
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 	u32 tmp;
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 	/* Put DF on broadcast mode */
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-	adev->df_funcs->enable_broadcast_mode(adev, true);
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+	adev->df.funcs->enable_broadcast_mode(adev, true);
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 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
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 		tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
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@@ -88,7 +95,7 @@
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 	}
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 	/* Exit boradcast mode */
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-	adev->df_funcs->enable_broadcast_mode(adev, false);
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+	adev->df.funcs->enable_broadcast_mode(adev, false);
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 }
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 static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
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@@ -110,7 +117,8 @@
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 }
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 const struct amdgpu_df_funcs df_v1_7_funcs = {
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-	.init = df_v1_7_init,
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+	.sw_init = df_v1_7_sw_init,
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+	.sw_fini = df_v1_7_sw_fini,
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 	.enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
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 	.get_fb_channel_number = df_v1_7_get_fb_channel_number,
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 	.get_hbm_channel_number = df_v1_7_get_hbm_channel_number,