forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
....@@ -20,7 +20,12 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  *
2222  */
23
-#include <drm/drmP.h>
23
+
24
+#include <linux/pci.h>
25
+
26
+#include <drm/drm_fourcc.h>
27
+#include <drm/drm_vblank.h>
28
+
2429 #include "amdgpu.h"
2530 #include "amdgpu_pm.h"
2631 #include "amdgpu_i2c.h"
....@@ -30,6 +35,7 @@
3035 #include "atombios_encoders.h"
3136 #include "amdgpu_pll.h"
3237 #include "amdgpu_connectors.h"
38
+#include "amdgpu_display.h"
3339 
3440 #include "bif/bif_3_0_d.h"
3541 #include "bif/bif_3_0_sh_mask.h"
....@@ -185,10 +191,14 @@
185191 			       int crtc_id, u64 crtc_base, bool async)
186192 {
187193 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
194
+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
188195 
189196 	/* flip at hsync for async, default is vsync */
190197 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
191198 	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
199
+	/* update pitch */
200
+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
201
+	       fb->pitches[0] / fb->format->cpp[0]);
192202 	/* update the scanout addresses */
193203 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
194204 	       upper_32_bits(crtc_base));
....@@ -269,11 +279,13 @@
269279  */
270280 static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
271281 {
272
-	struct drm_device *dev = adev->ddev;
282
+	struct drm_device *dev = adev_to_drm(adev);
273283 	struct drm_connector *connector;
284
+	struct drm_connector_list_iter iter;
274285 	u32 tmp;
275286 
276
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
287
+	drm_connector_list_iter_begin(dev, &iter);
288
+	drm_for_each_connector_iter(connector, &iter) {
277289 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
278290 
279291 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -299,7 +311,7 @@
299311 		dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
300312 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
301313 	}
302
-
314
+	drm_connector_list_iter_end(&iter);
303315 }
304316 
305317 /**
....@@ -312,11 +324,13 @@
312324  */
313325 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
314326 {
315
-	struct drm_device *dev = adev->ddev;
327
+	struct drm_device *dev = adev_to_drm(adev);
316328 	struct drm_connector *connector;
329
+	struct drm_connector_list_iter iter;
317330 	u32 tmp;
318331 
319
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332
+	drm_connector_list_iter_begin(dev, &iter);
333
+	drm_for_each_connector_iter(connector, &iter) {
320334 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
321335 
322336 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -328,6 +342,7 @@
328342 
329343 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
330344 	}
345
+	drm_connector_list_iter_end(&iter);
331346 }
332347 
333348 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
....@@ -386,7 +401,7 @@
386401 {
387402 
388403 	struct drm_device *dev = encoder->dev;
389
-	struct amdgpu_device *adev = dev->dev_private;
404
+	struct amdgpu_device *adev = drm_to_adev(dev);
390405 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
391406 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
392407 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
....@@ -1099,7 +1114,7 @@
10991114 
11001115 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
11011116 {
1102
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1117
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
11031118 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
11041119 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
11051120 
....@@ -1114,20 +1129,24 @@
11141129 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
11151130 						struct drm_display_mode *mode)
11161131 {
1117
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1132
+	struct drm_device *dev = encoder->dev;
1133
+	struct amdgpu_device *adev = drm_to_adev(dev);
11181134 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
11191135 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
11201136 	struct drm_connector *connector;
1137
+	struct drm_connector_list_iter iter;
11211138 	struct amdgpu_connector *amdgpu_connector = NULL;
11221139 	int interlace = 0;
11231140 	u32 tmp;
11241141 
1125
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1142
+	drm_connector_list_iter_begin(dev, &iter);
1143
+	drm_for_each_connector_iter(connector, &iter) {
11261144 		if (connector->encoder == encoder) {
11271145 			amdgpu_connector = to_amdgpu_connector(connector);
11281146 			break;
11291147 		}
11301148 	}
1149
+	drm_connector_list_iter_end(&iter);
11311150 
11321151 	if (!amdgpu_connector) {
11331152 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1154,21 +1173,25 @@
11541173 
11551174 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
11561175 {
1157
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1176
+	struct drm_device *dev = encoder->dev;
1177
+	struct amdgpu_device *adev = drm_to_adev(dev);
11581178 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
11591179 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
11601180 	struct drm_connector *connector;
1181
+	struct drm_connector_list_iter iter;
11611182 	struct amdgpu_connector *amdgpu_connector = NULL;
11621183 	u8 *sadb = NULL;
11631184 	int sad_count;
11641185 	u32 tmp;
11651186 
1166
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1187
+	drm_connector_list_iter_begin(dev, &iter);
1188
+	drm_for_each_connector_iter(connector, &iter) {
11671189 		if (connector->encoder == encoder) {
11681190 			amdgpu_connector = to_amdgpu_connector(connector);
11691191 			break;
11701192 		}
11711193 	}
1194
+	drm_connector_list_iter_end(&iter);
11721195 
11731196 	if (!amdgpu_connector) {
11741197 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1211,10 +1234,12 @@
12111234 
12121235 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
12131236 {
1214
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1237
+	struct drm_device *dev = encoder->dev;
1238
+	struct amdgpu_device *adev = drm_to_adev(dev);
12151239 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12161240 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12171241 	struct drm_connector *connector;
1242
+	struct drm_connector_list_iter iter;
12181243 	struct amdgpu_connector *amdgpu_connector = NULL;
12191244 	struct cea_sad *sads;
12201245 	int i, sad_count;
....@@ -1234,12 +1259,14 @@
12341259 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
12351260 	};
12361261 
1237
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1262
+	drm_connector_list_iter_begin(dev, &iter);
1263
+	drm_for_each_connector_iter(connector, &iter) {
12381264 		if (connector->encoder == encoder) {
12391265 			amdgpu_connector = to_amdgpu_connector(connector);
12401266 			break;
12411267 		}
12421268 	}
1269
+	drm_connector_list_iter_end(&iter);
12431270 
12441271 	if (!amdgpu_connector) {
12451272 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1247,10 +1274,10 @@
12471274 	}
12481275 
12491276 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1250
-	if (sad_count <= 0) {
1277
+	if (sad_count < 0)
12511278 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1279
+	if (sad_count <= 0)
12521280 		return;
1253
-	}
12541281 
12551282 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
12561283 		u32 tmp = 0;
....@@ -1365,7 +1392,7 @@
13651392 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
13661393 {
13671394 	struct drm_device *dev = encoder->dev;
1368
-	struct amdgpu_device *adev = dev->dev_private;
1395
+	struct amdgpu_device *adev = drm_to_adev(dev);
13691396 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
13701397 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
13711398 	u32 tmp;
....@@ -1381,7 +1408,7 @@
13811408 				   uint32_t clock, int bpc)
13821409 {
13831410 	struct drm_device *dev = encoder->dev;
1384
-	struct amdgpu_device *adev = dev->dev_private;
1411
+	struct amdgpu_device *adev = drm_to_adev(dev);
13851412 	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
13861413 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
13871414 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
....@@ -1419,9 +1446,10 @@
14191446 					       struct drm_display_mode *mode)
14201447 {
14211448 	struct drm_device *dev = encoder->dev;
1422
-	struct amdgpu_device *adev = dev->dev_private;
1449
+	struct amdgpu_device *adev = drm_to_adev(dev);
14231450 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14241451 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1452
+	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
14251453 	struct hdmi_avi_infoframe frame;
14261454 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
14271455 	uint8_t *payload = buffer + 3;
....@@ -1429,7 +1457,7 @@
14291457 	ssize_t err;
14301458 	u32 tmp;
14311459 
1432
-	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1460
+	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
14331461 	if (err < 0) {
14341462 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
14351463 		return;
....@@ -1460,7 +1488,7 @@
14601488 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
14611489 {
14621490 	struct drm_device *dev = encoder->dev;
1463
-	struct amdgpu_device *adev = dev->dev_private;
1491
+	struct amdgpu_device *adev = drm_to_adev(dev);
14641492 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
14651493 	int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
14661494 	u32 tmp;
....@@ -1494,7 +1522,7 @@
14941522 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
14951523 {
14961524 	struct drm_device *dev = encoder->dev;
1497
-	struct amdgpu_device *adev = dev->dev_private;
1525
+	struct amdgpu_device *adev = drm_to_adev(dev);
14981526 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14991527 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15001528 	u32 tmp;
....@@ -1538,7 +1566,7 @@
15381566 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
15391567 {
15401568 	struct drm_device *dev = encoder->dev;
1541
-	struct amdgpu_device *adev = dev->dev_private;
1569
+	struct amdgpu_device *adev = drm_to_adev(dev);
15421570 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15431571 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15441572 	u32 tmp;
....@@ -1551,7 +1579,7 @@
15511579 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
15521580 {
15531581 	struct drm_device *dev = encoder->dev;
1554
-	struct amdgpu_device *adev = dev->dev_private;
1582
+	struct amdgpu_device *adev = drm_to_adev(dev);
15551583 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15561584 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15571585 	u32 tmp;
....@@ -1588,7 +1616,7 @@
15881616 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
15891617 {
15901618 	struct drm_device *dev = encoder->dev;
1591
-	struct amdgpu_device *adev = dev->dev_private;
1619
+	struct amdgpu_device *adev = drm_to_adev(dev);
15921620 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15931621 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15941622 	u32 tmp;
....@@ -1617,10 +1645,11 @@
16171645 				  struct drm_display_mode *mode)
16181646 {
16191647 	struct drm_device *dev = encoder->dev;
1620
-	struct amdgpu_device *adev = dev->dev_private;
1648
+	struct amdgpu_device *adev = drm_to_adev(dev);
16211649 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
16221650 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
16231651 	struct drm_connector *connector;
1652
+	struct drm_connector_list_iter iter;
16241653 	struct amdgpu_connector *amdgpu_connector = NULL;
16251654 	int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
16261655 	int bpc = 8;
....@@ -1628,12 +1657,14 @@
16281657 	if (!dig || !dig->afmt)
16291658 		return;
16301659 
1631
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1660
+	drm_connector_list_iter_begin(dev, &iter);
1661
+	drm_for_each_connector_iter(connector, &iter) {
16321662 		if (connector->encoder == encoder) {
16331663 			amdgpu_connector = to_amdgpu_connector(connector);
16341664 			break;
16351665 		}
16361666 	}
1667
+	drm_connector_list_iter_end(&iter);
16371668 
16381669 	if (!amdgpu_connector) {
16391670 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1683,7 +1714,7 @@
16831714 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
16841715 {
16851716 	struct drm_device *dev = encoder->dev;
1686
-	struct amdgpu_device *adev = dev->dev_private;
1717
+	struct amdgpu_device *adev = drm_to_adev(dev);
16871718 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
16881719 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
16891720 
....@@ -1757,7 +1788,7 @@
17571788 {
17581789 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17591790 	struct drm_device *dev = crtc->dev;
1760
-	struct amdgpu_device *adev = dev->dev_private;
1791
+	struct amdgpu_device *adev = drm_to_adev(dev);
17611792 	u32 vga_control;
17621793 
17631794 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
....@@ -1768,7 +1799,7 @@
17681799 {
17691800 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17701801 	struct drm_device *dev = crtc->dev;
1771
-	struct amdgpu_device *adev = dev->dev_private;
1802
+	struct amdgpu_device *adev = drm_to_adev(dev);
17721803 
17731804 	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
17741805 }
....@@ -1779,7 +1810,7 @@
17791810 {
17801811 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17811812 	struct drm_device *dev = crtc->dev;
1782
-	struct amdgpu_device *adev = dev->dev_private;
1813
+	struct amdgpu_device *adev = drm_to_adev(dev);
17831814 	struct drm_framebuffer *target_fb;
17841815 	struct drm_gem_object *obj;
17851816 	struct amdgpu_bo *abo;
....@@ -1887,6 +1918,16 @@
18871918 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
18881919 		bypass_lut = true;
18891920 		break;
1921
+	case DRM_FORMAT_XBGR8888:
1922
+	case DRM_FORMAT_ABGR8888:
1923
+		fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1924
+			     GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1925
+		fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) |
1926
+			   GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R));
1927
+#ifdef __BIG_ENDIAN
1928
+		fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1929
+#endif
1930
+		break;
18901931 	default:
18911932 		DRM_ERROR("Unsupported screen format %s\n",
18921933 		          drm_get_format_name(target_fb->format->format, &format_name));
....@@ -1992,7 +2033,7 @@
19922033 				    struct drm_display_mode *mode)
19932034 {
19942035 	struct drm_device *dev = crtc->dev;
1995
-	struct amdgpu_device *adev = dev->dev_private;
2036
+	struct amdgpu_device *adev = drm_to_adev(dev);
19962037 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
19972038 
19982039 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
....@@ -2007,7 +2048,7 @@
20072048 
20082049 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
20092050 	struct drm_device *dev = crtc->dev;
2010
-	struct amdgpu_device *adev = dev->dev_private;
2051
+	struct amdgpu_device *adev = drm_to_adev(dev);
20112052 	u16 *r, *g, *b;
20122053 	int i;
20132054 
....@@ -2107,7 +2148,7 @@
21072148 {
21082149 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
21092150 	struct drm_device *dev = crtc->dev;
2110
-	struct amdgpu_device *adev = dev->dev_private;
2151
+	struct amdgpu_device *adev = drm_to_adev(dev);
21112152 	u32 pll_in_use;
21122153 	int pll;
21132154 
....@@ -2136,7 +2177,7 @@
21362177 
21372178 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
21382179 {
2139
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2180
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21402181 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
21412182 	uint32_t cur_lock;
21422183 
....@@ -2151,11 +2192,11 @@
21512192 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
21522193 {
21532194 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2154
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2195
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21552196 
2156
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2157
-		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2158
-		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2197
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2198
+	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2199
+	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
21592200 
21602201 
21612202 }
....@@ -2163,17 +2204,17 @@
21632204 static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
21642205 {
21652206 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2166
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2207
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21672208 
21682209 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
21692210 	       upper_32_bits(amdgpu_crtc->cursor_addr));
21702211 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
21712212 	       lower_32_bits(amdgpu_crtc->cursor_addr));
21722213 
2173
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2174
-		   CUR_CONTROL__CURSOR_EN_MASK |
2175
-		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2176
-		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2214
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2215
+	       CUR_CONTROL__CURSOR_EN_MASK |
2216
+	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2217
+	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
21772218 
21782219 }
21792220 
....@@ -2181,7 +2222,7 @@
21812222 				       int x, int y)
21822223 {
21832224 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2184
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2225
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
21852226 	int xorigin = 0, yorigin = 0;
21862227 
21872228 	int w = amdgpu_crtc->cursor_width;
....@@ -2258,7 +2299,7 @@
22582299 	aobj = gem_to_amdgpu_bo(obj);
22592300 	ret = amdgpu_bo_reserve(aobj, false);
22602301 	if (ret != 0) {
2261
-		drm_gem_object_put_unlocked(obj);
2302
+		drm_gem_object_put(obj);
22622303 		return ret;
22632304 	}
22642305 
....@@ -2266,7 +2307,7 @@
22662307 	amdgpu_bo_unreserve(aobj);
22672308 	if (ret) {
22682309 		DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2269
-		drm_gem_object_put_unlocked(obj);
2310
+		drm_gem_object_put(obj);
22702311 		return ret;
22712312 	}
22722313 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
....@@ -2301,7 +2342,7 @@
23012342 			amdgpu_bo_unpin(aobj);
23022343 			amdgpu_bo_unreserve(aobj);
23032344 		}
2304
-		drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2345
+		drm_gem_object_put(amdgpu_crtc->cursor_bo);
23052346 	}
23062347 
23072348 	amdgpu_crtc->cursor_bo = obj;
....@@ -2347,12 +2388,16 @@
23472388 	.set_config = amdgpu_display_crtc_set_config,
23482389 	.destroy = dce_v6_0_crtc_destroy,
23492390 	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2391
+	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2392
+	.enable_vblank = amdgpu_enable_vblank_kms,
2393
+	.disable_vblank = amdgpu_disable_vblank_kms,
2394
+	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
23502395 };
23512396 
23522397 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
23532398 {
23542399 	struct drm_device *dev = crtc->dev;
2355
-	struct amdgpu_device *adev = dev->dev_private;
2400
+	struct amdgpu_device *adev = drm_to_adev(dev);
23562401 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
23572402 	unsigned type;
23582403 
....@@ -2402,7 +2447,7 @@
24022447 
24032448 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
24042449 	struct drm_device *dev = crtc->dev;
2405
-	struct amdgpu_device *adev = dev->dev_private;
2450
+	struct amdgpu_device *adev = drm_to_adev(dev);
24062451 	struct amdgpu_atom_ss ss;
24072452 	int i;
24082453 
....@@ -2534,6 +2579,7 @@
25342579 	.prepare = dce_v6_0_crtc_prepare,
25352580 	.commit = dce_v6_0_crtc_commit,
25362581 	.disable = dce_v6_0_crtc_disable,
2582
+	.get_scanout_position = amdgpu_crtc_get_scanout_position,
25372583 };
25382584 
25392585 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
....@@ -2545,7 +2591,7 @@
25452591 	if (amdgpu_crtc == NULL)
25462592 		return -ENOMEM;
25472593 
2548
-	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2594
+	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
25492595 
25502596 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
25512597 	amdgpu_crtc->crtc_id = index;
....@@ -2553,8 +2599,8 @@
25532599 
25542600 	amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
25552601 	amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2556
-	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2557
-	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2602
+	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2603
+	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
25582604 
25592605 	amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
25602606 
....@@ -2605,38 +2651,38 @@
26052651 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
26062652 
26072653 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2608
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2654
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
26092655 		if (r)
26102656 			return r;
26112657 	}
26122658 
26132659 	for (i = 8; i < 20; i += 2) {
2614
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2660
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
26152661 		if (r)
26162662 			return r;
26172663 	}
26182664 
26192665 	/* HPD hotplug */
2620
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2666
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
26212667 	if (r)
26222668 		return r;
26232669 
26242670 	adev->mode_info.mode_config_initialized = true;
26252671 
2626
-	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2627
-	adev->ddev->mode_config.async_page_flip = true;
2628
-	adev->ddev->mode_config.max_width = 16384;
2629
-	adev->ddev->mode_config.max_height = 16384;
2630
-	adev->ddev->mode_config.preferred_depth = 24;
2631
-	adev->ddev->mode_config.prefer_shadow = 1;
2632
-	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2672
+	adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2673
+	adev_to_drm(adev)->mode_config.async_page_flip = true;
2674
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2675
+	adev_to_drm(adev)->mode_config.max_height = 16384;
2676
+	adev_to_drm(adev)->mode_config.preferred_depth = 24;
2677
+	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2678
+	adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
26332679 
26342680 	r = amdgpu_display_modeset_create_props(adev);
26352681 	if (r)
26362682 		return r;
26372683 
2638
-	adev->ddev->mode_config.max_width = 16384;
2639
-	adev->ddev->mode_config.max_height = 16384;
2684
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2685
+	adev_to_drm(adev)->mode_config.max_height = 16384;
26402686 
26412687 	/* allocate crtcs */
26422688 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
....@@ -2647,7 +2693,7 @@
26472693 
26482694 	ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
26492695 	if (ret)
2650
-		amdgpu_display_print_display_setup(adev->ddev);
2696
+		amdgpu_display_print_display_setup(adev_to_drm(adev));
26512697 	else
26522698 		return -EINVAL;
26532699 
....@@ -2660,7 +2706,7 @@
26602706 	if (r)
26612707 		return r;
26622708 
2663
-	drm_kms_helper_poll_init(adev->ddev);
2709
+	drm_kms_helper_poll_init(adev_to_drm(adev));
26642710 
26652711 	return r;
26662712 }
....@@ -2671,12 +2717,12 @@
26712717 
26722718 	kfree(adev->mode_info.bios_hardcoded_edid);
26732719 
2674
-	drm_kms_helper_poll_fini(adev->ddev);
2720
+	drm_kms_helper_poll_fini(adev_to_drm(adev));
26752721 
26762722 	dce_v6_0_audio_fini(adev);
26772723 	dce_v6_0_afmt_fini(adev);
26782724 
2679
-	drm_mode_config_cleanup(adev->ddev);
2725
+	drm_mode_config_cleanup(adev_to_drm(adev));
26802726 	adev->mode_info.mode_config_initialized = false;
26812727 
26822728 	return 0;
....@@ -2921,7 +2967,7 @@
29212967 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
29222968 
29232969 		if (amdgpu_irq_enabled(adev, source, irq_type)) {
2924
-			drm_handle_vblank(adev->ddev, crtc);
2970
+			drm_handle_vblank(adev_to_drm(adev), crtc);
29252971 		}
29262972 		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
29272973 		break;
....@@ -2968,7 +3014,7 @@
29683014 				 struct amdgpu_irq_src *source,
29693015 				 struct amdgpu_iv_entry *entry)
29703016 {
2971
-		unsigned long flags;
3017
+	unsigned long flags;
29723018 	unsigned crtc_id;
29733019 	struct amdgpu_crtc *amdgpu_crtc;
29743020 	struct amdgpu_flip_work *works;
....@@ -2990,14 +3036,14 @@
29903036 	if (amdgpu_crtc == NULL)
29913037 		return 0;
29923038 
2993
-	spin_lock_irqsave(&adev->ddev->event_lock, flags);
3039
+	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
29943040 	works = amdgpu_crtc->pflip_works;
29953041 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
29963042 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
29973043 						"AMDGPU_FLIP_SUBMITTED(%d)\n",
29983044 						amdgpu_crtc->pflip_status,
29993045 						AMDGPU_FLIP_SUBMITTED);
3000
-		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3046
+		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
30013047 		return 0;
30023048 	}
30033049 
....@@ -3009,7 +3055,7 @@
30093055 	if (works->event)
30103056 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
30113057 
3012
-	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3058
+	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
30133059 
30143060 	drm_crtc_vblank_put(&amdgpu_crtc->base);
30153061 	schedule_work(&works->unpin_work);
....@@ -3100,7 +3146,7 @@
31003146 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
31013147 {
31023148 
3103
-	struct amdgpu_device *adev = encoder->dev->dev_private;
3149
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
31043150 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
31053151 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
31063152 
....@@ -3141,7 +3187,7 @@
31413187 {
31423188 
31433189 	struct drm_device *dev = encoder->dev;
3144
-	struct amdgpu_device *adev = dev->dev_private;
3190
+	struct amdgpu_device *adev = drm_to_adev(dev);
31453191 
31463192 	/* need to call this here as we need the crtc set up */
31473193 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
....@@ -3251,7 +3297,7 @@
32513297 				 uint32_t supported_device,
32523298 				 u16 caps)
32533299 {
3254
-	struct drm_device *dev = adev->ddev;
3300
+	struct drm_device *dev = adev_to_drm(adev);
32553301 	struct drm_encoder *encoder;
32563302 	struct amdgpu_encoder *amdgpu_encoder;
32573303 
....@@ -3365,8 +3411,7 @@
33653411 
33663412 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
33673413 {
3368
-	if (adev->mode_info.funcs == NULL)
3369
-		adev->mode_info.funcs = &dce_v6_0_display_funcs;
3414
+	adev->mode_info.funcs = &dce_v6_0_display_funcs;
33703415 }
33713416 
33723417 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {