forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
....@@ -20,7 +20,10 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  *
2222  */
23
-#include <drm/drmP.h>
23
+
24
+#include <drm/drm_fourcc.h>
25
+#include <drm/drm_vblank.h>
26
+
2427 #include "amdgpu.h"
2528 #include "amdgpu_pm.h"
2629 #include "amdgpu_i2c.h"
....@@ -31,6 +34,7 @@
3134 #include "atombios_encoders.h"
3235 #include "amdgpu_pll.h"
3336 #include "amdgpu_connectors.h"
37
+#include "amdgpu_display.h"
3438 #include "dce_v11_0.h"
3539 
3640 #include "dce/dce_11_0_d.h"
....@@ -250,6 +254,7 @@
250254 				int crtc_id, u64 crtc_base, bool async)
251255 {
252256 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
257
+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
253258 	u32 tmp;
254259 
255260 	/* flip immediate for async, default is vsync */
....@@ -257,6 +262,9 @@
257262 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
258263 			    GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
259264 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
265
+	/* update pitch */
266
+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
267
+	       fb->pitches[0] / fb->format->cpp[0]);
260268 	/* update the scanout addresses */
261269 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
262270 	       upper_32_bits(crtc_base));
....@@ -338,11 +346,13 @@
338346  */
339347 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
340348 {
341
-	struct drm_device *dev = adev->ddev;
349
+	struct drm_device *dev = adev_to_drm(adev);
342350 	struct drm_connector *connector;
351
+	struct drm_connector_list_iter iter;
343352 	u32 tmp;
344353 
345
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
354
+	drm_connector_list_iter_begin(dev, &iter);
355
+	drm_for_each_connector_iter(connector, &iter) {
346356 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
347357 
348358 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -377,6 +387,7 @@
377387 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
378388 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
379389 	}
390
+	drm_connector_list_iter_end(&iter);
380391 }
381392 
382393 /**
....@@ -389,11 +400,13 @@
389400  */
390401 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
391402 {
392
-	struct drm_device *dev = adev->ddev;
403
+	struct drm_device *dev = adev_to_drm(adev);
393404 	struct drm_connector *connector;
405
+	struct drm_connector_list_iter iter;
394406 	u32 tmp;
395407 
396
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
408
+	drm_connector_list_iter_begin(dev, &iter);
409
+	drm_for_each_connector_iter(connector, &iter) {
397410 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
398411 
399412 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -405,6 +418,7 @@
405418 
406419 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
407420 	}
421
+	drm_connector_list_iter_end(&iter);
408422 }
409423 
410424 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
....@@ -516,7 +530,7 @@
516530 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
517531 {
518532 	struct drm_device *dev = encoder->dev;
519
-	struct amdgpu_device *adev = dev->dev_private;
533
+	struct amdgpu_device *adev = drm_to_adev(dev);
520534 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
521535 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
522536 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
....@@ -1221,7 +1235,7 @@
12211235 
12221236 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
12231237 {
1224
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1238
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
12251239 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12261240 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12271241 	u32 tmp;
....@@ -1237,10 +1251,12 @@
12371251 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
12381252 						struct drm_display_mode *mode)
12391253 {
1240
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1254
+	struct drm_device *dev = encoder->dev;
1255
+	struct amdgpu_device *adev = drm_to_adev(dev);
12411256 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12421257 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12431258 	struct drm_connector *connector;
1259
+	struct drm_connector_list_iter iter;
12441260 	struct amdgpu_connector *amdgpu_connector = NULL;
12451261 	u32 tmp;
12461262 	int interlace = 0;
....@@ -1248,12 +1264,14 @@
12481264 	if (!dig || !dig->afmt || !dig->afmt->pin)
12491265 		return;
12501266 
1251
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1267
+	drm_connector_list_iter_begin(dev, &iter);
1268
+	drm_for_each_connector_iter(connector, &iter) {
12521269 		if (connector->encoder == encoder) {
12531270 			amdgpu_connector = to_amdgpu_connector(connector);
12541271 			break;
12551272 		}
12561273 	}
1274
+	drm_connector_list_iter_end(&iter);
12571275 
12581276 	if (!amdgpu_connector) {
12591277 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1279,10 +1297,12 @@
12791297 
12801298 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
12811299 {
1282
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1300
+	struct drm_device *dev = encoder->dev;
1301
+	struct amdgpu_device *adev = drm_to_adev(dev);
12831302 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12841303 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12851304 	struct drm_connector *connector;
1305
+	struct drm_connector_list_iter iter;
12861306 	struct amdgpu_connector *amdgpu_connector = NULL;
12871307 	u32 tmp;
12881308 	u8 *sadb = NULL;
....@@ -1291,12 +1311,14 @@
12911311 	if (!dig || !dig->afmt || !dig->afmt->pin)
12921312 		return;
12931313 
1294
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1314
+	drm_connector_list_iter_begin(dev, &iter);
1315
+	drm_for_each_connector_iter(connector, &iter) {
12951316 		if (connector->encoder == encoder) {
12961317 			amdgpu_connector = to_amdgpu_connector(connector);
12971318 			break;
12981319 		}
12991320 	}
1321
+	drm_connector_list_iter_end(&iter);
13001322 
13011323 	if (!amdgpu_connector) {
13021324 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1331,10 +1353,12 @@
13311353 
13321354 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
13331355 {
1334
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1356
+	struct drm_device *dev = encoder->dev;
1357
+	struct amdgpu_device *adev = drm_to_adev(dev);
13351358 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
13361359 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
13371360 	struct drm_connector *connector;
1361
+	struct drm_connector_list_iter iter;
13381362 	struct amdgpu_connector *amdgpu_connector = NULL;
13391363 	struct cea_sad *sads;
13401364 	int i, sad_count;
....@@ -1357,12 +1381,14 @@
13571381 	if (!dig || !dig->afmt || !dig->afmt->pin)
13581382 		return;
13591383 
1360
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1384
+	drm_connector_list_iter_begin(dev, &iter);
1385
+	drm_for_each_connector_iter(connector, &iter) {
13611386 		if (connector->encoder == encoder) {
13621387 			amdgpu_connector = to_amdgpu_connector(connector);
13631388 			break;
13641389 		}
13651390 	}
1391
+	drm_connector_list_iter_end(&iter);
13661392 
13671393 	if (!amdgpu_connector) {
13681394 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1370,10 +1396,10 @@
13701396 	}
13711397 
13721398 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1373
-	if (sad_count <= 0) {
1399
+	if (sad_count < 0)
13741400 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1401
+	if (sad_count <= 0)
13751402 		return;
1376
-	}
13771403 	BUG_ON(!sads);
13781404 
13791405 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
....@@ -1499,7 +1525,7 @@
14991525 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
15001526 {
15011527 	struct drm_device *dev = encoder->dev;
1502
-	struct amdgpu_device *adev = dev->dev_private;
1528
+	struct amdgpu_device *adev = drm_to_adev(dev);
15031529 	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
15041530 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15051531 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
....@@ -1535,7 +1561,7 @@
15351561 					       void *buffer, size_t size)
15361562 {
15371563 	struct drm_device *dev = encoder->dev;
1538
-	struct amdgpu_device *adev = dev->dev_private;
1564
+	struct amdgpu_device *adev = drm_to_adev(dev);
15391565 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15401566 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15411567 	uint8_t *frame = buffer + 3;
....@@ -1554,7 +1580,7 @@
15541580 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
15551581 {
15561582 	struct drm_device *dev = encoder->dev;
1557
-	struct amdgpu_device *adev = dev->dev_private;
1583
+	struct amdgpu_device *adev = drm_to_adev(dev);
15581584 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15591585 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15601586 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
....@@ -1585,7 +1611,7 @@
15851611 				  struct drm_display_mode *mode)
15861612 {
15871613 	struct drm_device *dev = encoder->dev;
1588
-	struct amdgpu_device *adev = dev->dev_private;
1614
+	struct amdgpu_device *adev = drm_to_adev(dev);
15891615 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15901616 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15911617 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
....@@ -1723,7 +1749,7 @@
17231749 	dce_v11_0_audio_write_sad_regs(encoder);
17241750 	dce_v11_0_audio_write_latency_fields(encoder, mode);
17251751 
1726
-	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1752
+	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
17271753 	if (err < 0) {
17281754 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
17291755 		return;
....@@ -1765,7 +1791,7 @@
17651791 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
17661792 {
17671793 	struct drm_device *dev = encoder->dev;
1768
-	struct amdgpu_device *adev = dev->dev_private;
1794
+	struct amdgpu_device *adev = drm_to_adev(dev);
17691795 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
17701796 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
17711797 
....@@ -1838,7 +1864,7 @@
18381864 {
18391865 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
18401866 	struct drm_device *dev = crtc->dev;
1841
-	struct amdgpu_device *adev = dev->dev_private;
1867
+	struct amdgpu_device *adev = drm_to_adev(dev);
18421868 	u32 vga_control;
18431869 
18441870 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
....@@ -1852,7 +1878,7 @@
18521878 {
18531879 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
18541880 	struct drm_device *dev = crtc->dev;
1855
-	struct amdgpu_device *adev = dev->dev_private;
1881
+	struct amdgpu_device *adev = drm_to_adev(dev);
18561882 
18571883 	if (enable)
18581884 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
....@@ -1866,7 +1892,7 @@
18661892 {
18671893 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
18681894 	struct drm_device *dev = crtc->dev;
1869
-	struct amdgpu_device *adev = dev->dev_private;
1895
+	struct amdgpu_device *adev = drm_to_adev(dev);
18701896 	struct drm_framebuffer *target_fb;
18711897 	struct drm_gem_object *obj;
18721898 	struct amdgpu_bo *abo;
....@@ -1984,6 +2010,17 @@
19842010 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
19852011 		bypass_lut = true;
19862012 		break;
2013
+	case DRM_FORMAT_XBGR8888:
2014
+	case DRM_FORMAT_ABGR8888:
2015
+		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2016
+		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2017
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
2018
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
2019
+#ifdef __BIG_ENDIAN
2020
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2021
+					ENDIAN_8IN32);
2022
+#endif
2023
+		break;
19872024 	default:
19882025 		DRM_ERROR("Unsupported screen format %s\n",
19892026 		          drm_get_format_name(target_fb->format->format, &format_name));
....@@ -2100,7 +2137,7 @@
21002137 				     struct drm_display_mode *mode)
21012138 {
21022139 	struct drm_device *dev = crtc->dev;
2103
-	struct amdgpu_device *adev = dev->dev_private;
2140
+	struct amdgpu_device *adev = drm_to_adev(dev);
21042141 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
21052142 	u32 tmp;
21062143 
....@@ -2116,7 +2153,7 @@
21162153 {
21172154 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
21182155 	struct drm_device *dev = crtc->dev;
2119
-	struct amdgpu_device *adev = dev->dev_private;
2156
+	struct amdgpu_device *adev = drm_to_adev(dev);
21202157 	u16 *r, *g, *b;
21212158 	int i;
21222159 	u32 tmp;
....@@ -2246,7 +2283,7 @@
22462283 {
22472284 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
22482285 	struct drm_device *dev = crtc->dev;
2249
-	struct amdgpu_device *adev = dev->dev_private;
2286
+	struct amdgpu_device *adev = drm_to_adev(dev);
22502287 	u32 pll_in_use;
22512288 	int pll;
22522289 
....@@ -2305,7 +2342,7 @@
23052342 
23062343 	/* XXX need to determine what plls are available on each DCE11 part */
23072344 	pll_in_use = amdgpu_pll_get_use_mask(crtc);
2308
-	if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2345
+	if (adev->flags & AMD_IS_APU) {
23092346 		if (!(pll_in_use & (1 << ATOM_PPLL1)))
23102347 			return ATOM_PPLL1;
23112348 		if (!(pll_in_use & (1 << ATOM_PPLL0)))
....@@ -2327,7 +2364,7 @@
23272364 
23282365 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
23292366 {
2330
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2367
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
23312368 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
23322369 	uint32_t cur_lock;
23332370 
....@@ -2342,18 +2379,18 @@
23422379 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
23432380 {
23442381 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2345
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2382
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
23462383 	u32 tmp;
23472384 
2348
-	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2385
+	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
23492386 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2350
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2387
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
23512388 }
23522389 
23532390 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
23542391 {
23552392 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2356
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2393
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
23572394 	u32 tmp;
23582395 
23592396 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
....@@ -2361,17 +2398,17 @@
23612398 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
23622399 	       lower_32_bits(amdgpu_crtc->cursor_addr));
23632400 
2364
-	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2401
+	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
23652402 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
23662403 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2367
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2404
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
23682405 }
23692406 
23702407 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
23712408 					int x, int y)
23722409 {
23732410 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2374
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2411
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
23752412 	int xorigin = 0, yorigin = 0;
23762413 
23772414 	amdgpu_crtc->cursor_x = x;
....@@ -2446,7 +2483,7 @@
24462483 	aobj = gem_to_amdgpu_bo(obj);
24472484 	ret = amdgpu_bo_reserve(aobj, false);
24482485 	if (ret != 0) {
2449
-		drm_gem_object_put_unlocked(obj);
2486
+		drm_gem_object_put(obj);
24502487 		return ret;
24512488 	}
24522489 
....@@ -2454,7 +2491,7 @@
24542491 	amdgpu_bo_unreserve(aobj);
24552492 	if (ret) {
24562493 		DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2457
-		drm_gem_object_put_unlocked(obj);
2494
+		drm_gem_object_put(obj);
24582495 		return ret;
24592496 	}
24602497 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
....@@ -2489,7 +2526,7 @@
24892526 			amdgpu_bo_unpin(aobj);
24902527 			amdgpu_bo_unreserve(aobj);
24912528 		}
2492
-		drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2529
+		drm_gem_object_put(amdgpu_crtc->cursor_bo);
24932530 	}
24942531 
24952532 	amdgpu_crtc->cursor_bo = obj;
....@@ -2536,12 +2573,16 @@
25362573 	.set_config = amdgpu_display_crtc_set_config,
25372574 	.destroy = dce_v11_0_crtc_destroy,
25382575 	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2576
+	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2577
+	.enable_vblank = amdgpu_enable_vblank_kms,
2578
+	.disable_vblank = amdgpu_disable_vblank_kms,
2579
+	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
25392580 };
25402581 
25412582 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
25422583 {
25432584 	struct drm_device *dev = crtc->dev;
2544
-	struct amdgpu_device *adev = dev->dev_private;
2585
+	struct amdgpu_device *adev = drm_to_adev(dev);
25452586 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
25462587 	unsigned type;
25472588 
....@@ -2595,7 +2636,7 @@
25952636 {
25962637 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
25972638 	struct drm_device *dev = crtc->dev;
2598
-	struct amdgpu_device *adev = dev->dev_private;
2639
+	struct amdgpu_device *adev = drm_to_adev(dev);
25992640 	struct amdgpu_atom_ss ss;
26002641 	int i;
26012642 
....@@ -2665,7 +2706,7 @@
26652706 {
26662707 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
26672708 	struct drm_device *dev = crtc->dev;
2668
-	struct amdgpu_device *adev = dev->dev_private;
2709
+	struct amdgpu_device *adev = drm_to_adev(dev);
26692710 
26702711 	if (!amdgpu_crtc->adjusted_clock)
26712712 		return -EINVAL;
....@@ -2756,6 +2797,7 @@
27562797 	.prepare = dce_v11_0_crtc_prepare,
27572798 	.commit = dce_v11_0_crtc_commit,
27582799 	.disable = dce_v11_0_crtc_disable,
2800
+	.get_scanout_position = amdgpu_crtc_get_scanout_position,
27592801 };
27602802 
27612803 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
....@@ -2767,7 +2809,7 @@
27672809 	if (amdgpu_crtc == NULL)
27682810 		return -ENOMEM;
27692811 
2770
-	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2812
+	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
27712813 
27722814 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
27732815 	amdgpu_crtc->crtc_id = index;
....@@ -2775,8 +2817,8 @@
27752817 
27762818 	amdgpu_crtc->max_cursor_width = 128;
27772819 	amdgpu_crtc->max_cursor_height = 128;
2778
-	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2779
-	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2820
+	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2821
+	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
27802822 
27812823 	switch (amdgpu_crtc->crtc_id) {
27822824 	case 0:
....@@ -2855,40 +2897,40 @@
28552897 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
28562898 
28572899 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2858
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2900
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
28592901 		if (r)
28602902 			return r;
28612903 	}
28622904 
28632905 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2864
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2906
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
28652907 		if (r)
28662908 			return r;
28672909 	}
28682910 
28692911 	/* HPD hotplug */
2870
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2912
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
28712913 	if (r)
28722914 		return r;
28732915 
2874
-	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2916
+	adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
28752917 
2876
-	adev->ddev->mode_config.async_page_flip = true;
2918
+	adev_to_drm(adev)->mode_config.async_page_flip = true;
28772919 
2878
-	adev->ddev->mode_config.max_width = 16384;
2879
-	adev->ddev->mode_config.max_height = 16384;
2920
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2921
+	adev_to_drm(adev)->mode_config.max_height = 16384;
28802922 
2881
-	adev->ddev->mode_config.preferred_depth = 24;
2882
-	adev->ddev->mode_config.prefer_shadow = 1;
2923
+	adev_to_drm(adev)->mode_config.preferred_depth = 24;
2924
+	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
28832925 
2884
-	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2926
+	adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
28852927 
28862928 	r = amdgpu_display_modeset_create_props(adev);
28872929 	if (r)
28882930 		return r;
28892931 
2890
-	adev->ddev->mode_config.max_width = 16384;
2891
-	adev->ddev->mode_config.max_height = 16384;
2932
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2933
+	adev_to_drm(adev)->mode_config.max_height = 16384;
28922934 
28932935 
28942936 	/* allocate crtcs */
....@@ -2899,7 +2941,7 @@
28992941 	}
29002942 
29012943 	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2902
-		amdgpu_display_print_display_setup(adev->ddev);
2944
+		amdgpu_display_print_display_setup(adev_to_drm(adev));
29032945 	else
29042946 		return -EINVAL;
29052947 
....@@ -2912,7 +2954,7 @@
29122954 	if (r)
29132955 		return r;
29142956 
2915
-	drm_kms_helper_poll_init(adev->ddev);
2957
+	drm_kms_helper_poll_init(adev_to_drm(adev));
29162958 
29172959 	adev->mode_info.mode_config_initialized = true;
29182960 	return 0;
....@@ -2924,13 +2966,13 @@
29242966 
29252967 	kfree(adev->mode_info.bios_hardcoded_edid);
29262968 
2927
-	drm_kms_helper_poll_fini(adev->ddev);
2969
+	drm_kms_helper_poll_fini(adev_to_drm(adev));
29282970 
29292971 	dce_v11_0_audio_fini(adev);
29302972 
29312973 	dce_v11_0_afmt_fini(adev);
29322974 
2933
-	drm_mode_config_cleanup(adev->ddev);
2975
+	drm_mode_config_cleanup(adev_to_drm(adev));
29342976 	adev->mode_info.mode_config_initialized = false;
29352977 
29362978 	return 0;
....@@ -3241,14 +3283,14 @@
32413283 	if(amdgpu_crtc == NULL)
32423284 		return 0;
32433285 
3244
-	spin_lock_irqsave(&adev->ddev->event_lock, flags);
3286
+	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
32453287 	works = amdgpu_crtc->pflip_works;
32463288 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
32473289 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
32483290 						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
32493291 						 amdgpu_crtc->pflip_status,
32503292 						 AMDGPU_FLIP_SUBMITTED);
3251
-		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3293
+		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
32523294 		return 0;
32533295 	}
32543296 
....@@ -3260,7 +3302,7 @@
32603302 	if(works->event)
32613303 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
32623304 
3263
-	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3305
+	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
32643306 
32653307 	drm_crtc_vblank_put(&amdgpu_crtc->base);
32663308 	schedule_work(&works->unpin_work);
....@@ -3330,7 +3372,7 @@
33303372 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
33313373 
33323374 		if (amdgpu_irq_enabled(adev, source, irq_type)) {
3333
-			drm_handle_vblank(adev->ddev, crtc);
3375
+			drm_handle_vblank(adev_to_drm(adev), crtc);
33343376 		}
33353377 		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
33363378 
....@@ -3429,7 +3471,7 @@
34293471 
34303472 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
34313473 {
3432
-	struct amdgpu_device *adev = encoder->dev->dev_private;
3474
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
34333475 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
34343476 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
34353477 
....@@ -3469,7 +3511,7 @@
34693511 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
34703512 {
34713513 	struct drm_device *dev = encoder->dev;
3472
-	struct amdgpu_device *adev = dev->dev_private;
3514
+	struct amdgpu_device *adev = drm_to_adev(dev);
34733515 
34743516 	/* need to call this here as we need the crtc set up */
34753517 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
....@@ -3569,7 +3611,7 @@
35693611 				 uint32_t supported_device,
35703612 				 u16 caps)
35713613 {
3572
-	struct drm_device *dev = adev->ddev;
3614
+	struct drm_device *dev = adev_to_drm(adev);
35733615 	struct drm_encoder *encoder;
35743616 	struct amdgpu_encoder *amdgpu_encoder;
35753617 
....@@ -3690,8 +3732,7 @@
36903732 
36913733 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
36923734 {
3693
-	if (adev->mode_info.funcs == NULL)
3694
-		adev->mode_info.funcs = &dce_v11_0_display_funcs;
3735
+	adev->mode_info.funcs = &dce_v11_0_display_funcs;
36953736 }
36963737 
36973738 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {