forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
....@@ -20,7 +20,10 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  *
2222  */
23
-#include <drm/drmP.h>
23
+
24
+#include <drm/drm_fourcc.h>
25
+#include <drm/drm_vblank.h>
26
+
2427 #include "amdgpu.h"
2528 #include "amdgpu_pm.h"
2629 #include "amdgpu_i2c.h"
....@@ -31,6 +34,7 @@
3134 #include "atombios_encoders.h"
3235 #include "amdgpu_pll.h"
3336 #include "amdgpu_connectors.h"
37
+#include "amdgpu_display.h"
3438 #include "dce_v10_0.h"
3539 
3640 #include "dce/dce_10_0_d.h"
....@@ -232,6 +236,7 @@
232236 				int crtc_id, u64 crtc_base, bool async)
233237 {
234238 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
239
+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
235240 	u32 tmp;
236241 
237242 	/* flip at hsync for async, default is vsync */
....@@ -239,6 +244,9 @@
239244 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
240245 			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
241246 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
247
+	/* update pitch */
248
+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
249
+	       fb->pitches[0] / fb->format->cpp[0]);
242250 	/* update the primary scanout address */
243251 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
244252 	       upper_32_bits(crtc_base));
....@@ -320,11 +328,13 @@
320328  */
321329 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
322330 {
323
-	struct drm_device *dev = adev->ddev;
331
+	struct drm_device *dev = adev_to_drm(adev);
324332 	struct drm_connector *connector;
333
+	struct drm_connector_list_iter iter;
325334 	u32 tmp;
326335 
327
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
336
+	drm_connector_list_iter_begin(dev, &iter);
337
+	drm_for_each_connector_iter(connector, &iter) {
328338 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
329339 
330340 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -360,6 +370,7 @@
360370 		amdgpu_irq_get(adev, &adev->hpd_irq,
361371 			       amdgpu_connector->hpd.hpd);
362372 	}
373
+	drm_connector_list_iter_end(&iter);
363374 }
364375 
365376 /**
....@@ -372,11 +383,13 @@
372383  */
373384 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
374385 {
375
-	struct drm_device *dev = adev->ddev;
386
+	struct drm_device *dev = adev_to_drm(adev);
376387 	struct drm_connector *connector;
388
+	struct drm_connector_list_iter iter;
377389 	u32 tmp;
378390 
379
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
391
+	drm_connector_list_iter_begin(dev, &iter);
392
+	drm_for_each_connector_iter(connector, &iter) {
380393 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
381394 
382395 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
....@@ -389,6 +402,7 @@
389402 		amdgpu_irq_put(adev, &adev->hpd_irq,
390403 			       amdgpu_connector->hpd.hpd);
391404 	}
405
+	drm_connector_list_iter_end(&iter);
392406 }
393407 
394408 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
....@@ -490,7 +504,7 @@
490504 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
491505 {
492506 	struct drm_device *dev = encoder->dev;
493
-	struct amdgpu_device *adev = dev->dev_private;
507
+	struct amdgpu_device *adev = drm_to_adev(dev);
494508 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
495509 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
496510 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
....@@ -1195,7 +1209,7 @@
11951209 
11961210 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
11971211 {
1198
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1212
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
11991213 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12001214 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12011215 	u32 tmp;
....@@ -1211,10 +1225,12 @@
12111225 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
12121226 						struct drm_display_mode *mode)
12131227 {
1214
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1228
+	struct drm_device *dev = encoder->dev;
1229
+	struct amdgpu_device *adev = drm_to_adev(dev);
12151230 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12161231 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12171232 	struct drm_connector *connector;
1233
+	struct drm_connector_list_iter iter;
12181234 	struct amdgpu_connector *amdgpu_connector = NULL;
12191235 	u32 tmp;
12201236 	int interlace = 0;
....@@ -1222,12 +1238,14 @@
12221238 	if (!dig || !dig->afmt || !dig->afmt->pin)
12231239 		return;
12241240 
1225
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1241
+	drm_connector_list_iter_begin(dev, &iter);
1242
+	drm_for_each_connector_iter(connector, &iter) {
12261243 		if (connector->encoder == encoder) {
12271244 			amdgpu_connector = to_amdgpu_connector(connector);
12281245 			break;
12291246 		}
12301247 	}
1248
+	drm_connector_list_iter_end(&iter);
12311249 
12321250 	if (!amdgpu_connector) {
12331251 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1253,10 +1271,12 @@
12531271 
12541272 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
12551273 {
1256
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1274
+	struct drm_device *dev = encoder->dev;
1275
+	struct amdgpu_device *adev = drm_to_adev(dev);
12571276 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
12581277 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
12591278 	struct drm_connector *connector;
1279
+	struct drm_connector_list_iter iter;
12601280 	struct amdgpu_connector *amdgpu_connector = NULL;
12611281 	u32 tmp;
12621282 	u8 *sadb = NULL;
....@@ -1265,12 +1285,14 @@
12651285 	if (!dig || !dig->afmt || !dig->afmt->pin)
12661286 		return;
12671287 
1268
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1288
+	drm_connector_list_iter_begin(dev, &iter);
1289
+	drm_for_each_connector_iter(connector, &iter) {
12691290 		if (connector->encoder == encoder) {
12701291 			amdgpu_connector = to_amdgpu_connector(connector);
12711292 			break;
12721293 		}
12731294 	}
1295
+	drm_connector_list_iter_end(&iter);
12741296 
12751297 	if (!amdgpu_connector) {
12761298 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1305,10 +1327,12 @@
13051327 
13061328 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
13071329 {
1308
-	struct amdgpu_device *adev = encoder->dev->dev_private;
1330
+	struct drm_device *dev = encoder->dev;
1331
+	struct amdgpu_device *adev = drm_to_adev(dev);
13091332 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
13101333 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
13111334 	struct drm_connector *connector;
1335
+	struct drm_connector_list_iter iter;
13121336 	struct amdgpu_connector *amdgpu_connector = NULL;
13131337 	struct cea_sad *sads;
13141338 	int i, sad_count;
....@@ -1331,12 +1355,14 @@
13311355 	if (!dig || !dig->afmt || !dig->afmt->pin)
13321356 		return;
13331357 
1334
-	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1358
+	drm_connector_list_iter_begin(dev, &iter);
1359
+	drm_for_each_connector_iter(connector, &iter) {
13351360 		if (connector->encoder == encoder) {
13361361 			amdgpu_connector = to_amdgpu_connector(connector);
13371362 			break;
13381363 		}
13391364 	}
1365
+	drm_connector_list_iter_end(&iter);
13401366 
13411367 	if (!amdgpu_connector) {
13421368 		DRM_ERROR("Couldn't find encoder's connector\n");
....@@ -1344,10 +1370,10 @@
13441370 	}
13451371 
13461372 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1347
-	if (sad_count <= 0) {
1373
+	if (sad_count < 0)
13481374 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1375
+	if (sad_count <= 0)
13491376 		return;
1350
-	}
13511377 	BUG_ON(!sads);
13521378 
13531379 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
....@@ -1457,7 +1483,7 @@
14571483 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
14581484 {
14591485 	struct drm_device *dev = encoder->dev;
1460
-	struct amdgpu_device *adev = dev->dev_private;
1486
+	struct amdgpu_device *adev = drm_to_adev(dev);
14611487 	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
14621488 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14631489 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
....@@ -1493,7 +1519,7 @@
14931519 					       void *buffer, size_t size)
14941520 {
14951521 	struct drm_device *dev = encoder->dev;
1496
-	struct amdgpu_device *adev = dev->dev_private;
1522
+	struct amdgpu_device *adev = drm_to_adev(dev);
14971523 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
14981524 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
14991525 	uint8_t *frame = buffer + 3;
....@@ -1512,7 +1538,7 @@
15121538 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
15131539 {
15141540 	struct drm_device *dev = encoder->dev;
1515
-	struct amdgpu_device *adev = dev->dev_private;
1541
+	struct amdgpu_device *adev = drm_to_adev(dev);
15161542 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15171543 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15181544 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
....@@ -1543,7 +1569,7 @@
15431569 				  struct drm_display_mode *mode)
15441570 {
15451571 	struct drm_device *dev = encoder->dev;
1546
-	struct amdgpu_device *adev = dev->dev_private;
1572
+	struct amdgpu_device *adev = drm_to_adev(dev);
15471573 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
15481574 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
15491575 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
....@@ -1681,7 +1707,7 @@
16811707 	dce_v10_0_audio_write_sad_regs(encoder);
16821708 	dce_v10_0_audio_write_latency_fields(encoder, mode);
16831709 
1684
-	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1710
+	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
16851711 	if (err < 0) {
16861712 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
16871713 		return;
....@@ -1723,7 +1749,7 @@
17231749 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
17241750 {
17251751 	struct drm_device *dev = encoder->dev;
1726
-	struct amdgpu_device *adev = dev->dev_private;
1752
+	struct amdgpu_device *adev = drm_to_adev(dev);
17271753 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
17281754 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
17291755 
....@@ -1796,7 +1822,7 @@
17961822 {
17971823 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
17981824 	struct drm_device *dev = crtc->dev;
1799
-	struct amdgpu_device *adev = dev->dev_private;
1825
+	struct amdgpu_device *adev = drm_to_adev(dev);
18001826 	u32 vga_control;
18011827 
18021828 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
....@@ -1810,7 +1836,7 @@
18101836 {
18111837 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
18121838 	struct drm_device *dev = crtc->dev;
1813
-	struct amdgpu_device *adev = dev->dev_private;
1839
+	struct amdgpu_device *adev = drm_to_adev(dev);
18141840 
18151841 	if (enable)
18161842 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
....@@ -1824,7 +1850,7 @@
18241850 {
18251851 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
18261852 	struct drm_device *dev = crtc->dev;
1827
-	struct amdgpu_device *adev = dev->dev_private;
1853
+	struct amdgpu_device *adev = drm_to_adev(dev);
18281854 	struct drm_framebuffer *target_fb;
18291855 	struct drm_gem_object *obj;
18301856 	struct amdgpu_bo *abo;
....@@ -1942,6 +1968,17 @@
19421968 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
19431969 		bypass_lut = true;
19441970 		break;
1971
+	case DRM_FORMAT_XBGR8888:
1972
+	case DRM_FORMAT_ABGR8888:
1973
+		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1974
+		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1975
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1976
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1977
+#ifdef __BIG_ENDIAN
1978
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1979
+					ENDIAN_8IN32);
1980
+#endif
1981
+		break;
19451982 	default:
19461983 		DRM_ERROR("Unsupported screen format %s\n",
19471984 		          drm_get_format_name(target_fb->format->format, &format_name));
....@@ -2058,7 +2095,7 @@
20582095 				     struct drm_display_mode *mode)
20592096 {
20602097 	struct drm_device *dev = crtc->dev;
2061
-	struct amdgpu_device *adev = dev->dev_private;
2098
+	struct amdgpu_device *adev = drm_to_adev(dev);
20622099 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
20632100 	u32 tmp;
20642101 
....@@ -2074,7 +2111,7 @@
20742111 {
20752112 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
20762113 	struct drm_device *dev = crtc->dev;
2077
-	struct amdgpu_device *adev = dev->dev_private;
2114
+	struct amdgpu_device *adev = drm_to_adev(dev);
20782115 	u16 *r, *g, *b;
20792116 	int i;
20802117 	u32 tmp;
....@@ -2213,7 +2250,7 @@
22132250 {
22142251 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
22152252 	struct drm_device *dev = crtc->dev;
2216
-	struct amdgpu_device *adev = dev->dev_private;
2253
+	struct amdgpu_device *adev = drm_to_adev(dev);
22172254 	u32 pll_in_use;
22182255 	int pll;
22192256 
....@@ -2248,7 +2285,7 @@
22482285 
22492286 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
22502287 {
2251
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2288
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
22522289 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
22532290 	uint32_t cur_lock;
22542291 
....@@ -2263,18 +2300,18 @@
22632300 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
22642301 {
22652302 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2266
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2303
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
22672304 	u32 tmp;
22682305 
2269
-	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2306
+	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
22702307 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2271
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2308
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
22722309 }
22732310 
22742311 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
22752312 {
22762313 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2277
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2314
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
22782315 	u32 tmp;
22792316 
22802317 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
....@@ -2282,17 +2319,17 @@
22822319 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
22832320 	       lower_32_bits(amdgpu_crtc->cursor_addr));
22842321 
2285
-	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2322
+	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
22862323 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
22872324 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2288
-	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2325
+	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
22892326 }
22902327 
22912328 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
22922329 					int x, int y)
22932330 {
22942331 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2295
-	struct amdgpu_device *adev = crtc->dev->dev_private;
2332
+	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
22962333 	int xorigin = 0, yorigin = 0;
22972334 
22982335 	amdgpu_crtc->cursor_x = x;
....@@ -2367,7 +2404,7 @@
23672404 	aobj = gem_to_amdgpu_bo(obj);
23682405 	ret = amdgpu_bo_reserve(aobj, false);
23692406 	if (ret != 0) {
2370
-		drm_gem_object_put_unlocked(obj);
2407
+		drm_gem_object_put(obj);
23712408 		return ret;
23722409 	}
23732410 
....@@ -2375,7 +2412,7 @@
23752412 	amdgpu_bo_unreserve(aobj);
23762413 	if (ret) {
23772414 		DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2378
-		drm_gem_object_put_unlocked(obj);
2415
+		drm_gem_object_put(obj);
23792416 		return ret;
23802417 	}
23812418 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
....@@ -2410,7 +2447,7 @@
24102447 			amdgpu_bo_unpin(aobj);
24112448 			amdgpu_bo_unreserve(aobj);
24122449 		}
2413
-		drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2450
+		drm_gem_object_put(amdgpu_crtc->cursor_bo);
24142451 	}
24152452 
24162453 	amdgpu_crtc->cursor_bo = obj;
....@@ -2457,12 +2494,16 @@
24572494 	.set_config = amdgpu_display_crtc_set_config,
24582495 	.destroy = dce_v10_0_crtc_destroy,
24592496 	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2497
+	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2498
+	.enable_vblank = amdgpu_enable_vblank_kms,
2499
+	.disable_vblank = amdgpu_disable_vblank_kms,
2500
+	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
24602501 };
24612502 
24622503 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
24632504 {
24642505 	struct drm_device *dev = crtc->dev;
2465
-	struct amdgpu_device *adev = dev->dev_private;
2506
+	struct amdgpu_device *adev = drm_to_adev(dev);
24662507 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
24672508 	unsigned type;
24682509 
....@@ -2516,7 +2557,7 @@
25162557 {
25172558 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
25182559 	struct drm_device *dev = crtc->dev;
2519
-	struct amdgpu_device *adev = dev->dev_private;
2560
+	struct amdgpu_device *adev = drm_to_adev(dev);
25202561 	struct amdgpu_atom_ss ss;
25212562 	int i;
25222563 
....@@ -2648,6 +2689,7 @@
26482689 	.prepare = dce_v10_0_crtc_prepare,
26492690 	.commit = dce_v10_0_crtc_commit,
26502691 	.disable = dce_v10_0_crtc_disable,
2692
+	.get_scanout_position = amdgpu_crtc_get_scanout_position,
26512693 };
26522694 
26532695 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
....@@ -2659,7 +2701,7 @@
26592701 	if (amdgpu_crtc == NULL)
26602702 		return -ENOMEM;
26612703 
2662
-	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2704
+	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
26632705 
26642706 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
26652707 	amdgpu_crtc->crtc_id = index;
....@@ -2667,8 +2709,8 @@
26672709 
26682710 	amdgpu_crtc->max_cursor_width = 128;
26692711 	amdgpu_crtc->max_cursor_height = 128;
2670
-	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2671
-	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2712
+	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2713
+	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
26722714 
26732715 	switch (amdgpu_crtc->crtc_id) {
26742716 	case 0:
....@@ -2734,40 +2776,40 @@
27342776 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
27352777 
27362778 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2737
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2779
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
27382780 		if (r)
27392781 			return r;
27402782 	}
27412783 
27422784 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2743
-		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2785
+		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
27442786 		if (r)
27452787 			return r;
27462788 	}
27472789 
27482790 	/* HPD hotplug */
2749
-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2791
+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
27502792 	if (r)
27512793 		return r;
27522794 
2753
-	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2795
+	adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
27542796 
2755
-	adev->ddev->mode_config.async_page_flip = true;
2797
+	adev_to_drm(adev)->mode_config.async_page_flip = true;
27562798 
2757
-	adev->ddev->mode_config.max_width = 16384;
2758
-	adev->ddev->mode_config.max_height = 16384;
2799
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2800
+	adev_to_drm(adev)->mode_config.max_height = 16384;
27592801 
2760
-	adev->ddev->mode_config.preferred_depth = 24;
2761
-	adev->ddev->mode_config.prefer_shadow = 1;
2802
+	adev_to_drm(adev)->mode_config.preferred_depth = 24;
2803
+	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
27622804 
2763
-	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2805
+	adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
27642806 
27652807 	r = amdgpu_display_modeset_create_props(adev);
27662808 	if (r)
27672809 		return r;
27682810 
2769
-	adev->ddev->mode_config.max_width = 16384;
2770
-	adev->ddev->mode_config.max_height = 16384;
2811
+	adev_to_drm(adev)->mode_config.max_width = 16384;
2812
+	adev_to_drm(adev)->mode_config.max_height = 16384;
27712813 
27722814 	/* allocate crtcs */
27732815 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
....@@ -2777,7 +2819,7 @@
27772819 	}
27782820 
27792821 	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2780
-		amdgpu_display_print_display_setup(adev->ddev);
2822
+		amdgpu_display_print_display_setup(adev_to_drm(adev));
27812823 	else
27822824 		return -EINVAL;
27832825 
....@@ -2790,7 +2832,7 @@
27902832 	if (r)
27912833 		return r;
27922834 
2793
-	drm_kms_helper_poll_init(adev->ddev);
2835
+	drm_kms_helper_poll_init(adev_to_drm(adev));
27942836 
27952837 	adev->mode_info.mode_config_initialized = true;
27962838 	return 0;
....@@ -2802,13 +2844,13 @@
28022844 
28032845 	kfree(adev->mode_info.bios_hardcoded_edid);
28042846 
2805
-	drm_kms_helper_poll_fini(adev->ddev);
2847
+	drm_kms_helper_poll_fini(adev_to_drm(adev));
28062848 
28072849 	dce_v10_0_audio_fini(adev);
28082850 
28092851 	dce_v10_0_afmt_fini(adev);
28102852 
2811
-	drm_mode_config_cleanup(adev->ddev);
2853
+	drm_mode_config_cleanup(adev_to_drm(adev));
28122854 	adev->mode_info.mode_config_initialized = false;
28132855 
28142856 	return 0;
....@@ -3115,14 +3157,14 @@
31153157 	if (amdgpu_crtc == NULL)
31163158 		return 0;
31173159 
3118
-	spin_lock_irqsave(&adev->ddev->event_lock, flags);
3160
+	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
31193161 	works = amdgpu_crtc->pflip_works;
31203162 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
31213163 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
31223164 						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
31233165 						 amdgpu_crtc->pflip_status,
31243166 						 AMDGPU_FLIP_SUBMITTED);
3125
-		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3167
+		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
31263168 		return 0;
31273169 	}
31283170 
....@@ -3134,7 +3176,7 @@
31343176 	if (works->event)
31353177 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
31363178 
3137
-	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3179
+	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
31383180 
31393181 	drm_crtc_vblank_put(&amdgpu_crtc->base);
31403182 	schedule_work(&works->unpin_work);
....@@ -3203,7 +3245,7 @@
32033245 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
32043246 
32053247 		if (amdgpu_irq_enabled(adev, source, irq_type)) {
3206
-			drm_handle_vblank(adev->ddev, crtc);
3248
+			drm_handle_vblank(adev_to_drm(adev), crtc);
32073249 		}
32083250 		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
32093251 
....@@ -3303,7 +3345,7 @@
33033345 
33043346 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
33053347 {
3306
-	struct amdgpu_device *adev = encoder->dev->dev_private;
3348
+	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
33073349 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
33083350 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
33093351 
....@@ -3343,7 +3385,7 @@
33433385 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
33443386 {
33453387 	struct drm_device *dev = encoder->dev;
3346
-	struct amdgpu_device *adev = dev->dev_private;
3388
+	struct amdgpu_device *adev = drm_to_adev(dev);
33473389 
33483390 	/* need to call this here as we need the crtc set up */
33493391 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
....@@ -3443,7 +3485,7 @@
34433485 				 uint32_t supported_device,
34443486 				 u16 caps)
34453487 {
3446
-	struct drm_device *dev = adev->ddev;
3488
+	struct drm_device *dev = adev_to_drm(adev);
34473489 	struct drm_encoder *encoder;
34483490 	struct amdgpu_encoder *amdgpu_encoder;
34493491 
....@@ -3558,8 +3600,7 @@
35583600 
35593601 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
35603602 {
3561
-	if (adev->mode_info.funcs == NULL)
3562
-		adev->mode_info.funcs = &dce_v10_0_display_funcs;
3603
+	adev->mode_info.funcs = &dce_v10_0_display_funcs;
35633604 }
35643605 
35653606 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {