add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/cz_ih.c
..
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@@ -20,7 +20,9 @@
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  * OTHER DEALINGS IN THE SOFTWARE.
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  *
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  */
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-#include <drm/drmP.h>
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+
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+#include <linux/pci.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_ih.h"
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 #include "vid.h"
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@@ -103,9 +105,9 @@
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  */
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 static int cz_ih_irq_init(struct amdgpu_device *adev)
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 {
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-	int rb_bufsz;
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+	struct amdgpu_ih_ring *ih = &adev->irq.ih;
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 	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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-	u64 wptr_off;
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+	int rb_bufsz;
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111
 
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 	/* disable irqs */
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 	cz_ih_disable_interrupts(adev);
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@@ -133,9 +135,8 @@
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 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
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136
 
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 	/* set the writeback address whether it's enabled or not */
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-	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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-	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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-	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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+	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
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+	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
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 	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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142
 
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@@ -185,54 +186,38 @@
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  * Used by cz_irq_process(VI).
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  * Returns the value of the wptr.
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  */
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-static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
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+static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
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+			  struct amdgpu_ih_ring *ih)
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 {
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 	u32 wptr, tmp;
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193
 
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-	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
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+	wptr = le32_to_cpu(*ih->wptr_cpu);
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-	if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
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-		wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
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-		/* When a ring buffer overflow happen start parsing interrupt
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-		 * from the last not overwritten vector (wptr + 16). Hopefully
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-		 * this should allow us to catchup.
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-		 */
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-		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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-			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
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-		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
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-		tmp = RREG32(mmIH_RB_CNTL);
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-		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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-		WREG32(mmIH_RB_CNTL, tmp);
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-	}
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-	return (wptr & adev->irq.ih.ptr_mask);
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-}
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+	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
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+		goto out;
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198
 
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-/**
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- * cz_ih_prescreen_iv - prescreen an interrupt vector
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- *
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- * @adev: amdgpu_device pointer
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- *
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- * Returns true if the interrupt vector should be further processed.
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- */
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-static bool cz_ih_prescreen_iv(struct amdgpu_device *adev)
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-{
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-	u32 ring_index = adev->irq.ih.rptr >> 2;
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-	u16 pasid;
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+	/* Double check that the overflow wasn't already cleared. */
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+	wptr = RREG32(mmIH_RB_WPTR);
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201
 
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-	switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
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-	case 146:
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-	case 147:
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-		pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
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-		if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
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-			return true;
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-		break;
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-	default:
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-		/* Not a VM fault */
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-		return true;
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-	}
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+	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
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+		goto out;
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204
 
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-	adev->irq.ih.rptr += 16;
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-	return false;
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+	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
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+
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+	/* When a ring buffer overflow happen start parsing interrupt
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+	 * from the last not overwritten vector (wptr + 16). Hopefully
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+	 * this should allow us to catchup.
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+	 */
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+	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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+		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
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+	ih->rptr = (wptr + 16) & ih->ptr_mask;
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+	tmp = RREG32(mmIH_RB_CNTL);
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+	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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+	WREG32(mmIH_RB_CNTL, tmp);
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+
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+
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+out:
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+	return (wptr & ih->ptr_mask);
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 }
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222
 
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 /**
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@@ -244,18 +229,19 @@
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  * position and also advance the position.
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  */
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 static void cz_ih_decode_iv(struct amdgpu_device *adev,
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-				 struct amdgpu_iv_entry *entry)
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+			    struct amdgpu_ih_ring *ih,
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+			    struct amdgpu_iv_entry *entry)
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 {
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 	/* wptr/rptr are in bytes! */
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-	u32 ring_index = adev->irq.ih.rptr >> 2;
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+	u32 ring_index = ih->rptr >> 2;
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237
 	uint32_t dw[4];
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238
 
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-	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
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-	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
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-	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
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-	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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+	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
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+	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
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+	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
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+	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
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243
 
258
-	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
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+	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
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 	entry->src_id = dw[0] & 0xff;
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 	entry->src_data[0] = dw[1] & 0xfffffff;
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 	entry->ring_id = dw[2] & 0xff;
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@@ -263,7 +249,7 @@
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 	entry->pasid = (dw[2] >> 16) & 0xffff;
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250
 
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 	/* wptr/rptr are in bytes! */
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-	adev->irq.ih.rptr += 16;
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+	ih->rptr += 16;
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 }
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 /**
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@@ -273,9 +259,10 @@
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  *
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  * Set the IH ring buffer rptr.
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  */
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-static void cz_ih_set_rptr(struct amdgpu_device *adev)
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+static void cz_ih_set_rptr(struct amdgpu_device *adev,
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+			   struct amdgpu_ih_ring *ih)
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 {
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-	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
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+	WREG32(mmIH_RB_RPTR, ih->rptr);
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 }
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 static int cz_ih_early_init(void *handle)
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@@ -297,7 +284,7 @@
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 	int r;
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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286
 
300
-	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
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+	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
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 	if (r)
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 		return r;
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290
 
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@@ -311,7 +298,7 @@
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 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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299
 
313
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 	amdgpu_irq_fini(adev);
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-	amdgpu_ih_ring_fini(adev);
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+	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
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302
 	amdgpu_irq_remove_domain(adev);
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303
 
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 	return 0;
..
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@@ -442,15 +429,13 @@
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429
 
443
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 static const struct amdgpu_ih_funcs cz_ih_funcs = {
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 	.get_wptr = cz_ih_get_wptr,
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-	.prescreen_iv = cz_ih_prescreen_iv,
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 	.decode_iv = cz_ih_decode_iv,
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 	.set_rptr = cz_ih_set_rptr
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 };
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 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
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 {
452
-	if (adev->irq.ih_funcs == NULL)
453
-		adev->irq.ih_funcs = &cz_ih_funcs;
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+	adev->irq.ih_funcs = &cz_ih_funcs;
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 }
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 const struct amdgpu_ip_block_version cz_ih_ip_block =