add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/cik_ih.c
..
..
@@ -20,7 +20,9 @@
20
20
  * OTHER DEALINGS IN THE SOFTWARE.
21
21
  *
22
22
  */
23
-#include <drm/drmP.h>
23
+
24
+#include <linux/pci.h>
25
+
24
26
 #include "amdgpu.h"
25
27
 #include "amdgpu_ih.h"
26
28
 #include "cikd.h"
..
..
@@ -103,9 +105,9 @@
103
105
  */
104
106
 static int cik_ih_irq_init(struct amdgpu_device *adev)
105
107
 {
108
+	struct amdgpu_ih_ring *ih = &adev->irq.ih;
106
109
 	int rb_bufsz;
107
110
 	u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
108
-	u64 wptr_off;
109
111
 
110
112
 	/* disable irqs */
111
113
 	cik_ih_disable_interrupts(adev);
..
..
@@ -131,9 +133,8 @@
131
133
 	ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
132
134
 
133
135
 	/* set the writeback address whether it's enabled or not */
134
-	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
135
-	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
136
-	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
136
+	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
137
+	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
137
138
 
138
139
 	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
139
140
 
..
..
@@ -183,11 +184,12 @@
183
184
  * Used by cik_irq_process().
184
185
  * Returns the value of the wptr.
185
186
  */
186
-static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
187
+static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
188
+			   struct amdgpu_ih_ring *ih)
187
189
 {
188
190
 	u32 wptr, tmp;
189
191
 
190
-	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
192
+	wptr = le32_to_cpu(*ih->wptr_cpu);
191
193
 
192
194
 	if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
193
195
 		wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
..
..
@@ -196,13 +198,13 @@
196
198
 		 * this should allow us to catchup.
197
199
 		 */
198
200
 		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
199
-			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
200
-		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
201
+			 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
202
+		ih->rptr = (wptr + 16) & ih->ptr_mask;
201
203
 		tmp = RREG32(mmIH_RB_CNTL);
202
204
 		tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
203
205
 		WREG32(mmIH_RB_CNTL, tmp);
204
206
 	}
205
-	return (wptr & adev->irq.ih.ptr_mask);
207
+	return (wptr & ih->ptr_mask);
206
208
 }
207
209
 
208
210
 /*        CIK IV Ring
..
..
@@ -228,34 +230,6 @@
228
230
  * [127:96] - reserved
229
231
  */
230
232
 
231
-/**
232
- * cik_ih_prescreen_iv - prescreen an interrupt vector
233
- *
234
- * @adev: amdgpu_device pointer
235
- *
236
- * Returns true if the interrupt vector should be further processed.
237
- */
238
-static bool cik_ih_prescreen_iv(struct amdgpu_device *adev)
239
-{
240
-	u32 ring_index = adev->irq.ih.rptr >> 2;
241
-	u16 pasid;
242
-
243
-	switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
244
-	case 146:
245
-	case 147:
246
-		pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
247
-		if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
248
-			return true;
249
-		break;
250
-	default:
251
-		/* Not a VM fault */
252
-		return true;
253
-	}
254
-
255
-	adev->irq.ih.rptr += 16;
256
-	return false;
257
-}
258
-
259
233
  /**
260
234
  * cik_ih_decode_iv - decode an interrupt vector
261
235
  *
..
..
@@ -265,18 +239,19 @@
265
239
  * position and also advance the position.
266
240
  */
267
241
 static void cik_ih_decode_iv(struct amdgpu_device *adev,
242
+			     struct amdgpu_ih_ring *ih,
268
243
 			     struct amdgpu_iv_entry *entry)
269
244
 {
270
245
 	/* wptr/rptr are in bytes! */
271
-	u32 ring_index = adev->irq.ih.rptr >> 2;
246
+	u32 ring_index = ih->rptr >> 2;
272
247
 	uint32_t dw[4];
273
248
 
274
-	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
275
-	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
276
-	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
277
-	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
249
+	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
250
+	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
251
+	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
252
+	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
278
253
 
279
-	entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
254
+	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
280
255
 	entry->src_id = dw[0] & 0xff;
281
256
 	entry->src_data[0] = dw[1] & 0xfffffff;
282
257
 	entry->ring_id = dw[2] & 0xff;
..
..
@@ -284,7 +259,7 @@
284
259
 	entry->pasid = (dw[2] >> 16) & 0xffff;
285
260
 
286
261
 	/* wptr/rptr are in bytes! */
287
-	adev->irq.ih.rptr += 16;
262
+	ih->rptr += 16;
288
263
 }
289
264
 
290
265
 /**
..
..
@@ -294,9 +269,10 @@
294
269
  *
295
270
  * Set the IH ring buffer rptr.
296
271
  */
297
-static void cik_ih_set_rptr(struct amdgpu_device *adev)
272
+static void cik_ih_set_rptr(struct amdgpu_device *adev,
273
+			    struct amdgpu_ih_ring *ih)
298
274
 {
299
-	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
275
+	WREG32(mmIH_RB_RPTR, ih->rptr);
300
276
 }
301
277
 
302
278
 static int cik_ih_early_init(void *handle)
..
..
@@ -318,7 +294,7 @@
318
294
 	int r;
319
295
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
320
296
 
321
-	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
297
+	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);
322
298
 	if (r)
323
299
 		return r;
324
300
 
..
..
@@ -332,7 +308,7 @@
332
308
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
333
309
 
334
310
 	amdgpu_irq_fini(adev);
335
-	amdgpu_ih_ring_fini(adev);
311
+	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
336
312
 	amdgpu_irq_remove_domain(adev);
337
313
 
338
314
 	return 0;
..
..
@@ -340,14 +316,9 @@
340
316
 
341
317
 static int cik_ih_hw_init(void *handle)
342
318
 {
343
-	int r;
344
319
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
345
320
 
346
-	r = cik_ih_irq_init(adev);
347
-	if (r)
348
-		return r;
349
-
350
-	return 0;
321
+	return cik_ih_irq_init(adev);
351
322
 }
352
323
 
353
324
 static int cik_ih_hw_fini(void *handle)
..
..
@@ -461,15 +432,13 @@
461
432
 
462
433
 static const struct amdgpu_ih_funcs cik_ih_funcs = {
463
434
 	.get_wptr = cik_ih_get_wptr,
464
-	.prescreen_iv = cik_ih_prescreen_iv,
465
435
 	.decode_iv = cik_ih_decode_iv,
466
436
 	.set_rptr = cik_ih_set_rptr
467
437
 };
468
438
 
469
439
 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)
470
440
 {
471
-	if (adev->irq.ih_funcs == NULL)
472
-		adev->irq.ih_funcs = &cik_ih_funcs;
441
+	adev->irq.ih_funcs = &cik_ih_funcs;
473
442
 }
474
443
 
475
444
 const struct amdgpu_ip_block_version cik_ih_ip_block =