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hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
....@@ -24,11 +24,25 @@
2424 #ifndef AMDGPU_VIRT_H
2525 #define AMDGPU_VIRT_H
2626 
27
+#include "amdgv_sriovmsg.h"
28
+
2729 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS  (1 << 0) /* vBIOS is sr-iov ready */
2830 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV   (1 << 1) /* sr-iov is enabled on this GPU */
2931 #define AMDGPU_SRIOV_CAPS_IS_VF        (1 << 2) /* this GPU is a virtual function */
3032 #define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass through for VM */
3133 #define AMDGPU_SRIOV_CAPS_RUNTIME      (1 << 4) /* is out of full access mode */
34
+#define AMDGPU_VF_MMIO_ACCESS_PROTECT  (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
+
36
+/* all asic after AI use this offset */
37
+#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
38
+/* tonga/fiji use this offset */
39
+#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
40
+
41
+enum amdgpu_sriov_vf_mode {
42
+	SRIOV_VF_MODE_BARE_METAL = 0,
43
+	SRIOV_VF_MODE_ONE_VF,
44
+	SRIOV_VF_MODE_MULTI_VF,
45
+};
3246 
3347 struct amdgpu_mm_table {
3448 	struct amdgpu_bo	*bo;
....@@ -54,6 +68,7 @@
5468 struct amdgpu_virt_ops {
5569 	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
5670 	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
71
+	int (*req_init_data)(struct amdgpu_device *adev);
5772 	int (*reset_gpu)(struct amdgpu_device *adev);
5873 	int (*wait_reset)(struct amdgpu_device *adev);
5974 	void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
....@@ -63,11 +78,14 @@
6378  * Firmware Reserve Frame buffer
6479  */
6580 struct amdgpu_virt_fw_reserve {
66
-	struct amdgim_pf2vf_info_header *p_pf2vf;
67
-	struct amdgim_vf2pf_info_header *p_vf2pf;
81
+	struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
82
+	struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
6883 	unsigned int checksum_key;
6984 };
85
+
7086 /*
87
+ * Legacy GIM header
88
+ *
7189  * Defination between PF and VF
7290  * Structures forcibly aligned to 4 to keep the same style as PF.
7391  */
....@@ -83,17 +101,15 @@
83101 	AMDGIM_FEATURE_GIM_LOAD_UCODES   = 0x2,
84102 	/* VRAM LOST by GIM */
85103 	AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
104
+	/* MM bandwidth */
105
+	AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
106
+	/* PP ONE VF MODE in GIM */
107
+	AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
86108 };
87109 
88
-struct amdgim_pf2vf_info_header {
89
-	/* the total structure size in byte. */
90
-	uint32_t size;
91
-	/* version of this structure, written by the GIM */
92
-	uint32_t version;
93
-} __aligned(4);
94
-struct  amdgim_pf2vf_info_v1 {
110
+struct amdgim_pf2vf_info_v1 {
95111 	/* header contains size and version */
96
-	struct amdgim_pf2vf_info_header header;
112
+	struct amd_sriov_msg_pf2vf_info_header header;
97113 	/* max_width * max_height */
98114 	unsigned int uvd_enc_max_pixels_count;
99115 	/* 16x16 pixels/sec, codec independent */
....@@ -110,47 +126,9 @@
110126 	unsigned int checksum;
111127 } __aligned(4);
112128 
113
-struct  amdgim_pf2vf_info_v2 {
114
-	/* header contains size and version */
115
-	struct amdgim_pf2vf_info_header header;
116
-	/* use private key from mailbox 2 to create chueksum */
117
-	uint32_t checksum;
118
-	/* The features flags of the GIM driver supports. */
119
-	uint32_t feature_flags;
120
-	/* max_width * max_height */
121
-	uint32_t uvd_enc_max_pixels_count;
122
-	/* 16x16 pixels/sec, codec independent */
123
-	uint32_t uvd_enc_max_bandwidth;
124
-	/* max_width * max_height */
125
-	uint32_t vce_enc_max_pixels_count;
126
-	/* 16x16 pixels/sec, codec independent */
127
-	uint32_t vce_enc_max_bandwidth;
128
-	/* MEC FW position in kb from the start of VF visible frame buffer */
129
-	uint64_t mecfw_kboffset;
130
-	/* MEC FW size in KB */
131
-	uint32_t mecfw_ksize;
132
-	/* UVD FW position in kb from the start of VF visible frame buffer */
133
-	uint64_t uvdfw_kboffset;
134
-	/* UVD FW size in KB */
135
-	uint32_t uvdfw_ksize;
136
-	/* VCE FW position in kb from the start of VF visible frame buffer */
137
-	uint64_t vcefw_kboffset;
138
-	/* VCE FW size in KB */
139
-	uint32_t vcefw_ksize;
140
-	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amdgim_pf2vf_info_header)/sizeof(uint32_t)), 3)];
141
-} __aligned(4);
142
-
143
-
144
-struct amdgim_vf2pf_info_header {
145
-	/* the total structure size in byte. */
146
-	uint32_t size;
147
-	/*version of this structure, written by the guest */
148
-	uint32_t version;
149
-} __aligned(4);
150
-
151129 struct amdgim_vf2pf_info_v1 {
152130 	/* header contains size and version */
153
-	struct amdgim_vf2pf_info_header header;
131
+	struct amd_sriov_msg_vf2pf_info_header header;
154132 	/* driver version */
155133 	char driver_version[64];
156134 	/* driver certification, 1=WHQL, 0=None */
....@@ -180,7 +158,7 @@
180158 
181159 struct amdgim_vf2pf_info_v2 {
182160 	/* header contains size and version */
183
-	struct amdgim_vf2pf_info_header header;
161
+	struct amd_sriov_msg_vf2pf_info_header header;
184162 	uint32_t checksum;
185163 	/* driver version */
186164 	uint8_t driver_version[64];
....@@ -206,39 +184,25 @@
206184 	uint32_t uvd_enc_usage;
207185 	/* guest uvd engine usage percentage. 0xffff means N/A. */
208186 	uint32_t uvd_enc_health;
209
-	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amdgim_vf2pf_info_header)/sizeof(uint32_t)), 0)];
187
+	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
210188 } __aligned(4);
211189 
212
-#define AMDGPU_FW_VRAM_VF2PF_VER 2
213
-typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
214
-
215
-#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
216
-	do { \
217
-		((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
218
-	} while (0)
219
-
220
-#define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \
221
-	do { \
222
-		(*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
223
-	} while (0)
224
-
225
-#define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \
226
-	do { \
227
-		if (!adev->virt.fw_reserve.p_pf2vf) \
228
-			*(val) = 0; \
229
-		else { \
230
-			if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
231
-				*(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
232
-			if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
233
-				*(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
234
-		} \
235
-	} while (0)
190
+struct amdgpu_virt_ras_err_handler_data {
191
+	/* point to bad page records array */
192
+	struct eeprom_table_record *bps;
193
+	/* point to reserved bo array */
194
+	struct amdgpu_bo **bps_bo;
195
+	/* the count of entries */
196
+	int count;
197
+	/* last reserved entry's index + 1 */
198
+	int last_reserved;
199
+};
236200 
237201 /* GPU virtualization */
238202 struct amdgpu_virt {
239203 	uint32_t			caps;
240204 	struct amdgpu_bo		*csa_obj;
241
-	uint64_t			csa_vmid0_addr;
205
+	void				*csa_cpu_addr;
242206 	bool chained_ib_support;
243207 	uint32_t			reg_val_offs;
244208 	struct amdgpu_irq_src		ack_irq;
....@@ -246,12 +210,19 @@
246210 	struct work_struct		flr_work;
247211 	struct amdgpu_mm_table		mm_table;
248212 	const struct amdgpu_virt_ops	*ops;
249
-	struct amdgpu_vf_error_buffer   vf_errors;
213
+	struct amdgpu_vf_error_buffer	vf_errors;
250214 	struct amdgpu_virt_fw_reserve	fw_reserve;
251215 	uint32_t gim_feature;
252
-};
216
+	uint32_t reg_access_mode;
217
+	int req_init_data_ver;
218
+	bool tdr_debug;
219
+	struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
220
+	bool ras_init_done;
253221 
254
-#define AMDGPU_CSA_SIZE		(8 * 1024)
222
+	/* vf2pf message */
223
+	struct delayed_work vf2pf_work;
224
+	uint32_t vf2pf_update_interval_ms;
225
+};
255226 
256227 #define amdgpu_sriov_enabled(adev) \
257228 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
....@@ -265,8 +236,14 @@
265236 #define amdgpu_sriov_runtime(adev) \
266237 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
267238 
239
+#define amdgpu_sriov_fullaccess(adev) \
240
+(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
241
+
268242 #define amdgpu_passthrough(adev) \
269243 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
244
+
245
+#define amdgpu_sriov_vf_mmio_access_protection(adev) \
246
+((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
270247 
271248 static inline bool is_virtual_machine(void)
272249 {
....@@ -277,26 +254,34 @@
277254 #endif
278255 }
279256 
280
-struct amdgpu_vm;
257
+#define amdgpu_sriov_is_pp_one_vf(adev) \
258
+	((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
259
+#define amdgpu_sriov_is_debug(adev) \
260
+	((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
261
+#define amdgpu_sriov_is_normal(adev) \
262
+	((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
281263 
282
-uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev);
283264 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
284
-int amdgpu_allocate_static_csa(struct amdgpu_device *adev);
285
-int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
286
-			  struct amdgpu_bo_va **bo_va);
287
-void amdgpu_free_static_csa(struct amdgpu_device *adev);
288265 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
289
-uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
290
-void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
266
+void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
267
+					uint32_t reg0, uint32_t rreg1,
268
+					uint32_t ref, uint32_t mask);
291269 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
292270 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
293271 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
272
+void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
294273 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
295274 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
296275 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
297
-int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
298
-					unsigned int key,
299
-					unsigned int chksum);
276
+void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
300277 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
278
+void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
279
+void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
280
+void amdgpu_detect_virtualization(struct amdgpu_device *adev);
301281 
282
+bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
283
+int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
284
+void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
285
+
286
+enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
302287 #endif