forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
....@@ -30,7 +30,7 @@
3030 
3131 #include <linux/firmware.h>
3232 #include <linux/module.h>
33
-#include <drm/drmP.h>
33
+
3434 #include <drm/drm.h>
3535 
3636 #include "amdgpu.h"
....@@ -38,6 +38,8 @@
3838 #include "amdgpu_uvd.h"
3939 #include "cikd.h"
4040 #include "uvd/uvd_4_2_d.h"
41
+
42
+#include "amdgpu_ras.h"
4143 
4244 /* 1 second timeout */
4345 #define UVD_IDLE_TIMEOUT	msecs_to_jiffies(1000)
....@@ -52,6 +54,12 @@
5254 #define FW_1_66_16	((1 << 24) | (66 << 16) | (16 << 8))
5355 
5456 /* Firmware Names */
57
+#ifdef CONFIG_DRM_AMDGPU_SI
58
+#define FIRMWARE_TAHITI		"amdgpu/tahiti_uvd.bin"
59
+#define FIRMWARE_VERDE		"amdgpu/verde_uvd.bin"
60
+#define FIRMWARE_PITCAIRN	"amdgpu/pitcairn_uvd.bin"
61
+#define FIRMWARE_OLAND		"amdgpu/oland_uvd.bin"
62
+#endif
5563 #ifdef CONFIG_DRM_AMDGPU_CIK
5664 #define FIRMWARE_BONAIRE	"amdgpu/bonaire_uvd.bin"
5765 #define FIRMWARE_KABINI	"amdgpu/kabini_uvd.bin"
....@@ -98,6 +106,12 @@
98106 	unsigned *buf_sizes;
99107 };
100108 
109
+#ifdef CONFIG_DRM_AMDGPU_SI
110
+MODULE_FIRMWARE(FIRMWARE_TAHITI);
111
+MODULE_FIRMWARE(FIRMWARE_VERDE);
112
+MODULE_FIRMWARE(FIRMWARE_PITCAIRN);
113
+MODULE_FIRMWARE(FIRMWARE_OLAND);
114
+#endif
101115 #ifdef CONFIG_DRM_AMDGPU_CIK
102116 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
103117 MODULE_FIRMWARE(FIRMWARE_KABINI);
....@@ -131,6 +145,20 @@
131145 	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
132146 
133147 	switch (adev->asic_type) {
148
+#ifdef CONFIG_DRM_AMDGPU_SI
149
+	case CHIP_TAHITI:
150
+		fw_name = FIRMWARE_TAHITI;
151
+		break;
152
+	case CHIP_VERDE:
153
+		fw_name = FIRMWARE_VERDE;
154
+		break;
155
+	case CHIP_PITCAIRN:
156
+		fw_name = FIRMWARE_PITCAIRN;
157
+		break;
158
+	case CHIP_OLAND:
159
+		fw_name = FIRMWARE_OLAND;
160
+		break;
161
+#endif
134162 #ifdef CONFIG_DRM_AMDGPU_CIK
135163 	case CHIP_BONAIRE:
136164 		fw_name = FIRMWARE_BONAIRE;
....@@ -297,6 +325,7 @@
297325 {
298326 	int i, j;
299327 
328
+	cancel_delayed_work_sync(&adev->uvd.idle_work);
300329 	drm_sched_entity_destroy(&adev->uvd.entity);
301330 
302331 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
....@@ -327,12 +356,13 @@
327356 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
328357 {
329358 	struct amdgpu_ring *ring;
330
-	struct drm_sched_rq *rq;
359
+	struct drm_gpu_scheduler *sched;
331360 	int r;
332361 
333362 	ring = &adev->uvd.inst[0].ring;
334
-	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
335
-	r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);
363
+	sched = &ring->sched;
364
+	r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
365
+				  &sched, 1, NULL);
336366 	if (r) {
337367 		DRM_ERROR("Failed setting up UVD kernel entity.\n");
338368 		return r;
....@@ -346,6 +376,7 @@
346376 	unsigned size;
347377 	void *ptr;
348378 	int i, j;
379
+	bool in_ras_intr = amdgpu_ras_intr_triggered();
349380 
350381 	cancel_delayed_work_sync(&adev->uvd.idle_work);
351382 
....@@ -372,8 +403,16 @@
372403 		if (!adev->uvd.inst[j].saved_bo)
373404 			return -ENOMEM;
374405 
375
-		memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
406
+		/* re-write 0 since err_event_athub will corrupt VCPU buffer */
407
+		if (in_ras_intr)
408
+			memset(adev->uvd.inst[j].saved_bo, 0, size);
409
+		else
410
+			memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
376411 	}
412
+
413
+	if (in_ras_intr)
414
+		DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
415
+
377416 	return 0;
378417 }
379418 
....@@ -692,6 +731,8 @@
692731 	buf_sizes[0x1] = dpb_size;
693732 	buf_sizes[0x2] = image_size;
694733 	buf_sizes[0x4] = min_ctx_size;
734
+	/* store image width to adjust nb memory pstate */
735
+	adev->uvd.decode_image_width = width;
695736 	return 0;
696737 }
697738 
....@@ -1041,7 +1082,8 @@
10411082 			goto err;
10421083 	}
10431084 
1044
-	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
1085
+	r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT :
1086
+				     AMDGPU_IB_POOL_DELAYED, &job);
10451087 	if (r)
10461088 		goto err;
10471089 
....@@ -1071,7 +1113,7 @@
10711113 	ib->length_dw = 16;
10721114 
10731115 	if (direct) {
1074
-		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
1116
+		r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
10751117 							true, false,
10761118 							msecs_to_jiffies(10));
10771119 		if (r == 0)
....@@ -1083,8 +1125,9 @@
10831125 		if (r)
10841126 			goto err_free;
10851127 	} else {
1086
-		r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
1087
-				     AMDGPU_FENCE_OWNER_UNDEFINED, false);
1128
+		r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv,
1129
+				     AMDGPU_SYNC_ALWAYS,
1130
+				     AMDGPU_FENCE_OWNER_UNDEFINED);
10881131 		if (r)
10891132 			goto err_free;
10901133 
....@@ -1243,30 +1286,20 @@
12431286 {
12441287 	struct dma_fence *fence;
12451288 	long r;
1246
-	uint32_t ip_instance = ring->me;
12471289 
12481290 	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1249
-	if (r) {
1250
-		DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ip_instance, r);
1291
+	if (r)
12511292 		goto error;
1252
-	}
12531293 
12541294 	r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1255
-	if (r) {
1256
-		DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ip_instance, r);
1295
+	if (r)
12571296 		goto error;
1258
-	}
12591297 
12601298 	r = dma_fence_wait_timeout(fence, false, timeout);
1261
-	if (r == 0) {
1262
-		DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ip_instance);
1299
+	if (r == 0)
12631300 		r = -ETIMEDOUT;
1264
-	} else if (r < 0) {
1265
-		DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ip_instance, r);
1266
-	} else {
1267
-		DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ip_instance, ring->idx);
1301
+	else if (r > 0)
12681302 		r = 0;
1269
-	}
12701303 
12711304 	dma_fence_put(fence);
12721305