hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h
....@@ -27,9 +27,16 @@
2727 #include <linux/hashtable.h>
2828
2929 struct dma_fence;
30
-struct reservation_object;
30
+struct dma_resv;
3131 struct amdgpu_device;
3232 struct amdgpu_ring;
33
+
34
+enum amdgpu_sync_mode {
35
+ AMDGPU_SYNC_ALWAYS,
36
+ AMDGPU_SYNC_NE_OWNER,
37
+ AMDGPU_SYNC_EQ_OWNER,
38
+ AMDGPU_SYNC_EXPLICIT
39
+};
3340
3441 /*
3542 * Container for fences used to sync command submissions.
....@@ -40,16 +47,14 @@
4047 };
4148
4249 void amdgpu_sync_create(struct amdgpu_sync *sync);
43
-int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
44
- struct dma_fence *f, bool explicit);
45
-int amdgpu_sync_resv(struct amdgpu_device *adev,
46
- struct amdgpu_sync *sync,
47
- struct reservation_object *resv,
48
- void *owner,
49
- bool explicit_sync);
50
+int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f);
51
+int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence);
52
+int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,
53
+ struct dma_resv *resv, enum amdgpu_sync_mode mode,
54
+ void *owner);
5055 struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
5156 struct amdgpu_ring *ring);
52
-struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit);
57
+struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
5358 int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone);
5459 int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
5560 void amdgpu_sync_free(struct amdgpu_sync *sync);