add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
..
..
@@ -27,13 +27,33 @@
27
27
 
28
28
 #include "amdgpu.h"
29
29
 #include "psp_gfx_if.h"
30
+#include "ta_xgmi_if.h"
31
+#include "ta_ras_if.h"
32
+#include "ta_rap_if.h"
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33
 
31
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 #define PSP_FENCE_BUFFER_SIZE	0x1000
32
35
 #define PSP_CMD_BUFFER_SIZE	0x1000
33
-#define PSP_ASD_SHARED_MEM_SIZE	0x4000
36
+#define PSP_XGMI_SHARED_MEM_SIZE 0x4000
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+#define PSP_RAS_SHARED_MEM_SIZE 0x4000
34
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 #define PSP_1_MEG		0x100000
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+#define PSP_TMR_SIZE	0x400000
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+#define PSP_HDCP_SHARED_MEM_SIZE	0x4000
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+#define PSP_DTM_SHARED_MEM_SIZE	0x4000
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+#define PSP_RAP_SHARED_MEM_SIZE	0x4000
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+#define PSP_SHARED_MEM_SIZE		0x4000
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44
 
36
45
 struct psp_context;
46
+struct psp_xgmi_node_info;
47
+struct psp_xgmi_topology_info;
48
+
49
+enum psp_bootloader_cmd {
50
+	PSP_BL__LOAD_SYSDRV		= 0x10000,
51
+	PSP_BL__LOAD_SOSDRV		= 0x20000,
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+	PSP_BL__LOAD_KEY_DATABASE	= 0x80000,
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+	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,
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+	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,
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+	PSP_BL__LOAD_TOS_SPL_TABLE	= 0x10000000,
56
+};
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57
 
38
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 enum psp_ring_type
39
59
 {
..
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@@ -53,28 +73,146 @@
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 	uint64_t			ring_mem_mc_addr;
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74
 	void				*ring_mem_handle;
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 	uint32_t			ring_size;
76
+	uint32_t			ring_wptr;
77
+};
78
+
79
+/* More registers may will be supported */
80
+enum psp_reg_prog_id {
81
+	PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
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+	PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
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+	PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
84
+	PSP_REG_LAST
56
85
 };
57
86
 
58
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 struct psp_funcs
59
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 {
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 	int (*init_microcode)(struct psp_context *psp);
90
+	int (*bootloader_load_kdb)(struct psp_context *psp);
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+	int (*bootloader_load_spl)(struct psp_context *psp);
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 	int (*bootloader_load_sysdrv)(struct psp_context *psp);
62
93
 	int (*bootloader_load_sos)(struct psp_context *psp);
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-	int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
64
-			    struct psp_gfx_cmd_resp *cmd);
65
94
 	int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
66
-	int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
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+	int (*ring_create)(struct psp_context *psp,
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+			   enum psp_ring_type ring_type);
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 	int (*ring_stop)(struct psp_context *psp,
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 			    enum psp_ring_type ring_type);
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 	int (*ring_destroy)(struct psp_context *psp,
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 			    enum psp_ring_type ring_type);
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-	int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
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-			  uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index);
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-	bool (*compare_sram_data)(struct psp_context *psp,
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-				  struct amdgpu_firmware_info *ucode,
75
-				  enum AMDGPU_UCODE_ID ucode_type);
76
101
 	bool (*smu_reload_quirk)(struct psp_context *psp);
77
102
 	int (*mode1_reset)(struct psp_context *psp);
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+	int (*mem_training)(struct psp_context *psp, uint32_t ops);
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+	uint32_t (*ring_get_wptr)(struct psp_context *psp);
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+	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
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+	int (*load_usbc_pd_fw)(struct psp_context *psp, dma_addr_t dma_addr);
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+	int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
108
+};
109
+
110
+#define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
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+struct psp_xgmi_node_info {
112
+	uint64_t				node_id;
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+	uint8_t					num_hops;
114
+	uint8_t					is_sharing_enabled;
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+	enum ta_xgmi_assigned_sdma_engine	sdma_engine;
116
+};
117
+
118
+struct psp_xgmi_topology_info {
119
+	uint32_t			num_nodes;
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+	struct psp_xgmi_node_info	nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
121
+};
122
+
123
+struct psp_asd_context {
124
+	bool			asd_initialized;
125
+	uint32_t		session_id;
126
+};
127
+
128
+struct psp_xgmi_context {
129
+	uint8_t				initialized;
130
+	uint32_t			session_id;
131
+	struct amdgpu_bo                *xgmi_shared_bo;
132
+	uint64_t                        xgmi_shared_mc_addr;
133
+	void                            *xgmi_shared_buf;
134
+	struct psp_xgmi_topology_info	top_info;
135
+};
136
+
137
+struct psp_ras_context {
138
+	/*ras fw*/
139
+	bool			ras_initialized;
140
+	uint32_t		session_id;
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+	struct amdgpu_bo	*ras_shared_bo;
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+	uint64_t		ras_shared_mc_addr;
143
+	void			*ras_shared_buf;
144
+	struct amdgpu_ras	*ras;
145
+};
146
+
147
+struct psp_hdcp_context {
148
+	bool			hdcp_initialized;
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+	uint32_t		session_id;
150
+	struct amdgpu_bo	*hdcp_shared_bo;
151
+	uint64_t		hdcp_shared_mc_addr;
152
+	void			*hdcp_shared_buf;
153
+	struct mutex		mutex;
154
+};
155
+
156
+struct psp_dtm_context {
157
+	bool			dtm_initialized;
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+	uint32_t		session_id;
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+	struct amdgpu_bo	*dtm_shared_bo;
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+	uint64_t		dtm_shared_mc_addr;
161
+	void			*dtm_shared_buf;
162
+	struct mutex		mutex;
163
+};
164
+
165
+struct psp_rap_context {
166
+	bool			rap_initialized;
167
+	uint32_t		session_id;
168
+	struct amdgpu_bo	*rap_shared_bo;
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+	uint64_t		rap_shared_mc_addr;
170
+	void			*rap_shared_buf;
171
+	struct mutex		mutex;
172
+};
173
+
174
+#define MEM_TRAIN_SYSTEM_SIGNATURE		0x54534942
175
+#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES	0x1000
176
+#define GDDR6_MEM_TRAINING_OFFSET		0x8000
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+/*Define the VRAM size that will be encroached by BIST training.*/
178
+#define GDDR6_MEM_TRAINING_ENCROACHED_SIZE	0x2000000
179
+
180
+enum psp_memory_training_init_flag {
181
+	PSP_MEM_TRAIN_NOT_SUPPORT	= 0x0,
182
+	PSP_MEM_TRAIN_SUPPORT		= 0x1,
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+	PSP_MEM_TRAIN_INIT_FAILED	= 0x2,
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+	PSP_MEM_TRAIN_RESERVE_SUCCESS	= 0x4,
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+	PSP_MEM_TRAIN_INIT_SUCCESS	= 0x8,
186
+};
187
+
188
+enum psp_memory_training_ops {
189
+	PSP_MEM_TRAIN_SEND_LONG_MSG	= 0x1,
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+	PSP_MEM_TRAIN_SAVE		= 0x2,
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+	PSP_MEM_TRAIN_RESTORE		= 0x4,
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+	PSP_MEM_TRAIN_SEND_SHORT_MSG	= 0x8,
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+	PSP_MEM_TRAIN_COLD_BOOT		= PSP_MEM_TRAIN_SEND_LONG_MSG,
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+	PSP_MEM_TRAIN_RESUME		= PSP_MEM_TRAIN_SEND_SHORT_MSG,
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+};
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+
197
+struct psp_memory_training_context {
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+	/*training data size*/
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+	u64 train_data_size;
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+	/*
201
+	 * sys_cache
202
+	 * cpu virtual address
203
+	 * system memory buffer that used to store the training data.
204
+	 */
205
+	void *sys_cache;
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+
207
+	/*vram offset of the p2c training data*/
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+	u64 p2c_train_data_offset;
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+
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+	/*vram offset of the c2p training data*/
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+	u64 c2p_train_data_offset;
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+	struct amdgpu_bo *c2p_bo;
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+
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+	enum psp_memory_training_init_flag init;
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+	u32 training_cnt;
78
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 };
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217
 
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 struct psp_context
..
..
@@ -83,11 +221,11 @@
83
221
 	struct psp_ring                 km_ring;
84
222
 	struct psp_gfx_cmd_resp		*cmd;
85
223
 
86
-	const struct psp_funcs 		*funcs;
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+	const struct psp_funcs		*funcs;
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225
 
88
-	/* fence buffer */
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-	struct amdgpu_bo 		*fw_pri_bo;
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-	uint64_t 			fw_pri_mc_addr;
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+	/* firmware buffer */
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+	struct amdgpu_bo		*fw_pri_bo;
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+	uint64_t			fw_pri_mc_addr;
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 	void				*fw_pri_buf;
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230
 
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 	/* sos firmware */
..
..
@@ -96,33 +234,73 @@
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 	uint32_t			sos_feature_version;
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 	uint32_t			sys_bin_size;
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 	uint32_t			sos_bin_size;
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+	uint32_t			toc_bin_size;
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+	uint32_t			kdb_bin_size;
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+	uint32_t			spl_bin_size;
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 	uint8_t				*sys_start_addr;
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 	uint8_t				*sos_start_addr;
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+	uint8_t				*toc_start_addr;
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+	uint8_t				*kdb_start_addr;
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+	uint8_t				*spl_start_addr;
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245
 
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 	/* tmr buffer */
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-	struct amdgpu_bo 		*tmr_bo;
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-	uint64_t 			tmr_mc_addr;
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-	void				*tmr_buf;
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+	struct amdgpu_bo		*tmr_bo;
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+	uint64_t			tmr_mc_addr;
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249
 
107
-	/* asd firmware and buffer */
250
+	/* asd firmware */
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251
 	const struct firmware		*asd_fw;
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 	uint32_t			asd_fw_version;
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 	uint32_t			asd_feature_version;
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 	uint32_t			asd_ucode_size;
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 	uint8_t				*asd_start_addr;
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-	struct amdgpu_bo 		*asd_shared_bo;
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-	uint64_t 			asd_shared_mc_addr;
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-	void				*asd_shared_buf;
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256
 
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 	/* fence buffer */
118
-	struct amdgpu_bo 		*fence_buf_bo;
119
-	uint64_t 			fence_buf_mc_addr;
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+	struct amdgpu_bo		*fence_buf_bo;
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+	uint64_t			fence_buf_mc_addr;
120
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 	void				*fence_buf;
121
261
 
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 	/* cmd buffer */
123
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 	struct amdgpu_bo		*cmd_buf_bo;
124
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 	uint64_t			cmd_buf_mc_addr;
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 	struct psp_gfx_cmd_resp		*cmd_buf_mem;
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+
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+	/* fence value associated with cmd buffer */
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+	atomic_t			fence_value;
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+	/* flag to mark whether gfx fw autoload is supported or not */
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+	bool				autoload_supported;
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+	/* flag to mark whether df cstate management centralized to PMFW */
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+	bool				pmfw_centralized_cstate_management;
273
+
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+	/* xgmi ta firmware and buffer */
275
+	const struct firmware		*ta_fw;
276
+	uint32_t			ta_fw_version;
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+	uint32_t			ta_xgmi_ucode_version;
278
+	uint32_t			ta_xgmi_ucode_size;
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+	uint8_t				*ta_xgmi_start_addr;
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+	uint32_t			ta_ras_ucode_version;
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+	uint32_t			ta_ras_ucode_size;
282
+	uint8_t				*ta_ras_start_addr;
283
+
284
+	uint32_t			ta_hdcp_ucode_version;
285
+	uint32_t			ta_hdcp_ucode_size;
286
+	uint8_t				*ta_hdcp_start_addr;
287
+
288
+	uint32_t			ta_dtm_ucode_version;
289
+	uint32_t			ta_dtm_ucode_size;
290
+	uint8_t				*ta_dtm_start_addr;
291
+
292
+	uint32_t			ta_rap_ucode_version;
293
+	uint32_t			ta_rap_ucode_size;
294
+	uint8_t				*ta_rap_start_addr;
295
+
296
+	struct psp_asd_context		asd_context;
297
+	struct psp_xgmi_context		xgmi_context;
298
+	struct psp_ras_context		ras;
299
+	struct psp_hdcp_context 	hdcp_context;
300
+	struct psp_dtm_context		dtm_context;
301
+	struct psp_rap_context		rap_context;
302
+	struct mutex			mutex;
303
+	struct psp_memory_training_context mem_train_ctx;
126
304
 };
127
305
 
128
306
 struct amdgpu_psp_funcs {
..
..
@@ -130,17 +308,17 @@
130
308
 					enum AMDGPU_UCODE_ID);
131
309
 };
132
310
 
133
-#define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type))
311
+
134
312
 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
135
313
 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
136
314
 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
137
315
 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
138
-#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
139
-		(psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
140
-#define psp_compare_sram_data(psp, ucode, type) \
141
-		(psp)->funcs->compare_sram_data((psp), (ucode), (type))
142
316
 #define psp_init_microcode(psp) \
143
317
 		((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
318
+#define psp_bootloader_load_kdb(psp) \
319
+		((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
320
+#define psp_bootloader_load_spl(psp) \
321
+		((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
144
322
 #define psp_bootloader_load_sysdrv(psp) \
145
323
 		((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
146
324
 #define psp_bootloader_load_sos(psp) \
..
..
@@ -149,6 +327,19 @@
149
327
 		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
150
328
 #define psp_mode1_reset(psp) \
151
329
 		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
330
+#define psp_mem_training(psp, ops) \
331
+	((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
332
+
333
+#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
334
+#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
335
+
336
+#define psp_load_usbc_pd_fw(psp, dma_addr) \
337
+	((psp)->funcs->load_usbc_pd_fw ? \
338
+	(psp)->funcs->load_usbc_pd_fw((psp), (dma_addr)) : -EINVAL)
339
+
340
+#define psp_read_usbc_pd_fw(psp, fw_ver) \
341
+	((psp)->funcs->read_usbc_pd_fw ? \
342
+	(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
152
343
 
153
344
 extern const struct amd_ip_funcs psp_ip_funcs;
154
345
 
..
..
@@ -157,7 +348,47 @@
157
348
 			uint32_t field_val, uint32_t mask, bool check_changed);
158
349
 
159
350
 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
351
+extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
160
352
 
161
353
 int psp_gpu_reset(struct amdgpu_device *adev);
354
+int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
355
+			uint64_t cmd_gpu_addr, int cmd_size);
162
356
 
357
+int psp_xgmi_initialize(struct psp_context *psp);
358
+int psp_xgmi_terminate(struct psp_context *psp);
359
+int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
360
+int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
361
+int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
362
+int psp_xgmi_get_topology_info(struct psp_context *psp,
363
+			       int number_devices,
364
+			       struct psp_xgmi_topology_info *topology);
365
+int psp_xgmi_set_topology_info(struct psp_context *psp,
366
+			       int number_devices,
367
+			       struct psp_xgmi_topology_info *topology);
368
+
369
+int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
370
+int psp_ras_enable_features(struct psp_context *psp,
371
+		union ta_ras_cmd_input *info, bool enable);
372
+int psp_ras_trigger_error(struct psp_context *psp,
373
+			  struct ta_ras_trigger_error_input *info);
374
+
375
+int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
376
+int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
377
+int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
378
+
379
+int psp_rlc_autoload_start(struct psp_context *psp);
380
+
381
+extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
382
+int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
383
+		uint32_t value);
384
+int psp_ring_cmd_submit(struct psp_context *psp,
385
+			uint64_t cmd_buf_mc_addr,
386
+			uint64_t fence_mc_addr,
387
+			int index);
388
+int psp_init_asd_microcode(struct psp_context *psp,
389
+			   const char *chip_name);
390
+int psp_init_sos_microcode(struct psp_context *psp,
391
+			   const char *chip_name);
392
+int psp_init_ta_microcode(struct psp_context *psp,
393
+			  const char *chip_name);
163
394
 #endif