add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
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@@ -38,7 +38,7 @@
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 #include <drm/drm_crtc_helper.h>
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 #include <drm/drm_fb_helper.h>
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 #include <drm/drm_plane_helper.h>
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-#include <drm/drm_fb_helper.h>
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+#include <drm/drm_probe_helper.h>
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 #include <linux/i2c.h>
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 #include <linux/i2c-algo-bit.h>
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 #include <linux/hrtimer.h>
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@@ -46,6 +46,7 @@
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 #include <drm/drm_dp_mst_helper.h>
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 #include "modules/inc/mod_freesync.h"
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+#include "amdgpu_dm_irq_params.h"
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 struct amdgpu_bo;
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 struct amdgpu_device;
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@@ -57,9 +58,8 @@
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 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
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 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
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 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
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-#define to_amdgpu_plane(x)	container_of(x, struct amdgpu_plane, base)
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-#define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base);
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+#define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base)
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 #define AMDGPU_MAX_HPD_PINS 6
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 #define AMDGPU_MAX_CRTCS 6
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@@ -295,13 +295,6 @@
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 			      uint16_t connector_object_id,
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 			      struct amdgpu_hpd *hpd,
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 			      struct amdgpu_router *router);
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-	/* it is used to enter or exit into free sync mode */
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-	int (*notify_freesync)(struct drm_device *dev, void *data,
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-			       struct drm_file *filp);
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-	/* it is used to allow enablement of freesync mode */
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-	int (*set_freesync_property)(struct drm_connector *connector,
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-				     struct drm_property *property,
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-				     uint64_t val);
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 };
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@@ -325,7 +318,7 @@
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 	struct card_info *atom_card_info;
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 	bool mode_config_initialized;
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 	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
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-	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
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+	struct drm_plane *planes[AMDGPU_MAX_PLANES];
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 	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
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 	/* DVI-I properties */
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 	struct drm_property *coherent_mode_property;
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@@ -339,8 +332,8 @@
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 	struct drm_property *audio_property;
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 	/* FMT dithering */
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 	struct drm_property *dither_property;
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-	/* maximum number of bits per channel for monitor color */
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-	struct drm_property *max_bpc_property;
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+	/* Adaptive Backlight Modulation (power feature) */
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+	struct drm_property *abm_level_property;
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 	/* hardcoded DFP edid from BIOS */
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 	struct edid *bios_hardcoded_edid;
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 	int bios_hardcoded_edid_size;
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@@ -412,6 +405,8 @@
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 	struct amdgpu_flip_work *pflip_works;
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 	enum amdgpu_flip_status pflip_status;
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 	int deferred_flip_completion;
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+	/* parameters access from DM IRQ handler */
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+	struct dm_irq_params dm_irq_params;
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 	/* pll sharing */
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 	struct amdgpu_atom_ss ss;
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 	bool ss_enabled;
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@@ -434,11 +429,6 @@
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 	int otg_inst;
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 	struct drm_pending_vblank_event *event;
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-};
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-
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-struct amdgpu_plane {
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-	struct drm_plane base;
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-	enum drm_plane_type plane_type;
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 };
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 struct amdgpu_encoder_atom_dig {
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@@ -481,6 +471,7 @@
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 struct amdgpu_connector_atom_dig {
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 	/* displayport */
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 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
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+	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
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 	u8 dp_sink_type;
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 	int dp_clock;
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 	int dp_lane_count;
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@@ -624,6 +615,11 @@
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 			     struct drm_display_mode *adjusted_mode);
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 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
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+bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
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+			bool in_vblank_irq, int *vpos,
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+			int *hpos, ktime_t *stime, ktime_t *etime,
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+			const struct drm_display_mode *mode);
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+
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 /* fbdev layer */
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 int amdgpu_fbdev_init(struct amdgpu_device *adev);
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 void amdgpu_fbdev_fini(struct amdgpu_device *adev);