hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
....@@ -29,11 +29,16 @@
2929 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1)
3030 /* bit set means context switch occured */
3131 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2)
32
+/* bit set means IB is preempted */
33
+#define AMDGPU_IB_PREEMPTED (1 << 3)
3234
3335 #define to_amdgpu_job(sched_job) \
3436 container_of((sched_job), struct amdgpu_job, base)
3537
38
+#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
39
+
3640 struct amdgpu_fence;
41
+enum amdgpu_ib_pool_type;
3742
3843 struct amdgpu_job {
3944 struct drm_sched_job base;
....@@ -43,8 +48,8 @@
4348 struct amdgpu_ib *ibs;
4449 struct dma_fence *fence; /* the hw fence */
4550 uint32_t preamble_status;
51
+ uint32_t preemption_status;
4652 uint32_t num_ibs;
47
- void *owner;
4853 bool vm_needs_flush;
4954 uint64_t vm_pd_addr;
5055 unsigned vmid;
....@@ -57,18 +62,19 @@
5762 /* user fence handling */
5863 uint64_t uf_addr;
5964 uint64_t uf_sequence;
60
-
6165 };
6266
6367 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
6468 struct amdgpu_job **job, struct amdgpu_vm *vm);
6569 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
66
- struct amdgpu_job **job);
67
-
70
+ enum amdgpu_ib_pool_type pool, struct amdgpu_job **job);
6871 void amdgpu_job_free_resources(struct amdgpu_job *job);
6972 void amdgpu_job_free(struct amdgpu_job *job);
7073 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
7174 void *owner, struct dma_fence **f);
7275 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
7376 struct dma_fence **fence);
77
+
78
+void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
79
+
7480 #endif