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29 | 29 | #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) |
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30 | 30 | /* bit set means context switch occured */ |
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31 | 31 | #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) |
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| 32 | +/* bit set means IB is preempted */ |
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| 33 | +#define AMDGPU_IB_PREEMPTED (1 << 3) |
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32 | 34 | |
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33 | 35 | #define to_amdgpu_job(sched_job) \ |
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34 | 36 | container_of((sched_job), struct amdgpu_job, base) |
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35 | 37 | |
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| 38 | +#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0) |
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| 39 | + |
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36 | 40 | struct amdgpu_fence; |
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| 41 | +enum amdgpu_ib_pool_type; |
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37 | 42 | |
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38 | 43 | struct amdgpu_job { |
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39 | 44 | struct drm_sched_job base; |
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43 | 48 | struct amdgpu_ib *ibs; |
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44 | 49 | struct dma_fence *fence; /* the hw fence */ |
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45 | 50 | uint32_t preamble_status; |
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| 51 | + uint32_t preemption_status; |
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46 | 52 | uint32_t num_ibs; |
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47 | | - void *owner; |
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48 | 53 | bool vm_needs_flush; |
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49 | 54 | uint64_t vm_pd_addr; |
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50 | 55 | unsigned vmid; |
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57 | 62 | /* user fence handling */ |
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58 | 63 | uint64_t uf_addr; |
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59 | 64 | uint64_t uf_sequence; |
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60 | | - |
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61 | 65 | }; |
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62 | 66 | |
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63 | 67 | int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, |
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64 | 68 | struct amdgpu_job **job, struct amdgpu_vm *vm); |
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65 | 69 | int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, |
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66 | | - struct amdgpu_job **job); |
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67 | | - |
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| 70 | + enum amdgpu_ib_pool_type pool, struct amdgpu_job **job); |
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68 | 71 | void amdgpu_job_free_resources(struct amdgpu_job *job); |
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69 | 72 | void amdgpu_job_free(struct amdgpu_job *job); |
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70 | 73 | int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, |
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71 | 74 | void *owner, struct dma_fence **f); |
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72 | 75 | int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, |
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73 | 76 | struct dma_fence **fence); |
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| 77 | + |
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| 78 | +void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched); |
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| 79 | + |
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74 | 80 | #endif |
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