hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
....@@ -24,34 +24,14 @@
2424 #ifndef __AMDGPU_GDS_H__
2525 #define __AMDGPU_GDS_H__
2626
27
-/* Because TTM request that alloacted buffer should be PAGE_SIZE aligned,
28
- * we should report GDS/GWS/OA size as PAGE_SIZE aligned
29
- * */
30
-#define AMDGPU_GDS_SHIFT 2
31
-#define AMDGPU_GWS_SHIFT PAGE_SHIFT
32
-#define AMDGPU_OA_SHIFT PAGE_SHIFT
33
-
3427 struct amdgpu_ring;
3528 struct amdgpu_bo;
3629
37
-struct amdgpu_gds_asic_info {
38
- uint32_t total_size;
39
- uint32_t gfx_partition_size;
40
- uint32_t cs_partition_size;
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-};
42
-
4330 struct amdgpu_gds {
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- struct amdgpu_gds_asic_info mem;
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- struct amdgpu_gds_asic_info gws;
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- struct amdgpu_gds_asic_info oa;
47
- /* At present, GDS, GWS and OA resources for gfx (graphics)
48
- * is always pre-allocated and available for graphics operation.
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- * Such resource is shared between all gfx clients.
50
- * TODO: move this operation to user space
51
- * */
52
- struct amdgpu_bo* gds_gfx_bo;
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- struct amdgpu_bo* gws_gfx_bo;
54
- struct amdgpu_bo* oa_gfx_bo;
31
+ uint32_t gds_size;
32
+ uint32_t gws_size;
33
+ uint32_t oa_size;
34
+ uint32_t gds_compute_max_wave_id;
5535 };
5636
5737 struct amdgpu_gds_reg_offset {