forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
....@@ -23,7 +23,7 @@
2323  * Authors: Dave Airlie
2424  *          Alex Deucher
2525  */
26
-#include <drm/drmP.h>
26
+
2727 #include <drm/amdgpu_drm.h>
2828 #include "amdgpu.h"
2929 #include "amdgpu_i2c.h"
....@@ -32,11 +32,13 @@
3232 #include "amdgpu_display.h"
3333 #include <asm/div64.h>
3434 
35
+#include <linux/pci.h>
3536 #include <linux/pm_runtime.h>
3637 #include <drm/drm_crtc_helper.h>
3738 #include <drm/drm_edid.h>
3839 #include <drm/drm_gem_framebuffer_helper.h>
3940 #include <drm/drm_fb_helper.h>
41
+#include <drm/drm_vblank.h>
4042 
4143 static void amdgpu_display_flip_callback(struct dma_fence *f,
4244 					 struct dma_fence_cb *cb)
....@@ -91,13 +93,13 @@
9193 	 * targeted by the flip
9294 	 */
9395 	if (amdgpu_crtc->enabled &&
94
-	    (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0,
96
+	    (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
9597 						&vpos, &hpos, NULL, NULL,
9698 						&crtc->hwmode)
9799 	     & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
98100 	    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
99101 	    (int)(work->target_vblank -
100
-		  amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) {
102
+		  amdgpu_get_vblank_counter_kms(crtc)) > 0) {
101103 		schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
102104 		return;
103105 	}
....@@ -150,7 +152,7 @@
150152 				struct drm_modeset_acquire_ctx *ctx)
151153 {
152154 	struct drm_device *dev = crtc->dev;
153
-	struct amdgpu_device *adev = dev->dev_private;
155
+	struct amdgpu_device *adev = drm_to_adev(dev);
154156 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
155157 	struct drm_gem_object *obj;
156158 	struct amdgpu_flip_work *work;
....@@ -188,10 +190,13 @@
188190 		goto cleanup;
189191 	}
190192 
191
-	r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
192
-	if (unlikely(r != 0)) {
193
-		DRM_ERROR("failed to pin new abo buffer before flip\n");
194
-		goto unreserve;
193
+	if (!adev->enable_virtual_display) {
194
+		r = amdgpu_bo_pin(new_abo,
195
+				  amdgpu_display_supported_domains(adev, new_abo->flags));
196
+		if (unlikely(r != 0)) {
197
+			DRM_ERROR("failed to pin new abo buffer before flip\n");
198
+			goto unreserve;
199
+		}
195200 	}
196201 
197202 	r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
....@@ -200,7 +205,7 @@
200205 		goto unpin;
201206 	}
202207 
203
-	r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl,
208
+	r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,
204209 					      &work->shared_count,
205210 					      &work->shared);
206211 	if (unlikely(r != 0)) {
....@@ -211,9 +216,10 @@
211216 	amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
212217 	amdgpu_bo_unreserve(new_abo);
213218 
214
-	work->base = amdgpu_bo_gpu_offset(new_abo);
219
+	if (!adev->enable_virtual_display)
220
+		work->base = amdgpu_bo_gpu_offset(new_abo);
215221 	work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
216
-		amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
222
+		amdgpu_get_vblank_counter_kms(crtc);
217223 
218224 	/* we borrow the event spin lock for protecting flip_wrok */
219225 	spin_lock_irqsave(&crtc->dev->event_lock, flags);
....@@ -242,9 +248,10 @@
242248 		goto cleanup;
243249 	}
244250 unpin:
245
-	if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) {
246
-		DRM_ERROR("failed to unpin new abo in error path\n");
247
-	}
251
+	if (!adev->enable_virtual_display)
252
+		if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
253
+			DRM_ERROR("failed to unpin new abo in error path\n");
254
+
248255 unreserve:
249256 	amdgpu_bo_unreserve(new_abo);
250257 
....@@ -285,7 +292,7 @@
285292 
286293 	pm_runtime_mark_last_busy(dev->dev);
287294 
288
-	adev = dev->dev_private;
295
+	adev = drm_to_adev(dev);
289296 	/* if we have active crtcs and we don't have a power ref,
290297 	   take the current one */
291298 	if (active && !adev->have_disp_power_ref) {
....@@ -364,11 +371,13 @@
364371 	struct amdgpu_connector *amdgpu_connector;
365372 	struct drm_encoder *encoder;
366373 	struct amdgpu_encoder *amdgpu_encoder;
374
+	struct drm_connector_list_iter iter;
367375 	uint32_t devices;
368376 	int i = 0;
369377 
378
+	drm_connector_list_iter_begin(dev, &iter);
370379 	DRM_INFO("AMDGPU Display Connectors\n");
371
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
380
+	drm_for_each_connector_iter(connector, &iter) {
372381 		amdgpu_connector = to_amdgpu_connector(connector);
373382 		DRM_INFO("Connector %d:\n", i);
374383 		DRM_INFO("  %s\n", connector->name);
....@@ -432,6 +441,7 @@
432441 		}
433442 		i++;
434443 	}
444
+	drm_connector_list_iter_end(&iter);
435445 }
436446 
437447 /**
....@@ -490,15 +500,38 @@
490500 	.create_handle = drm_gem_fb_create_handle,
491501 };
492502 
493
-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
503
+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
504
+					  uint64_t bo_flags)
494505 {
495506 	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
496507 
497508 #if defined(CONFIG_DRM_AMD_DC)
498
-	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
499
-	    adev->flags & AMD_IS_APU &&
500
-	    amdgpu_device_asic_has_dc_support(adev->asic_type))
501
-		domain |= AMDGPU_GEM_DOMAIN_GTT;
509
+	/*
510
+	 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
511
+	 * is not supported for this board. But this mapping is required
512
+	 * to avoid hang caused by placement of scanout BO in GTT on certain
513
+	 * APUs. So force the BO placement to VRAM in case this architecture
514
+	 * will not allow USWC mappings.
515
+	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
516
+	 */
517
+	if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
518
+	    amdgpu_bo_support_uswc(bo_flags) &&
519
+	    amdgpu_device_asic_has_dc_support(adev->asic_type)) {
520
+		switch (adev->asic_type) {
521
+		case CHIP_CARRIZO:
522
+		case CHIP_STONEY:
523
+			domain |= AMDGPU_GEM_DOMAIN_GTT;
524
+			break;
525
+		case CHIP_RAVEN:
526
+			/* enable S/G on PCO and RV2 */
527
+			if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
528
+			    (adev->apu_flags & AMD_APU_IS_PICASSO))
529
+				domain |= AMDGPU_GEM_DOMAIN_GTT;
530
+			break;
531
+		default:
532
+			break;
533
+		}
534
+	}
502535 #endif
503536 
504537 	return domain;
....@@ -544,14 +577,14 @@
544577 
545578 	amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
546579 	if (amdgpu_fb == NULL) {
547
-		drm_gem_object_put_unlocked(obj);
580
+		drm_gem_object_put(obj);
548581 		return ERR_PTR(-ENOMEM);
549582 	}
550583 
551584 	ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
552585 	if (ret) {
553586 		kfree(amdgpu_fb);
554
-		drm_gem_object_put_unlocked(obj);
587
+		drm_gem_object_put(obj);
555588 		return ERR_PTR(ret);
556589 	}
557590 
....@@ -586,51 +619,52 @@
586619 	int sz;
587620 
588621 	adev->mode_info.coherent_mode_property =
589
-		drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
622
+		drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
590623 	if (!adev->mode_info.coherent_mode_property)
591624 		return -ENOMEM;
592625 
593626 	adev->mode_info.load_detect_property =
594
-		drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
627
+		drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
595628 	if (!adev->mode_info.load_detect_property)
596629 		return -ENOMEM;
597630 
598
-	drm_mode_create_scaling_mode_property(adev->ddev);
631
+	drm_mode_create_scaling_mode_property(adev_to_drm(adev));
599632 
600633 	sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
601634 	adev->mode_info.underscan_property =
602
-		drm_property_create_enum(adev->ddev, 0,
603
-				    "underscan",
604
-				    amdgpu_underscan_enum_list, sz);
635
+		drm_property_create_enum(adev_to_drm(adev), 0,
636
+					 "underscan",
637
+					 amdgpu_underscan_enum_list, sz);
605638 
606639 	adev->mode_info.underscan_hborder_property =
607
-		drm_property_create_range(adev->ddev, 0,
608
-					"underscan hborder", 0, 128);
640
+		drm_property_create_range(adev_to_drm(adev), 0,
641
+					  "underscan hborder", 0, 128);
609642 	if (!adev->mode_info.underscan_hborder_property)
610643 		return -ENOMEM;
611644 
612645 	adev->mode_info.underscan_vborder_property =
613
-		drm_property_create_range(adev->ddev, 0,
614
-					"underscan vborder", 0, 128);
646
+		drm_property_create_range(adev_to_drm(adev), 0,
647
+					  "underscan vborder", 0, 128);
615648 	if (!adev->mode_info.underscan_vborder_property)
616649 		return -ENOMEM;
617650 
618651 	sz = ARRAY_SIZE(amdgpu_audio_enum_list);
619652 	adev->mode_info.audio_property =
620
-		drm_property_create_enum(adev->ddev, 0,
653
+		drm_property_create_enum(adev_to_drm(adev), 0,
621654 					 "audio",
622655 					 amdgpu_audio_enum_list, sz);
623656 
624657 	sz = ARRAY_SIZE(amdgpu_dither_enum_list);
625658 	adev->mode_info.dither_property =
626
-		drm_property_create_enum(adev->ddev, 0,
659
+		drm_property_create_enum(adev_to_drm(adev), 0,
627660 					 "dither",
628661 					 amdgpu_dither_enum_list, sz);
629662 
630663 	if (amdgpu_device_has_dc_support(adev)) {
631
-		adev->mode_info.max_bpc_property =
632
-			drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);
633
-		if (!adev->mode_info.max_bpc_property)
664
+		adev->mode_info.abm_level_property =
665
+			drm_property_create_range(adev_to_drm(adev), 0,
666
+						  "abm level", 0, 4);
667
+		if (!adev->mode_info.abm_level_property)
634668 			return -ENOMEM;
635669 	}
636670 
....@@ -668,7 +702,6 @@
668702 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
669703 	struct amdgpu_encoder *amdgpu_encoder;
670704 	struct drm_connector *connector;
671
-	struct amdgpu_connector *amdgpu_connector;
672705 	u32 src_v = 1, dst_v = 1;
673706 	u32 src_h = 1, dst_h = 1;
674707 
....@@ -680,7 +713,6 @@
680713 			continue;
681714 		amdgpu_encoder = to_amdgpu_encoder(encoder);
682715 		connector = amdgpu_get_connector_for_encoder(encoder);
683
-		amdgpu_connector = to_amdgpu_connector(connector);
684716 
685717 		/* set scaling */
686718 		if (amdgpu_encoder->rmx_type == RMX_OFF)
....@@ -781,7 +813,7 @@
781813 	int vbl_start, vbl_end, vtotal, ret = 0;
782814 	bool in_vbl = true;
783815 
784
-	struct amdgpu_device *adev = dev->dev_private;
816
+	struct amdgpu_device *adev = drm_to_adev(dev);
785817 
786818 	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
787819 
....@@ -858,7 +890,12 @@
858890 	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
859891 	if (in_vbl && (*vpos >= vbl_start)) {
860892 		vtotal = mode->crtc_vtotal;
861
-		*vpos = *vpos - vtotal;
893
+
894
+		/* With variable refresh rate displays the vpos can exceed
895
+		 * the vtotal value. Clamp to 0 to return -vbl_end instead
896
+		 * of guessing the remaining number of lines until scanout.
897
+		 */
898
+		*vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
862899 	}
863900 
864901 	/* Correct for shifted end of vbl at vbl_end. */
....@@ -889,3 +926,15 @@
889926 		return AMDGPU_CRTC_IRQ_NONE;
890927 	}
891928 }
929
+
930
+bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
931
+			bool in_vblank_irq, int *vpos,
932
+			int *hpos, ktime_t *stime, ktime_t *etime,
933
+			const struct drm_display_mode *mode)
934
+{
935
+	struct drm_device *dev = crtc->dev;
936
+	unsigned int pipe = crtc->index;
937
+
938
+	return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
939
+						  stime, etime, mode);
940
+}