forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
....@@ -20,14 +20,8 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  */
2222 
23
-#include <linux/module.h>
24
-#include <linux/fdtable.h>
25
-#include <linux/uaccess.h>
26
-#include <linux/firmware.h>
27
-#include <drm/drmP.h>
2823 #include "amdgpu.h"
2924 #include "amdgpu_amdkfd.h"
30
-#include "amdgpu_ucode.h"
3125 #include "gfx_v8_0.h"
3226 #include "gca/gfx_8_0_sh_mask.h"
3327 #include "gca/gfx_8_0_d.h"
....@@ -44,147 +38,6 @@
4438 	DRAIN_PIPE,
4539 	RESET_WAVES
4640 };
47
-
48
-struct vi_sdma_mqd;
49
-
50
-/*
51
- * Register access functions
52
- */
53
-
54
-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
55
-		uint32_t sh_mem_config,
56
-		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
57
-		uint32_t sh_mem_bases);
58
-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
59
-		unsigned int vmid);
60
-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
61
-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
62
-			uint32_t queue_id, uint32_t __user *wptr,
63
-			uint32_t wptr_shift, uint32_t wptr_mask,
64
-			struct mm_struct *mm);
65
-static int kgd_hqd_dump(struct kgd_dev *kgd,
66
-			uint32_t pipe_id, uint32_t queue_id,
67
-			uint32_t (**dump)[2], uint32_t *n_regs);
68
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
69
-			     uint32_t __user *wptr, struct mm_struct *mm);
70
-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
71
-			     uint32_t engine_id, uint32_t queue_id,
72
-			     uint32_t (**dump)[2], uint32_t *n_regs);
73
-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
74
-		uint32_t pipe_id, uint32_t queue_id);
75
-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
76
-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
77
-				enum kfd_preempt_type reset_type,
78
-				unsigned int utimeout, uint32_t pipe_id,
79
-				uint32_t queue_id);
80
-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
81
-				unsigned int utimeout);
82
-static int kgd_address_watch_disable(struct kgd_dev *kgd);
83
-static int kgd_address_watch_execute(struct kgd_dev *kgd,
84
-					unsigned int watch_point_id,
85
-					uint32_t cntl_val,
86
-					uint32_t addr_hi,
87
-					uint32_t addr_lo);
88
-static int kgd_wave_control_execute(struct kgd_dev *kgd,
89
-					uint32_t gfx_index_val,
90
-					uint32_t sq_cmd);
91
-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
92
-					unsigned int watch_point_id,
93
-					unsigned int reg_offset);
94
-
95
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
96
-		uint8_t vmid);
97
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
98
-		uint8_t vmid);
99
-static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
100
-static void set_scratch_backing_va(struct kgd_dev *kgd,
101
-					uint64_t va, uint32_t vmid);
102
-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
103
-		uint32_t page_table_base);
104
-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
105
-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
106
-
107
-/* Because of REG_GET_FIELD() being used, we put this function in the
108
- * asic specific file.
109
- */
110
-static int get_tile_config(struct kgd_dev *kgd,
111
-		struct tile_config *config)
112
-{
113
-	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
114
-
115
-	config->gb_addr_config = adev->gfx.config.gb_addr_config;
116
-	config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
117
-				MC_ARB_RAMCFG, NOOFBANK);
118
-	config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
119
-				MC_ARB_RAMCFG, NOOFRANKS);
120
-
121
-	config->tile_config_ptr = adev->gfx.config.tile_mode_array;
122
-	config->num_tile_configs =
123
-			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
124
-	config->macro_tile_config_ptr =
125
-			adev->gfx.config.macrotile_mode_array;
126
-	config->num_macro_tile_configs =
127
-			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
128
-
129
-	return 0;
130
-}
131
-
132
-static const struct kfd2kgd_calls kfd2kgd = {
133
-	.init_gtt_mem_allocation = alloc_gtt_mem,
134
-	.free_gtt_mem = free_gtt_mem,
135
-	.get_local_mem_info = get_local_mem_info,
136
-	.get_gpu_clock_counter = get_gpu_clock_counter,
137
-	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
138
-	.alloc_pasid = amdgpu_pasid_alloc,
139
-	.free_pasid = amdgpu_pasid_free,
140
-	.program_sh_mem_settings = kgd_program_sh_mem_settings,
141
-	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
142
-	.init_interrupts = kgd_init_interrupts,
143
-	.hqd_load = kgd_hqd_load,
144
-	.hqd_sdma_load = kgd_hqd_sdma_load,
145
-	.hqd_dump = kgd_hqd_dump,
146
-	.hqd_sdma_dump = kgd_hqd_sdma_dump,
147
-	.hqd_is_occupied = kgd_hqd_is_occupied,
148
-	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
149
-	.hqd_destroy = kgd_hqd_destroy,
150
-	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
151
-	.address_watch_disable = kgd_address_watch_disable,
152
-	.address_watch_execute = kgd_address_watch_execute,
153
-	.wave_control_execute = kgd_wave_control_execute,
154
-	.address_watch_get_offset = kgd_address_watch_get_offset,
155
-	.get_atc_vmid_pasid_mapping_pasid =
156
-			get_atc_vmid_pasid_mapping_pasid,
157
-	.get_atc_vmid_pasid_mapping_valid =
158
-			get_atc_vmid_pasid_mapping_valid,
159
-	.get_fw_version = get_fw_version,
160
-	.set_scratch_backing_va = set_scratch_backing_va,
161
-	.get_tile_config = get_tile_config,
162
-	.get_cu_info = get_cu_info,
163
-	.get_vram_usage = amdgpu_amdkfd_get_vram_usage,
164
-	.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
165
-	.acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
166
-	.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
167
-	.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
168
-	.set_vm_context_page_table_base = set_vm_context_page_table_base,
169
-	.alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
170
-	.free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
171
-	.map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
172
-	.unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
173
-	.sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
174
-	.map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
175
-	.restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
176
-	.invalidate_tlbs = invalidate_tlbs,
177
-	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
178
-	.submit_ib = amdgpu_amdkfd_submit_ib,
179
-	.get_vm_fault_info = amdgpu_amdkfd_gpuvm_get_vm_fault_info,
180
-	.gpu_recover = amdgpu_amdkfd_gpu_reset,
181
-	.set_compute_idle = amdgpu_amdkfd_set_compute_idle
182
-};
183
-
184
-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
185
-{
186
-	return (struct kfd2kgd_calls *)&kfd2kgd;
187
-}
18841 
18942 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
19043 {
....@@ -243,7 +96,7 @@
24396 	unlock_srbm(kgd);
24497 }
24598 
246
-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
99
+static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,
247100 					unsigned int vmid)
248101 {
249102 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
....@@ -281,20 +134,23 @@
281134 
282135 	lock_srbm(kgd, mec, pipe, 0, 0);
283136 
284
-	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);
137
+	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
138
+			CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
285139 
286140 	unlock_srbm(kgd);
287141 
288142 	return 0;
289143 }
290144 
291
-static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
145
+static inline uint32_t get_sdma_rlc_reg_offset(struct vi_sdma_mqd *m)
292146 {
293147 	uint32_t retval;
294148 
295149 	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
296150 		m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
297
-	pr_debug("kfd: sdma base address: 0x%x\n", retval);
151
+
152
+	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
153
+			m->sdma_engine_id, m->sdma_queue_id, retval);
298154 
299155 	return retval;
300156 }
....@@ -366,7 +222,7 @@
366222 			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
367223 	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
368224 
369
-	/* read_user_ptr may take the mm->mmap_sem.
225
+	/* read_user_ptr may take the mm->mmap_lock.
370226 	 * release srbm_mutex to avoid circular dependency between
371227 	 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
372228 	 */
....@@ -426,59 +282,51 @@
426282 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
427283 	struct vi_sdma_mqd *m;
428284 	unsigned long end_jiffies;
429
-	uint32_t sdma_base_addr;
285
+	uint32_t sdma_rlc_reg_offset;
430286 	uint32_t data;
431287 
432288 	m = get_sdma_mqd(mqd);
433
-	sdma_base_addr = get_sdma_base_addr(m);
434
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
289
+	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
290
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
435291 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
436292 
437293 	end_jiffies = msecs_to_jiffies(2000) + jiffies;
438294 	while (true) {
439
-		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
295
+		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
440296 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
441297 			break;
442
-		if (time_after(jiffies, end_jiffies))
298
+		if (time_after(jiffies, end_jiffies)) {
299
+			pr_err("SDMA RLC not idle in %s\n", __func__);
443300 			return -ETIME;
301
+		}
444302 		usleep_range(500, 1000);
445
-	}
446
-	if (m->sdma_engine_id) {
447
-		data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
448
-		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
449
-				RESUME_CTX, 0);
450
-		WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
451
-	} else {
452
-		data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
453
-		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
454
-				RESUME_CTX, 0);
455
-		WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
456303 	}
457304 
458305 	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
459306 			     ENABLE, 1);
460
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
461
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
307
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
308
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
309
+				m->sdmax_rlcx_rb_rptr);
462310 
463311 	if (read_user_wptr(mm, wptr, data))
464
-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
312
+		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
465313 	else
466
-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
314
+		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
467315 		       m->sdmax_rlcx_rb_rptr);
468316 
469
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
317
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
470318 				m->sdmax_rlcx_virtual_addr);
471
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
472
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
319
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
320
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
473321 			m->sdmax_rlcx_rb_base_hi);
474
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
322
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
475323 			m->sdmax_rlcx_rb_rptr_addr_lo);
476
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
324
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
477325 			m->sdmax_rlcx_rb_rptr_addr_hi);
478326 
479327 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
480328 			     RB_ENABLE, 1);
481
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
329
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
482330 
483331 	return 0;
484332 }
....@@ -545,13 +393,13 @@
545393 {
546394 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
547395 	struct vi_sdma_mqd *m;
548
-	uint32_t sdma_base_addr;
396
+	uint32_t sdma_rlc_reg_offset;
549397 	uint32_t sdma_rlc_rb_cntl;
550398 
551399 	m = get_sdma_mqd(mqd);
552
-	sdma_base_addr = get_sdma_base_addr(m);
400
+	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
553401 
554
-	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
402
+	sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
555403 
556404 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
557405 		return true;
....@@ -571,7 +419,7 @@
571419 	int retry;
572420 	struct vi_mqd *m = get_mqd(mqd);
573421 
574
-	if (adev->in_gpu_reset)
422
+	if (amdgpu_in_reset(adev))
575423 		return -EIO;
576424 
577425 	acquire_queue(kgd, pipe_id, queue_id);
....@@ -669,54 +517,48 @@
669517 {
670518 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
671519 	struct vi_sdma_mqd *m;
672
-	uint32_t sdma_base_addr;
520
+	uint32_t sdma_rlc_reg_offset;
673521 	uint32_t temp;
674522 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
675523 
676524 	m = get_sdma_mqd(mqd);
677
-	sdma_base_addr = get_sdma_base_addr(m);
525
+	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
678526 
679
-	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
527
+	temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
680528 	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
681
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
529
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
682530 
683531 	while (true) {
684
-		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
532
+		temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
685533 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
686534 			break;
687
-		if (time_after(jiffies, end_jiffies))
535
+		if (time_after(jiffies, end_jiffies)) {
536
+			pr_err("SDMA RLC not idle in %s\n", __func__);
688537 			return -ETIME;
538
+		}
689539 		usleep_range(500, 1000);
690540 	}
691541 
692
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
693
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
694
-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
542
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
543
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
544
+		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
695545 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
696546 
697
-	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
547
+	m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
698548 
699549 	return 0;
700550 }
701551 
702
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
703
-							uint8_t vmid)
552
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
553
+					uint8_t vmid, uint16_t *p_pasid)
704554 {
705
-	uint32_t reg;
555
+	uint32_t value;
706556 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
707557 
708
-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
709
-	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
710
-}
558
+	value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
559
+	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
711560 
712
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
713
-								uint8_t vmid)
714
-{
715
-	uint32_t reg;
716
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
717
-
718
-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
719
-	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
561
+	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
720562 }
721563 
722564 static int kgd_address_watch_disable(struct kgd_dev *kgd)
....@@ -775,65 +617,8 @@
775617 	unlock_srbm(kgd);
776618 }
777619 
778
-static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
779
-{
780
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
781
-	const union amdgpu_firmware_header *hdr;
782
-
783
-	switch (type) {
784
-	case KGD_ENGINE_PFP:
785
-		hdr = (const union amdgpu_firmware_header *)
786
-						adev->gfx.pfp_fw->data;
787
-		break;
788
-
789
-	case KGD_ENGINE_ME:
790
-		hdr = (const union amdgpu_firmware_header *)
791
-						adev->gfx.me_fw->data;
792
-		break;
793
-
794
-	case KGD_ENGINE_CE:
795
-		hdr = (const union amdgpu_firmware_header *)
796
-						adev->gfx.ce_fw->data;
797
-		break;
798
-
799
-	case KGD_ENGINE_MEC1:
800
-		hdr = (const union amdgpu_firmware_header *)
801
-						adev->gfx.mec_fw->data;
802
-		break;
803
-
804
-	case KGD_ENGINE_MEC2:
805
-		hdr = (const union amdgpu_firmware_header *)
806
-						adev->gfx.mec2_fw->data;
807
-		break;
808
-
809
-	case KGD_ENGINE_RLC:
810
-		hdr = (const union amdgpu_firmware_header *)
811
-						adev->gfx.rlc_fw->data;
812
-		break;
813
-
814
-	case KGD_ENGINE_SDMA1:
815
-		hdr = (const union amdgpu_firmware_header *)
816
-						adev->sdma.instance[0].fw->data;
817
-		break;
818
-
819
-	case KGD_ENGINE_SDMA2:
820
-		hdr = (const union amdgpu_firmware_header *)
821
-						adev->sdma.instance[1].fw->data;
822
-		break;
823
-
824
-	default:
825
-		return 0;
826
-	}
827
-
828
-	if (hdr == NULL)
829
-		return 0;
830
-
831
-	/* Only 12 bit in use*/
832
-	return hdr->common.ucode_version;
833
-}
834
-
835620 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
836
-		uint32_t page_table_base)
621
+		uint64_t page_table_base)
837622 {
838623 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
839624 
....@@ -841,44 +626,28 @@
841626 		pr_err("trying to set page table base for wrong VMID\n");
842627 		return;
843628 	}
844
-	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
629
+	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
630
+			lower_32_bits(page_table_base));
845631 }
846632 
847
-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
848
-{
849
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
850
-	int vmid;
851
-	unsigned int tmp;
852
-
853
-	if (adev->in_gpu_reset)
854
-		return -EIO;
855
-
856
-	for (vmid = 0; vmid < 16; vmid++) {
857
-		if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
858
-			continue;
859
-
860
-		tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
861
-		if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
862
-			(tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
863
-			WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
864
-			RREG32(mmVM_INVALIDATE_RESPONSE);
865
-			break;
866
-		}
867
-	}
868
-
869
-	return 0;
870
-}
871
-
872
-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
873
-{
874
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
875
-
876
-	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
877
-		pr_err("non kfd vmid %d\n", vmid);
878
-		return -EINVAL;
879
-	}
880
-
881
-	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
882
-	RREG32(mmVM_INVALIDATE_RESPONSE);
883
-	return 0;
884
-}
633
+const struct kfd2kgd_calls gfx_v8_kfd2kgd = {
634
+	.program_sh_mem_settings = kgd_program_sh_mem_settings,
635
+	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
636
+	.init_interrupts = kgd_init_interrupts,
637
+	.hqd_load = kgd_hqd_load,
638
+	.hqd_sdma_load = kgd_hqd_sdma_load,
639
+	.hqd_dump = kgd_hqd_dump,
640
+	.hqd_sdma_dump = kgd_hqd_sdma_dump,
641
+	.hqd_is_occupied = kgd_hqd_is_occupied,
642
+	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
643
+	.hqd_destroy = kgd_hqd_destroy,
644
+	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
645
+	.address_watch_disable = kgd_address_watch_disable,
646
+	.address_watch_execute = kgd_address_watch_execute,
647
+	.wave_control_execute = kgd_wave_control_execute,
648
+	.address_watch_get_offset = kgd_address_watch_get_offset,
649
+	.get_atc_vmid_pasid_mapping_info =
650
+			get_atc_vmid_pasid_mapping_info,
651
+	.set_scratch_backing_va = set_scratch_backing_va,
652
+	.set_vm_context_page_table_base = set_vm_context_page_table_base,
653
+};