forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
....@@ -20,15 +20,10 @@
2020  * OTHER DEALINGS IN THE SOFTWARE.
2121  */
2222 
23
-#include <linux/fdtable.h>
24
-#include <linux/uaccess.h>
25
-#include <linux/firmware.h>
26
-#include <drm/drmP.h>
2723 #include "amdgpu.h"
2824 #include "amdgpu_amdkfd.h"
2925 #include "cikd.h"
3026 #include "cik_sdma.h"
31
-#include "amdgpu_ucode.h"
3227 #include "gfx_v7_0.h"
3328 #include "gca/gfx_7_2_d.h"
3429 #include "gca/gfx_7_2_enum.h"
....@@ -87,147 +82,6 @@
8782 	float f32All;
8883 };
8984 
90
-/*
91
- * Register access functions
92
- */
93
-
94
-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
95
-		uint32_t sh_mem_config,	uint32_t sh_mem_ape1_base,
96
-		uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
97
-
98
-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
99
-					unsigned int vmid);
100
-
101
-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
102
-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
103
-			uint32_t queue_id, uint32_t __user *wptr,
104
-			uint32_t wptr_shift, uint32_t wptr_mask,
105
-			struct mm_struct *mm);
106
-static int kgd_hqd_dump(struct kgd_dev *kgd,
107
-			uint32_t pipe_id, uint32_t queue_id,
108
-			uint32_t (**dump)[2], uint32_t *n_regs);
109
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
110
-			     uint32_t __user *wptr, struct mm_struct *mm);
111
-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
112
-			     uint32_t engine_id, uint32_t queue_id,
113
-			     uint32_t (**dump)[2], uint32_t *n_regs);
114
-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
115
-				uint32_t pipe_id, uint32_t queue_id);
116
-
117
-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
118
-				enum kfd_preempt_type reset_type,
119
-				unsigned int utimeout, uint32_t pipe_id,
120
-				uint32_t queue_id);
121
-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
122
-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
123
-				unsigned int utimeout);
124
-static int kgd_address_watch_disable(struct kgd_dev *kgd);
125
-static int kgd_address_watch_execute(struct kgd_dev *kgd,
126
-					unsigned int watch_point_id,
127
-					uint32_t cntl_val,
128
-					uint32_t addr_hi,
129
-					uint32_t addr_lo);
130
-static int kgd_wave_control_execute(struct kgd_dev *kgd,
131
-					uint32_t gfx_index_val,
132
-					uint32_t sq_cmd);
133
-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
134
-					unsigned int watch_point_id,
135
-					unsigned int reg_offset);
136
-
137
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
138
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
139
-							uint8_t vmid);
140
-
141
-static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
142
-static void set_scratch_backing_va(struct kgd_dev *kgd,
143
-					uint64_t va, uint32_t vmid);
144
-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
145
-		uint32_t page_table_base);
146
-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
147
-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
148
-static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd);
149
-
150
-/* Because of REG_GET_FIELD() being used, we put this function in the
151
- * asic specific file.
152
- */
153
-static int get_tile_config(struct kgd_dev *kgd,
154
-		struct tile_config *config)
155
-{
156
-	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
157
-
158
-	config->gb_addr_config = adev->gfx.config.gb_addr_config;
159
-	config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
160
-				MC_ARB_RAMCFG, NOOFBANK);
161
-	config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
162
-				MC_ARB_RAMCFG, NOOFRANKS);
163
-
164
-	config->tile_config_ptr = adev->gfx.config.tile_mode_array;
165
-	config->num_tile_configs =
166
-			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
167
-	config->macro_tile_config_ptr =
168
-			adev->gfx.config.macrotile_mode_array;
169
-	config->num_macro_tile_configs =
170
-			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
171
-
172
-	return 0;
173
-}
174
-
175
-static const struct kfd2kgd_calls kfd2kgd = {
176
-	.init_gtt_mem_allocation = alloc_gtt_mem,
177
-	.free_gtt_mem = free_gtt_mem,
178
-	.get_local_mem_info = get_local_mem_info,
179
-	.get_gpu_clock_counter = get_gpu_clock_counter,
180
-	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
181
-	.alloc_pasid = amdgpu_pasid_alloc,
182
-	.free_pasid = amdgpu_pasid_free,
183
-	.program_sh_mem_settings = kgd_program_sh_mem_settings,
184
-	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
185
-	.init_interrupts = kgd_init_interrupts,
186
-	.hqd_load = kgd_hqd_load,
187
-	.hqd_sdma_load = kgd_hqd_sdma_load,
188
-	.hqd_dump = kgd_hqd_dump,
189
-	.hqd_sdma_dump = kgd_hqd_sdma_dump,
190
-	.hqd_is_occupied = kgd_hqd_is_occupied,
191
-	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
192
-	.hqd_destroy = kgd_hqd_destroy,
193
-	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
194
-	.address_watch_disable = kgd_address_watch_disable,
195
-	.address_watch_execute = kgd_address_watch_execute,
196
-	.wave_control_execute = kgd_wave_control_execute,
197
-	.address_watch_get_offset = kgd_address_watch_get_offset,
198
-	.get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
199
-	.get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
200
-	.get_fw_version = get_fw_version,
201
-	.set_scratch_backing_va = set_scratch_backing_va,
202
-	.get_tile_config = get_tile_config,
203
-	.get_cu_info = get_cu_info,
204
-	.get_vram_usage = amdgpu_amdkfd_get_vram_usage,
205
-	.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
206
-	.acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
207
-	.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
208
-	.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
209
-	.set_vm_context_page_table_base = set_vm_context_page_table_base,
210
-	.alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
211
-	.free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu,
212
-	.map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu,
213
-	.unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu,
214
-	.sync_memory = amdgpu_amdkfd_gpuvm_sync_memory,
215
-	.map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel,
216
-	.restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos,
217
-	.invalidate_tlbs = invalidate_tlbs,
218
-	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
219
-	.submit_ib = amdgpu_amdkfd_submit_ib,
220
-	.get_vm_fault_info = amdgpu_amdkfd_gpuvm_get_vm_fault_info,
221
-	.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
222
-	.gpu_recover = amdgpu_amdkfd_gpu_reset,
223
-	.set_compute_idle = amdgpu_amdkfd_set_compute_idle
224
-};
225
-
226
-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
227
-{
228
-	return (struct kfd2kgd_calls *)&kfd2kgd;
229
-}
230
-
23185 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
23286 {
23387 	return (struct amdgpu_device *)kgd;
....@@ -285,7 +139,7 @@
285139 	unlock_srbm(kgd);
286140 }
287141 
288
-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
142
+static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,
289143 					unsigned int vmid)
290144 {
291145 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
....@@ -330,14 +184,15 @@
330184 	return 0;
331185 }
332186 
333
-static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
187
+static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)
334188 {
335189 	uint32_t retval;
336190 
337191 	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
338192 			m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
339193 
340
-	pr_debug("kfd: sdma base address: 0x%x\n", retval);
194
+	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
195
+			m->sdma_engine_id, m->sdma_queue_id, retval);
341196 
342197 	return retval;
343198 }
....@@ -380,7 +235,7 @@
380235 			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
381236 	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
382237 
383
-	/* read_user_ptr may take the mm->mmap_sem.
238
+	/* read_user_ptr may take the mm->mmap_lock.
384239 	 * release srbm_mutex to avoid circular dependency between
385240 	 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
386241 	 */
....@@ -440,60 +295,52 @@
440295 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
441296 	struct cik_sdma_rlc_registers *m;
442297 	unsigned long end_jiffies;
443
-	uint32_t sdma_base_addr;
298
+	uint32_t sdma_rlc_reg_offset;
444299 	uint32_t data;
445300 
446301 	m = get_sdma_mqd(mqd);
447
-	sdma_base_addr = get_sdma_base_addr(m);
302
+	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
448303 
449
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
304
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
450305 		m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
451306 
452307 	end_jiffies = msecs_to_jiffies(2000) + jiffies;
453308 	while (true) {
454
-		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
309
+		data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
455310 		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
456311 			break;
457
-		if (time_after(jiffies, end_jiffies))
312
+		if (time_after(jiffies, end_jiffies)) {
313
+			pr_err("SDMA RLC not idle in %s\n", __func__);
458314 			return -ETIME;
315
+		}
459316 		usleep_range(500, 1000);
460
-	}
461
-	if (m->sdma_engine_id) {
462
-		data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
463
-		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
464
-				RESUME_CTX, 0);
465
-		WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
466
-	} else {
467
-		data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
468
-		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
469
-				RESUME_CTX, 0);
470
-		WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
471317 	}
472318 
473319 	data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
474320 			     ENABLE, 1);
475
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
476
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
321
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
322
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
323
+				m->sdma_rlc_rb_rptr);
477324 
478325 	if (read_user_wptr(mm, wptr, data))
479
-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
326
+		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
480327 	else
481
-		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
328
+		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
482329 		       m->sdma_rlc_rb_rptr);
483330 
484
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
331
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
485332 				m->sdma_rlc_virtual_addr);
486
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
487
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
333
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
334
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
488335 			m->sdma_rlc_rb_base_hi);
489
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
336
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
490337 			m->sdma_rlc_rb_rptr_addr_lo);
491
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
338
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
492339 			m->sdma_rlc_rb_rptr_addr_hi);
493340 
494341 	data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
495342 			     RB_ENABLE, 1);
496
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
343
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
497344 
498345 	return 0;
499346 }
....@@ -551,13 +398,13 @@
551398 {
552399 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
553400 	struct cik_sdma_rlc_registers *m;
554
-	uint32_t sdma_base_addr;
401
+	uint32_t sdma_rlc_reg_offset;
555402 	uint32_t sdma_rlc_rb_cntl;
556403 
557404 	m = get_sdma_mqd(mqd);
558
-	sdma_base_addr = get_sdma_base_addr(m);
405
+	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
559406 
560
-	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
407
+	sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
561408 
562409 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
563410 		return true;
....@@ -576,7 +423,7 @@
576423 	unsigned long flags, end_jiffies;
577424 	int retry;
578425 
579
-	if (adev->in_gpu_reset)
426
+	if (amdgpu_in_reset(adev))
580427 		return -EIO;
581428 
582429 	acquire_queue(kgd, pipe_id, queue_id);
....@@ -672,32 +519,34 @@
672519 {
673520 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
674521 	struct cik_sdma_rlc_registers *m;
675
-	uint32_t sdma_base_addr;
522
+	uint32_t sdma_rlc_reg_offset;
676523 	uint32_t temp;
677524 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
678525 
679526 	m = get_sdma_mqd(mqd);
680
-	sdma_base_addr = get_sdma_base_addr(m);
527
+	sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
681528 
682
-	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
529
+	temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
683530 	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
684
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
531
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
685532 
686533 	while (true) {
687
-		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
534
+		temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
688535 		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
689536 			break;
690
-		if (time_after(jiffies, end_jiffies))
537
+		if (time_after(jiffies, end_jiffies)) {
538
+			pr_err("SDMA RLC not idle in %s\n", __func__);
691539 			return -ETIME;
540
+		}
692541 		usleep_range(500, 1000);
693542 	}
694543 
695
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
696
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
697
-		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
544
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
545
+	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
546
+		RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
698547 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
699548 
700
-	m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
549
+	m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
701550 
702551 	return 0;
703552 }
....@@ -785,24 +634,16 @@
785634 	return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
786635 }
787636 
788
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
789
-							uint8_t vmid)
637
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
638
+					uint8_t vmid, uint16_t *p_pasid)
790639 {
791
-	uint32_t reg;
640
+	uint32_t value;
792641 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
793642 
794
-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
795
-	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
796
-}
643
+	value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
644
+	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
797645 
798
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
799
-								uint8_t vmid)
800
-{
801
-	uint32_t reg;
802
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
803
-
804
-	reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
805
-	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
646
+	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
806647 }
807648 
808649 static void set_scratch_backing_va(struct kgd_dev *kgd,
....@@ -815,65 +656,8 @@
815656 	unlock_srbm(kgd);
816657 }
817658 
818
-static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
819
-{
820
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
821
-	const union amdgpu_firmware_header *hdr;
822
-
823
-	switch (type) {
824
-	case KGD_ENGINE_PFP:
825
-		hdr = (const union amdgpu_firmware_header *)
826
-						adev->gfx.pfp_fw->data;
827
-		break;
828
-
829
-	case KGD_ENGINE_ME:
830
-		hdr = (const union amdgpu_firmware_header *)
831
-						adev->gfx.me_fw->data;
832
-		break;
833
-
834
-	case KGD_ENGINE_CE:
835
-		hdr = (const union amdgpu_firmware_header *)
836
-						adev->gfx.ce_fw->data;
837
-		break;
838
-
839
-	case KGD_ENGINE_MEC1:
840
-		hdr = (const union amdgpu_firmware_header *)
841
-						adev->gfx.mec_fw->data;
842
-		break;
843
-
844
-	case KGD_ENGINE_MEC2:
845
-		hdr = (const union amdgpu_firmware_header *)
846
-						adev->gfx.mec2_fw->data;
847
-		break;
848
-
849
-	case KGD_ENGINE_RLC:
850
-		hdr = (const union amdgpu_firmware_header *)
851
-						adev->gfx.rlc_fw->data;
852
-		break;
853
-
854
-	case KGD_ENGINE_SDMA1:
855
-		hdr = (const union amdgpu_firmware_header *)
856
-						adev->sdma.instance[0].fw->data;
857
-		break;
858
-
859
-	case KGD_ENGINE_SDMA2:
860
-		hdr = (const union amdgpu_firmware_header *)
861
-						adev->sdma.instance[1].fw->data;
862
-		break;
863
-
864
-	default:
865
-		return 0;
866
-	}
867
-
868
-	if (hdr == NULL)
869
-		return 0;
870
-
871
-	/* Only 12 bit in use*/
872
-	return hdr->common.ucode_version;
873
-}
874
-
875659 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
876
-			uint32_t page_table_base)
660
+			uint64_t page_table_base)
877661 {
878662 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
879663 
....@@ -881,46 +665,8 @@
881665 		pr_err("trying to set page table base for wrong VMID\n");
882666 		return;
883667 	}
884
-	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base);
885
-}
886
-
887
-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
888
-{
889
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
890
-	int vmid;
891
-	unsigned int tmp;
892
-
893
-	if (adev->in_gpu_reset)
894
-		return -EIO;
895
-
896
-	for (vmid = 0; vmid < 16; vmid++) {
897
-		if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
898
-			continue;
899
-
900
-		tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
901
-		if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
902
-			(tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
903
-			WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
904
-			RREG32(mmVM_INVALIDATE_RESPONSE);
905
-			break;
906
-		}
907
-	}
908
-
909
-	return 0;
910
-}
911
-
912
-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
913
-{
914
-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
915
-
916
-	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
917
-		pr_err("non kfd vmid\n");
918
-		return 0;
919
-	}
920
-
921
-	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
922
-	RREG32(mmVM_INVALIDATE_RESPONSE);
923
-	return 0;
668
+	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
669
+		lower_32_bits(page_table_base));
924670 }
925671 
926672  /**
....@@ -938,3 +684,25 @@
938684 
939685 	return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
940686 }
687
+
688
+const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
689
+	.program_sh_mem_settings = kgd_program_sh_mem_settings,
690
+	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
691
+	.init_interrupts = kgd_init_interrupts,
692
+	.hqd_load = kgd_hqd_load,
693
+	.hqd_sdma_load = kgd_hqd_sdma_load,
694
+	.hqd_dump = kgd_hqd_dump,
695
+	.hqd_sdma_dump = kgd_hqd_sdma_dump,
696
+	.hqd_is_occupied = kgd_hqd_is_occupied,
697
+	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
698
+	.hqd_destroy = kgd_hqd_destroy,
699
+	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
700
+	.address_watch_disable = kgd_address_watch_disable,
701
+	.address_watch_execute = kgd_address_watch_execute,
702
+	.wave_control_execute = kgd_wave_control_execute,
703
+	.address_watch_get_offset = kgd_address_watch_get_offset,
704
+	.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
705
+	.set_scratch_backing_va = set_scratch_backing_va,
706
+	.set_vm_context_page_table_base = set_vm_context_page_table_base,
707
+	.read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
708
+};