add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpio/gpio-wcove.c
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@@ -1,34 +1,26 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * Intel Whiskey Cove PMIC GPIO Driver
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  *
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  * This driver is written based on gpio-crystalcove.c
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  *
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  * Copyright (C) 2016 Intel Corporation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License version
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- * 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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9
 
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 #include <linux/bitops.h>
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-#include <linux/module.h>
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-#include <linux/interrupt.h>
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 #include <linux/gpio/driver.h>
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+#include <linux/interrupt.h>
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 #include <linux/mfd/intel_soc_pmic.h>
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+#include <linux/module.h>
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 #include <linux/platform_device.h>
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 #include <linux/regmap.h>
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 #include <linux/seq_file.h>
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 /*
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  * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
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- * Bank 0: Pin 0 - 6
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- * Bank 1: Pin 7 - 10
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- * Bank 2: Pin 11 -12
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+ * Bank 0: Pin  0 - 6
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+ * Bank 1: Pin  7 - 10
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+ * Bank 2: Pin 11 - 12
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  * Each pin has one output control register and one input control register.
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  */
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 #define BANK0_NR_PINS		7
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@@ -75,8 +67,8 @@
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 #define CTLO_RVAL_50KDOWN	(2 << 1)
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 #define CTLO_RVAL_50KUP		(3 << 1)
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-#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
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-#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)
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+#define CTLO_INPUT_SET		(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
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+#define CTLO_OUTPUT_SET		(CTLO_DIR_OUT | CTLO_INPUT_SET)
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 enum ctrl_register {
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 	CTRL_IN,
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@@ -105,7 +97,7 @@
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 	bool set_irq_mask;
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 };
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-static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type)
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+static inline int to_reg(int gpio, enum ctrl_register reg_type)
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 {
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 	unsigned int reg;
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@@ -178,13 +170,16 @@
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 	int ret, reg = to_reg(gpio, CTRL_OUT);
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 	if (reg < 0)
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-		return 0;
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+		return GPIO_LINE_DIRECTION_OUT;
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 	ret = regmap_read(wg->regmap, reg, &val);
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 	if (ret)
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 		return ret;
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-	return !(val & CTLO_DIR_OUT);
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+	if (val & CTLO_DIR_OUT)
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+		return GPIO_LINE_DIRECTION_OUT;
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+
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+	return GPIO_LINE_DIRECTION_IN;
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183
 }
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184
 
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 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
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@@ -203,8 +198,7 @@
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 	return val & 0x1;
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 }
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200
 
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-static void wcove_gpio_set(struct gpio_chip *chip,
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-				 unsigned int gpio, int value)
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+static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
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 {
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 	struct wcove_gpio *wg = gpiochip_get_data(chip);
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 	int reg = to_reg(gpio, CTRL_OUT);
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@@ -406,6 +400,7 @@
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 	struct wcove_gpio *wg;
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 	int virq, ret, irq;
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 	struct device *dev;
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+	struct gpio_irq_chip *girq;
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404
 
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 	/*
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 	 * This gpio platform device is created by a mfd device (see
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@@ -448,33 +443,34 @@
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 	wg->dev = dev;
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 	wg->regmap = pmic->regmap;
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-	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
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-	if (ret) {
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-		dev_err(dev, "Failed to add gpiochip: %d\n", ret);
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-		return ret;
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-	}
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-
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-	ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0,
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-					  handle_simple_irq, IRQ_TYPE_NONE);
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-	if (ret) {
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-		dev_err(dev, "Failed to add irqchip: %d\n", ret);
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-		return ret;
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-	}
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-
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 	virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
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 	if (virq < 0) {
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 		dev_err(dev, "Failed to get virq by irq %d\n", irq);
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 		return virq;
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 	}
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-	ret = devm_request_threaded_irq(dev, virq, NULL,
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-		wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
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+	girq = &wg->chip.irq;
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+	girq->chip = &wcove_irqchip;
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+	/* This will let us handle the parent IRQ in the driver */
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+	girq->parent_handler = NULL;
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+	girq->num_parents = 0;
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+	girq->parents = NULL;
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+	girq->default_type = IRQ_TYPE_NONE;
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+	girq->handler = handle_simple_irq;
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+	girq->threaded = true;
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+
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+	ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler,
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+					IRQF_ONESHOT, pdev->name, wg);
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 	if (ret) {
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 		dev_err(dev, "Failed to request irq %d\n", virq);
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 		return ret;
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 	}
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-	gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
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+	ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
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+	if (ret) {
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+		dev_err(dev, "Failed to add gpiochip: %d\n", ret);
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+		return ret;
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+	}
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 	/* Enable GPIO0 interrupts */
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 	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,