hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/gpio/gpio-rcar.c
....@@ -1,17 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23 * Renesas R-Car GPIO Support
34 *
45 * Copyright (C) 2014 Renesas Electronics Corporation
56 * Copyright (C) 2013 Magnus Damm
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License as published by
9
- * the Free Software Foundation; either version 2 of the License
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
- * GNU General Public License for more details.
157 */
168
179 #include <linux/err.h>
....@@ -43,11 +35,12 @@
4335 struct gpio_rcar_priv {
4436 void __iomem *base;
4537 spinlock_t lock;
46
- struct platform_device *pdev;
38
+ struct device *dev;
4739 struct gpio_chip gpio_chip;
4840 struct irq_chip irq_chip;
4941 unsigned int irq_parent;
5042 atomic_t wakeup_path;
43
+ bool has_outdtsel;
5144 bool has_both_edge_trigger;
5245 struct gpio_rcar_bank_info bank_info;
5346 };
....@@ -63,6 +56,7 @@
6356 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
6457 #define EDGLEVEL 0x24 /* Edge/level Select Register */
6558 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
59
+#define OUTDTSEL 0x40 /* Output Data Select Register */
6660 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
6761
6862 #define RCAR_MAX_GPIO_PER_BANK 32
....@@ -122,7 +116,7 @@
122116
123117 spin_lock_irqsave(&p->lock, flags);
124118
125
- /* Configure postive or negative logic in POSNEG */
119
+ /* Configure positive or negative logic in POSNEG */
126120 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
127121
128122 /* Configure edge or level trigger in EDGLEVEL */
....@@ -148,7 +142,7 @@
148142 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
149143 unsigned int hwirq = irqd_to_hwirq(d);
150144
151
- dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
145
+ dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
152146
153147 switch (type & IRQ_TYPE_SENSE_MASK) {
154148 case IRQ_TYPE_LEVEL_HIGH:
....@@ -188,8 +182,7 @@
188182 if (p->irq_parent) {
189183 error = irq_set_irq_wake(p->irq_parent, on);
190184 if (error) {
191
- dev_dbg(&p->pdev->dev,
192
- "irq %u doesn't support irq_set_wake\n",
185
+ dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
193186 p->irq_parent);
194187 p->irq_parent = 0;
195188 }
....@@ -235,7 +228,7 @@
235228
236229 spin_lock_irqsave(&p->lock, flags);
237230
238
- /* Configure postive logic in POSNEG */
231
+ /* Configure positive logic in POSNEG */
239232 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
240233
241234 /* Select "General Input/Output Mode" in IOINTSEL */
....@@ -243,6 +236,10 @@
243236
244237 /* Select Input Mode or Output Mode in INOUTSEL */
245238 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
239
+
240
+ /* Select General Output Register to output data in OUTDTSEL */
241
+ if (p->has_outdtsel && output)
242
+ gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
246243
247244 spin_unlock_irqrestore(&p->lock, flags);
248245 }
....@@ -252,13 +249,15 @@
252249 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
253250 int error;
254251
255
- error = pm_runtime_get_sync(&p->pdev->dev);
256
- if (error < 0)
252
+ error = pm_runtime_get_sync(p->dev);
253
+ if (error < 0) {
254
+ pm_runtime_put(p->dev);
257255 return error;
256
+ }
258257
259258 error = pinctrl_gpio_request(chip->base + offset);
260259 if (error)
261
- pm_runtime_put(&p->pdev->dev);
260
+ pm_runtime_put(p->dev);
262261
263262 return error;
264263 }
....@@ -275,14 +274,17 @@
275274 */
276275 gpio_rcar_config_general_input_output_mode(chip, offset, false);
277276
278
- pm_runtime_put(&p->pdev->dev);
277
+ pm_runtime_put(p->dev);
279278 }
280279
281280 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
282281 {
283282 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
284283
285
- return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
284
+ if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
285
+ return GPIO_LINE_DIRECTION_OUT;
286
+
287
+ return GPIO_LINE_DIRECTION_IN;
286288 }
287289
288290 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
....@@ -321,6 +323,9 @@
321323 u32 val, bankmask;
322324
323325 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
326
+ if (chip->valid_mask)
327
+ bankmask &= chip->valid_mask[0];
328
+
324329 if (!bankmask)
325330 return;
326331
....@@ -342,14 +347,17 @@
342347 }
343348
344349 struct gpio_rcar_info {
350
+ bool has_outdtsel;
345351 bool has_both_edge_trigger;
346352 };
347353
348354 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
355
+ .has_outdtsel = false,
349356 .has_both_edge_trigger = false,
350357 };
351358
352359 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
360
+ .has_outdtsel = true,
353361 .has_both_edge_trigger = true,
354362 };
355363
....@@ -403,21 +411,21 @@
403411
404412 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
405413 {
406
- struct device_node *np = p->pdev->dev.of_node;
414
+ struct device_node *np = p->dev->of_node;
407415 const struct gpio_rcar_info *info;
408416 struct of_phandle_args args;
409417 int ret;
410418
411
- info = of_device_get_match_data(&p->pdev->dev);
419
+ info = of_device_get_match_data(p->dev);
420
+ p->has_outdtsel = info->has_outdtsel;
421
+ p->has_both_edge_trigger = info->has_both_edge_trigger;
412422
413423 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
414424 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
415
- p->has_both_edge_trigger = info->has_both_edge_trigger;
416425
417426 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
418
- dev_warn(&p->pdev->dev,
419
- "Invalid number of gpio lines %u, using %u\n", *npins,
420
- RCAR_MAX_GPIO_PER_BANK);
427
+ dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
428
+ *npins, RCAR_MAX_GPIO_PER_BANK);
421429 *npins = RCAR_MAX_GPIO_PER_BANK;
422430 }
423431
....@@ -427,9 +435,10 @@
427435 static int gpio_rcar_probe(struct platform_device *pdev)
428436 {
429437 struct gpio_rcar_priv *p;
430
- struct resource *io, *irq;
438
+ struct resource *irq;
431439 struct gpio_chip *gpio_chip;
432440 struct irq_chip *irq_chip;
441
+ struct gpio_irq_chip *girq;
433442 struct device *dev = &pdev->dev;
434443 const char *name = dev_name(dev);
435444 unsigned int npins;
....@@ -439,7 +448,7 @@
439448 if (!p)
440449 return -ENOMEM;
441450
442
- p->pdev = pdev;
451
+ p->dev = dev;
443452 spin_lock_init(&p->lock);
444453
445454 /* Get device configuration from DT node */
....@@ -458,8 +467,7 @@
458467 goto err0;
459468 }
460469
461
- io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
462
- p->base = devm_ioremap_resource(dev, io);
470
+ p->base = devm_platform_ioremap_resource(pdev, 0);
463471 if (IS_ERR(p->base)) {
464472 ret = PTR_ERR(p->base);
465473 goto err0;
....@@ -481,25 +489,27 @@
481489 gpio_chip->ngpio = npins;
482490
483491 irq_chip = &p->irq_chip;
484
- irq_chip->name = name;
492
+ irq_chip->name = "gpio-rcar";
485493 irq_chip->parent_device = dev;
486494 irq_chip->irq_mask = gpio_rcar_irq_disable;
487495 irq_chip->irq_unmask = gpio_rcar_irq_enable;
488496 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
489497 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
490
- irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
498
+ irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
499
+
500
+ girq = &gpio_chip->irq;
501
+ girq->chip = irq_chip;
502
+ /* This will let us handle the parent IRQ in the driver */
503
+ girq->parent_handler = NULL;
504
+ girq->num_parents = 0;
505
+ girq->parents = NULL;
506
+ girq->default_type = IRQ_TYPE_NONE;
507
+ girq->handler = handle_level_irq;
491508
492509 ret = gpiochip_add_data(gpio_chip, p);
493510 if (ret) {
494511 dev_err(dev, "failed to add GPIO controller\n");
495512 goto err0;
496
- }
497
-
498
- ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
499
- IRQ_TYPE_NONE);
500
- if (ret) {
501
- dev_err(dev, "cannot add irqchip\n");
502
- goto err1;
503513 }
504514
505515 p->irq_parent = irq->start;
....@@ -558,6 +568,9 @@
558568 u32 mask;
559569
560570 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
571
+ if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
572
+ continue;
573
+
561574 mask = BIT(offset);
562575 /* I/O pin */
563576 if (!(p->bank_info.iointsel & mask)) {