add boot partition size

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/gpio/gpio-max77620.c
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@@ -1,11 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * MAXIM MAX77620 GPIO driver
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  *
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  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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  */
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7
 
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 #include <linux/gpio/driver.h>
..
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@@ -21,77 +18,115 @@
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 	struct gpio_chip	gpio_chip;
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 	struct regmap		*rmap;
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 	struct device		*dev;
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+	struct mutex		buslock; /* irq_bus_lock */
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+	unsigned int		irq_type[MAX77620_GPIO_NR];
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+	bool			irq_enabled[MAX77620_GPIO_NR];
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 };
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25
 
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-static const struct regmap_irq max77620_gpio_irqs[] = {
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-	[0] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE0,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 0,
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-	},
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-	[1] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE1,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 1,
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-	},
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-	[2] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE2,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 2,
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-	},
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-	[3] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE3,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 3,
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-	},
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-	[4] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE4,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 4,
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-	},
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-	[5] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE5,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 5,
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-	},
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-	[6] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE6,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 6,
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-	},
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-	[7] = {
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-		.mask = MAX77620_IRQ_LVL2_GPIO_EDGE7,
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-		.type_rising_mask = MAX77620_CNFG_GPIO_INT_RISING,
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-		.type_falling_mask = MAX77620_CNFG_GPIO_INT_FALLING,
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-		.reg_offset = 0,
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-		.type_reg_offset = 7,
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-	},
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-};
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+static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
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+{
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+	struct max77620_gpio *gpio = data;
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+	unsigned int value, offset;
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+	unsigned long pending;
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+	int err;
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32
 
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-static const struct regmap_irq_chip max77620_gpio_irq_chip = {
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-	.name = "max77620-gpio",
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-	.irqs = max77620_gpio_irqs,
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-	.num_irqs = ARRAY_SIZE(max77620_gpio_irqs),
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-	.num_regs = 1,
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-	.num_type_reg = 8,
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-	.irq_reg_stride = 1,
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-	.type_reg_stride = 1,
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-	.status_base = MAX77620_REG_IRQ_LVL2_GPIO,
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-	.type_base = MAX77620_REG_GPIO0,
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+	err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
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+	if (err < 0) {
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+		dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
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+		return IRQ_NONE;
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+	}
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+
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+	pending = value;
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+
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+	for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
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+		unsigned int virq;
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+
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+		virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
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+		handle_nested_irq(virq);
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+	}
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+
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+	return IRQ_HANDLED;
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+}
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+
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+static void max77620_gpio_irq_mask(struct irq_data *data)
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+{
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+	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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+	struct max77620_gpio *gpio = gpiochip_get_data(chip);
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+
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+	gpio->irq_enabled[data->hwirq] = false;
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+}
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+
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+static void max77620_gpio_irq_unmask(struct irq_data *data)
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+{
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+	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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+	struct max77620_gpio *gpio = gpiochip_get_data(chip);
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+
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+	gpio->irq_enabled[data->hwirq] = true;
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+}
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+
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+static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
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+{
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+	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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+	struct max77620_gpio *gpio = gpiochip_get_data(chip);
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+	unsigned int irq_type;
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+
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+	switch (type) {
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+	case IRQ_TYPE_EDGE_RISING:
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+		irq_type = MAX77620_CNFG_GPIO_INT_RISING;
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+		break;
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+
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+	case IRQ_TYPE_EDGE_FALLING:
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+		irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
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+		break;
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+
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+	case IRQ_TYPE_EDGE_BOTH:
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+		irq_type = MAX77620_CNFG_GPIO_INT_RISING |
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+			   MAX77620_CNFG_GPIO_INT_FALLING;
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+		break;
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+
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+	default:
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+		return -EINVAL;
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+	}
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+
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+	gpio->irq_type[data->hwirq] = irq_type;
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+
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+	return 0;
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+}
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+
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+static void max77620_gpio_bus_lock(struct irq_data *data)
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+{
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+	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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+	struct max77620_gpio *gpio = gpiochip_get_data(chip);
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+
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+	mutex_lock(&gpio->buslock);
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+}
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+
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+static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
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+{
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+	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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+	struct max77620_gpio *gpio = gpiochip_get_data(chip);
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+	unsigned int value, offset = data->hwirq;
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+	int err;
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+
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+	value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
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+
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+	err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
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+				 MAX77620_CNFG_GPIO_INT_MASK, value);
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+	if (err < 0)
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+		dev_err(chip->parent, "failed to update interrupt mask: %d\n",
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+			err);
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+
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+	mutex_unlock(&gpio->buslock);
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+}
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+
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+static struct irq_chip max77620_gpio_irqchip = {
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+	.name		= "max77620-gpio",
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+	.irq_mask	= max77620_gpio_irq_mask,
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+	.irq_unmask	= max77620_gpio_irq_unmask,
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+	.irq_set_type	= max77620_gpio_set_irq_type,
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+	.irq_bus_lock	= max77620_gpio_bus_lock,
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+	.irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
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+	.flags		= IRQCHIP_MASK_ON_SUSPEND,
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 };
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 static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
..
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@@ -225,48 +260,73 @@
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 	return -ENOTSUPP;
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 }
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262
 
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-static int max77620_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
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+static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
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 {
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-	struct max77620_gpio *mgpio = gpiochip_get_data(gc);
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-	struct max77620_chip *chip = dev_get_drvdata(mgpio->dev->parent);
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+	struct max77620_gpio *gpio = gpiochip_get_data(gc);
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+	unsigned int i;
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+	int err;
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268
 
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-	return regmap_irq_get_virq(chip->gpio_irq_data, offset);
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+	/*
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+	 * GPIO interrupts may be left ON after bootloader, hence let's
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+	 * pre-initialize hardware to the expected state by disabling all
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+	 * the interrupts.
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+	 */
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+	for (i = 0; i < MAX77620_GPIO_NR; i++) {
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+		err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
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+					 MAX77620_CNFG_GPIO_INT_MASK, 0);
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+		if (err < 0) {
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+			dev_err(gpio->dev,
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+				"failed to disable interrupt: %d\n", err);
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+			return err;
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+		}
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+	}
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+
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+	return 0;
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 }
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 static int max77620_gpio_probe(struct platform_device *pdev)
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 {
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 	struct max77620_chip *chip =  dev_get_drvdata(pdev->dev.parent);
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 	struct max77620_gpio *mgpio;
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-	int gpio_irq;
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+	struct gpio_irq_chip *girq;
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+	unsigned int gpio_irq;
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 	int ret;
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294
 
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-	gpio_irq = platform_get_irq(pdev, 0);
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-	if (gpio_irq <= 0) {
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-		dev_err(&pdev->dev, "GPIO irq not available %d\n", gpio_irq);
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-		return -ENODEV;
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-	}
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+	ret = platform_get_irq(pdev, 0);
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+	if (ret < 0)
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+		return ret;
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+
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+	gpio_irq = ret;
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 	mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
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 	if (!mgpio)
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 		return -ENOMEM;
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304
 
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+	mutex_init(&mgpio->buslock);
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 	mgpio->rmap = chip->rmap;
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 	mgpio->dev = &pdev->dev;
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308
 
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 	mgpio->gpio_chip.label = pdev->name;
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-	mgpio->gpio_chip.parent = &pdev->dev;
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+	mgpio->gpio_chip.parent = pdev->dev.parent;
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 	mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
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 	mgpio->gpio_chip.get = max77620_gpio_get;
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 	mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
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 	mgpio->gpio_chip.set = max77620_gpio_set;
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 	mgpio->gpio_chip.set_config = max77620_gpio_set_config;
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-	mgpio->gpio_chip.to_irq = max77620_gpio_to_irq;
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 	mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
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 	mgpio->gpio_chip.can_sleep = 1;
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 	mgpio->gpio_chip.base = -1;
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-#ifdef CONFIG_OF_GPIO
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-	mgpio->gpio_chip.of_node = pdev->dev.parent->of_node;
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-#endif
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+
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+	girq = &mgpio->gpio_chip.irq;
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+	girq->chip = &max77620_gpio_irqchip;
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+	/* This will let us handle the parent IRQ in the driver */
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+	girq->parent_handler = NULL;
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+	girq->num_parents = 0;
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+	girq->parents = NULL;
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+	girq->default_type = IRQ_TYPE_NONE;
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+	girq->handler = handle_edge_irq;
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+	girq->init_hw = max77620_gpio_irq_init_hw,
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+	girq->threaded = true;
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330
 
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 	platform_set_drvdata(pdev, mgpio);
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332
 
..
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@@ -276,12 +336,11 @@
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 		return ret;
277
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 	}
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338
 
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-	ret = devm_regmap_add_irq_chip(&pdev->dev, chip->rmap, gpio_irq,
280
-				       IRQF_ONESHOT, -1,
281
-				       &max77620_gpio_irq_chip,
282
-				       &chip->gpio_irq_data);
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+	ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
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+					max77620_gpio_irqhandler, IRQF_ONESHOT,
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+					"max77620-gpio", mgpio);
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342
 	if (ret < 0) {
284
-		dev_err(&pdev->dev, "Failed to add gpio irq_chip %d\n", ret);
343
+		dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
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 		return ret;
286
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 	}
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