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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpio/gpio-ich.c
....@@ -1,32 +1,18 @@
1
+// SPDX-License-Identifier: GPL-2.0+
12 /*
23  * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
34  *
45  * Copyright (C) 2010 Extreme Engineering Solutions.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
15
- *
16
- * You should have received a copy of the GNU General Public License
17
- * along with this program; if not, write to the Free Software
18
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
196  */
207 
21
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
228 
9
+#include <linux/bitops.h>
10
+#include <linux/gpio/driver.h>
2311 #include <linux/ioport.h>
12
+#include <linux/mfd/lpc_ich.h>
2413 #include <linux/module.h>
2514 #include <linux/pci.h>
26
-#include <linux/gpio/driver.h>
2715 #include <linux/platform_device.h>
28
-#include <linux/mfd/lpc_ich.h>
29
-#include <linux/bitops.h>
3016 
3117 #define DRV_NAME "gpio_ich"
3218 
....@@ -88,8 +74,8 @@
8874 	u32 use_sel_ignore[3];
8975 
9076 	/* Some chipsets have quirks, let these use their own request/get */
91
-	int (*request)(struct gpio_chip *chip, unsigned offset);
92
-	int (*get)(struct gpio_chip *chip, unsigned offset);
77
+	int (*request)(struct gpio_chip *chip, unsigned int offset);
78
+	int (*get)(struct gpio_chip *chip, unsigned int offset);
9379 
9480 	/*
9581 	 * Some chipsets don't let reading output values on GPIO_LVL register
....@@ -100,10 +86,10 @@
10086 
10187 static struct {
10288 	spinlock_t lock;
103
-	struct platform_device *dev;
89
+	struct device *dev;
10490 	struct gpio_chip chip;
10591 	struct resource *gpio_base;	/* GPIO IO base */
106
-	struct resource *pm_base;	/* Power Mangagment IO base */
92
+	struct resource *pm_base;	/* Power Management IO base */
10793 	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
10894 	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
10995 	u8 use_gpio;		/* Which GPIO groups are usable */
....@@ -112,16 +98,14 @@
11298 
11399 static int modparam_gpiobase = -1;	/* dynamic */
114100 module_param_named(gpiobase, modparam_gpiobase, int, 0444);
115
-MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
116
-			   "which is the default.");
101
+MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
117102 
118
-static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
103
+static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
119104 {
120105 	unsigned long flags;
121106 	u32 data, tmp;
122107 	int reg_nr = nr / 32;
123108 	int bit = nr & 0x1f;
124
-	int ret = 0;
125109 
126110 	spin_lock_irqsave(&ichx_priv.lock, flags);
127111 
....@@ -142,15 +126,13 @@
142126 
143127 	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
144128 			ichx_priv.gpio_base);
145
-	if (verify && data != tmp)
146
-		ret = -EPERM;
147129 
148130 	spin_unlock_irqrestore(&ichx_priv.lock, flags);
149131 
150
-	return ret;
132
+	return (verify && data != tmp) ? -EPERM : 0;
151133 }
152134 
153
-static int ichx_read_bit(int reg, unsigned nr)
135
+static int ichx_read_bit(int reg, unsigned int nr)
154136 {
155137 	unsigned long flags;
156138 	u32 data;
....@@ -170,29 +152,29 @@
170152 	return !!(data & BIT(bit));
171153 }
172154 
173
-static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
155
+static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
174156 {
175157 	return !!(ichx_priv.use_gpio & BIT(nr / 32));
176158 }
177159 
178
-static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
160
+static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
179161 {
180
-	return ichx_read_bit(GPIO_IO_SEL, nr);
162
+	if (ichx_read_bit(GPIO_IO_SEL, nr))
163
+		return GPIO_LINE_DIRECTION_IN;
164
+
165
+	return GPIO_LINE_DIRECTION_OUT;
181166 }
182167 
183
-static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
168
+static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
184169 {
185170 	/*
186171 	 * Try setting pin as an input and verify it worked since many pins
187172 	 * are output-only.
188173 	 */
189
-	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
190
-		return -EINVAL;
191
-
192
-	return 0;
174
+	return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
193175 }
194176 
195
-static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
177
+static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
196178 					int val)
197179 {
198180 	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
....@@ -206,18 +188,15 @@
206188 	 * Try setting pin as an output and verify it worked since many pins
207189 	 * are input-only.
208190 	 */
209
-	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
210
-		return -EINVAL;
211
-
212
-	return 0;
191
+	return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
213192 }
214193 
215
-static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
194
+static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
216195 {
217196 	return ichx_read_bit(GPIO_LVL, nr);
218197 }
219198 
220
-static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
199
+static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
221200 {
222201 	unsigned long flags;
223202 	u32 data;
....@@ -244,7 +223,7 @@
244223 	}
245224 }
246225 
247
-static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
226
+static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
248227 {
249228 	if (!ichx_gpio_check_available(chip, nr))
250229 		return -ENXIO;
....@@ -261,7 +240,7 @@
261240 	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
262241 }
263242 
264
-static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
243
+static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
265244 {
266245 	/*
267246 	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
....@@ -275,7 +254,7 @@
275254 	return ichx_gpio_request(chip, nr);
276255 }
277256 
278
-static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
257
+static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
279258 {
280259 	ichx_write_bit(GPIO_LVL, nr, val, 0);
281260 }
....@@ -284,7 +263,7 @@
284263 {
285264 	chip->owner = THIS_MODULE;
286265 	chip->label = DRV_NAME;
287
-	chip->parent = &ichx_priv.dev->dev;
266
+	chip->parent = ichx_priv.dev;
288267 
289268 	/* Allow chip-specific overrides of request()/get() */
290269 	chip->request = ichx_priv.desc->request ?
....@@ -407,14 +386,13 @@
407386 
408387 static int ichx_gpio_probe(struct platform_device *pdev)
409388 {
389
+	struct device *dev = &pdev->dev;
390
+	struct lpc_ich_info *ich_info = dev_get_platdata(dev);
410391 	struct resource *res_base, *res_pm;
411392 	int err;
412
-	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
413393 
414394 	if (!ich_info)
415395 		return -ENODEV;
416
-
417
-	ichx_priv.dev = pdev;
418396 
419397 	switch (ich_info->gpio_version) {
420398 	case ICH_I3100_GPIO:
....@@ -445,19 +423,21 @@
445423 		return -ENODEV;
446424 	}
447425 
426
+	ichx_priv.dev = dev;
448427 	spin_lock_init(&ichx_priv.lock);
428
+
449429 	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
450
-	ichx_priv.use_gpio = ich_info->use_gpio;
451
-	err = ichx_gpio_request_regions(&pdev->dev, res_base, pdev->name,
452
-					ichx_priv.use_gpio);
430
+	err = ichx_gpio_request_regions(dev, res_base, pdev->name,
431
+					ich_info->use_gpio);
453432 	if (err)
454433 		return err;
455434 
456435 	ichx_priv.gpio_base = res_base;
436
+	ichx_priv.use_gpio = ich_info->use_gpio;
457437 
458438 	/*
459439 	 * If necessary, determine the I/O address of ACPI/power management
460
-	 * registers which are needed to read the the GPE0 register for GPI pins
440
+	 * registers which are needed to read the GPE0 register for GPI pins
461441 	 * 0 - 15 on some chipsets.
462442 	 */
463443 	if (!ichx_priv.desc->uses_gpe0)
....@@ -465,13 +445,13 @@
465445 
466446 	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
467447 	if (!res_pm) {
468
-		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
448
+		dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
469449 		goto init;
470450 	}
471451 
472
-	if (!devm_request_region(&pdev->dev, res_pm->start,
473
-			resource_size(res_pm), pdev->name)) {
474
-		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
452
+	if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
453
+				 pdev->name)) {
454
+		dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
475455 		goto init;
476456 	}
477457 
....@@ -481,12 +461,12 @@
481461 	ichx_gpiolib_setup(&ichx_priv.chip);
482462 	err = gpiochip_add_data(&ichx_priv.chip, NULL);
483463 	if (err) {
484
-		pr_err("Failed to register GPIOs\n");
464
+		dev_err(dev, "Failed to register GPIOs\n");
485465 		return err;
486466 	}
487467 
488
-	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
489
-	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
468
+	dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
469
+		 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
490470 
491471 	return 0;
492472 }