forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/gpio/gpio-aspeed.c
....@@ -1,12 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright 2015 IBM Corp.
34  *
45  * Joel Stanley <joel@jms.id.au>
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License
8
- * as published by the Free Software Foundation; either version
9
- * 2 of the License, or (at your option) any later version.
106  */
117 
128 #include <asm/div64.h>
....@@ -56,7 +52,8 @@
5652  */
5753 struct aspeed_gpio {
5854 	struct gpio_chip chip;
59
-	spinlock_t lock;
55
+	struct irq_chip irqc;
56
+	raw_spinlock_t lock;
6057 	void __iomem *base;
6158 	int irq;
6259 	const struct aspeed_gpio_config *config;
....@@ -416,14 +413,14 @@
416413 	unsigned long flags;
417414 	bool copro;
418415 
419
-	spin_lock_irqsave(&gpio->lock, flags);
416
+	raw_spin_lock_irqsave(&gpio->lock, flags);
420417 	copro = aspeed_gpio_copro_request(gpio, offset);
421418 
422419 	__aspeed_gpio_set(gc, offset, val);
423420 
424421 	if (copro)
425422 		aspeed_gpio_copro_release(gpio, offset);
426
-	spin_unlock_irqrestore(&gpio->lock, flags);
423
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
427424 }
428425 
429426 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
....@@ -438,7 +435,7 @@
438435 	if (!have_input(gpio, offset))
439436 		return -ENOTSUPP;
440437 
441
-	spin_lock_irqsave(&gpio->lock, flags);
438
+	raw_spin_lock_irqsave(&gpio->lock, flags);
442439 
443440 	reg = ioread32(addr);
444441 	reg &= ~GPIO_BIT(offset);
....@@ -448,7 +445,7 @@
448445 	if (copro)
449446 		aspeed_gpio_copro_release(gpio, offset);
450447 
451
-	spin_unlock_irqrestore(&gpio->lock, flags);
448
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
452449 
453450 	return 0;
454451 }
....@@ -466,7 +463,7 @@
466463 	if (!have_output(gpio, offset))
467464 		return -ENOTSUPP;
468465 
469
-	spin_lock_irqsave(&gpio->lock, flags);
466
+	raw_spin_lock_irqsave(&gpio->lock, flags);
470467 
471468 	reg = ioread32(addr);
472469 	reg |= GPIO_BIT(offset);
....@@ -477,7 +474,7 @@
477474 
478475 	if (copro)
479476 		aspeed_gpio_copro_release(gpio, offset);
480
-	spin_unlock_irqrestore(&gpio->lock, flags);
477
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
481478 
482479 	return 0;
483480 }
....@@ -490,19 +487,18 @@
490487 	u32 val;
491488 
492489 	if (!have_input(gpio, offset))
493
-		return 0;
490
+		return GPIO_LINE_DIRECTION_OUT;
494491 
495492 	if (!have_output(gpio, offset))
496
-		return 1;
493
+		return GPIO_LINE_DIRECTION_IN;
497494 
498
-	spin_lock_irqsave(&gpio->lock, flags);
495
+	raw_spin_lock_irqsave(&gpio->lock, flags);
499496 
500497 	val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
501498 
502
-	spin_unlock_irqrestore(&gpio->lock, flags);
499
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
503500 
504
-	return !val;
505
-
501
+	return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
506502 }
507503 
508504 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
....@@ -543,14 +539,14 @@
543539 
544540 	status_addr = bank_reg(gpio, bank, reg_irq_status);
545541 
546
-	spin_lock_irqsave(&gpio->lock, flags);
542
+	raw_spin_lock_irqsave(&gpio->lock, flags);
547543 	copro = aspeed_gpio_copro_request(gpio, offset);
548544 
549545 	iowrite32(bit, status_addr);
550546 
551547 	if (copro)
552548 		aspeed_gpio_copro_release(gpio, offset);
553
-	spin_unlock_irqrestore(&gpio->lock, flags);
549
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
554550 }
555551 
556552 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
....@@ -569,7 +565,7 @@
569565 
570566 	addr = bank_reg(gpio, bank, reg_irq_enable);
571567 
572
-	spin_lock_irqsave(&gpio->lock, flags);
568
+	raw_spin_lock_irqsave(&gpio->lock, flags);
573569 	copro = aspeed_gpio_copro_request(gpio, offset);
574570 
575571 	reg = ioread32(addr);
....@@ -581,7 +577,7 @@
581577 
582578 	if (copro)
583579 		aspeed_gpio_copro_release(gpio, offset);
584
-	spin_unlock_irqrestore(&gpio->lock, flags);
580
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
585581 }
586582 
587583 static void aspeed_gpio_irq_mask(struct irq_data *d)
....@@ -615,16 +611,16 @@
615611 	switch (type & IRQ_TYPE_SENSE_MASK) {
616612 	case IRQ_TYPE_EDGE_BOTH:
617613 		type2 |= bit;
618
-		/* fall through */
614
+		fallthrough;
619615 	case IRQ_TYPE_EDGE_RISING:
620616 		type0 |= bit;
621
-		/* fall through */
617
+		fallthrough;
622618 	case IRQ_TYPE_EDGE_FALLING:
623619 		handler = handle_edge_irq;
624620 		break;
625621 	case IRQ_TYPE_LEVEL_HIGH:
626622 		type0 |= bit;
627
-		/* fall through */
623
+		fallthrough;
628624 	case IRQ_TYPE_LEVEL_LOW:
629625 		type1 |= bit;
630626 		handler = handle_level_irq;
....@@ -633,7 +629,7 @@
633629 		return -EINVAL;
634630 	}
635631 
636
-	spin_lock_irqsave(&gpio->lock, flags);
632
+	raw_spin_lock_irqsave(&gpio->lock, flags);
637633 	copro = aspeed_gpio_copro_request(gpio, offset);
638634 
639635 	addr = bank_reg(gpio, bank, reg_irq_type0);
....@@ -653,7 +649,7 @@
653649 
654650 	if (copro)
655651 		aspeed_gpio_copro_release(gpio, offset);
656
-	spin_unlock_irqrestore(&gpio->lock, flags);
652
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
657653 
658654 	irq_set_handler_locked(d, handler);
659655 
....@@ -665,12 +661,14 @@
665661 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
666662 	struct irq_chip *ic = irq_desc_get_chip(desc);
667663 	struct aspeed_gpio *data = gpiochip_get_data(gc);
668
-	unsigned int i, p, girq;
664
+	unsigned int i, p, girq, banks;
669665 	unsigned long reg;
666
+	struct aspeed_gpio *gpio = gpiochip_get_data(gc);
670667 
671668 	chained_irq_enter(ic, desc);
672669 
673
-	for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) {
670
+	banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
671
+	for (i = 0; i < banks; i++) {
674672 		const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
675673 
676674 		reg = ioread32(bank_reg(data, bank, reg_irq_status));
....@@ -685,16 +683,11 @@
685683 	chained_irq_exit(ic, desc);
686684 }
687685 
688
-static struct irq_chip aspeed_gpio_irqchip = {
689
-	.name		= "aspeed-gpio",
690
-	.irq_ack	= aspeed_gpio_irq_ack,
691
-	.irq_mask	= aspeed_gpio_irq_mask,
692
-	.irq_unmask	= aspeed_gpio_irq_unmask,
693
-	.irq_set_type	= aspeed_gpio_set_type,
694
-};
695
-
696
-static void set_irq_valid_mask(struct aspeed_gpio *gpio)
686
+static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
687
+				       unsigned long *valid_mask,
688
+				       unsigned int ngpios)
697689 {
690
+	struct aspeed_gpio *gpio = gpiochip_get_data(gc);
698691 	const struct aspeed_bank_props *props = gpio->config->props;
699692 
700693 	while (!is_bank_props_sentinel(props)) {
....@@ -705,40 +698,14 @@
705698 		for_each_clear_bit(offset, &input, 32) {
706699 			unsigned int i = props->bank * 32 + offset;
707700 
708
-			if (i >= gpio->config->nr_gpios)
701
+			if (i >= gpio->chip.ngpio)
709702 				break;
710703 
711
-			clear_bit(i, gpio->chip.irq.valid_mask);
704
+			clear_bit(i, valid_mask);
712705 		}
713706 
714707 		props++;
715708 	}
716
-}
717
-
718
-static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
719
-		struct platform_device *pdev)
720
-{
721
-	int rc;
722
-
723
-	rc = platform_get_irq(pdev, 0);
724
-	if (rc < 0)
725
-		return rc;
726
-
727
-	gpio->irq = rc;
728
-
729
-	set_irq_valid_mask(gpio);
730
-
731
-	rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip,
732
-			0, handle_bad_irq, IRQ_TYPE_NONE);
733
-	if (rc) {
734
-		dev_info(&pdev->dev, "Could not add irqchip\n");
735
-		return rc;
736
-	}
737
-
738
-	gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip,
739
-				     gpio->irq, aspeed_gpio_irq_handler);
740
-
741
-	return 0;
742709 }
743710 
744711 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
....@@ -752,7 +719,7 @@
752719 
753720 	treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
754721 
755
-	spin_lock_irqsave(&gpio->lock, flags);
722
+	raw_spin_lock_irqsave(&gpio->lock, flags);
756723 	copro = aspeed_gpio_copro_request(gpio, offset);
757724 
758725 	val = readl(treg);
....@@ -766,7 +733,7 @@
766733 
767734 	if (copro)
768735 		aspeed_gpio_copro_release(gpio, offset);
769
-	spin_unlock_irqrestore(&gpio->lock, flags);
736
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
770737 
771738 	return 0;
772739 }
....@@ -892,7 +859,7 @@
892859 		return rc;
893860 	}
894861 
895
-	spin_lock_irqsave(&gpio->lock, flags);
862
+	raw_spin_lock_irqsave(&gpio->lock, flags);
896863 
897864 	if (timer_allocation_registered(gpio, offset)) {
898865 		rc = unregister_allocated_timer(gpio, offset);
....@@ -952,7 +919,7 @@
952919 	configure_timer(gpio, offset, i);
953920 
954921 out:
955
-	spin_unlock_irqrestore(&gpio->lock, flags);
922
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
956923 
957924 	return rc;
958925 }
....@@ -963,13 +930,13 @@
963930 	unsigned long flags;
964931 	int rc;
965932 
966
-	spin_lock_irqsave(&gpio->lock, flags);
933
+	raw_spin_lock_irqsave(&gpio->lock, flags);
967934 
968935 	rc = unregister_allocated_timer(gpio, offset);
969936 	if (!rc)
970937 		configure_timer(gpio, offset, 0);
971938 
972
-	spin_unlock_irqrestore(&gpio->lock, flags);
939
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
973940 
974941 	return rc;
975942 }
....@@ -1011,7 +978,7 @@
1011978 }
1012979 
1013980 /**
1014
- * aspeed_gpio_copro_set_ops - Sets the callbacks used for handhsaking with
981
+ * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
1015982  *                             the coprocessor for shared GPIO banks
1016983  * @ops: The callbacks
1017984  * @data: Pointer passed back to the callbacks
....@@ -1044,14 +1011,14 @@
10441011 	unsigned long flags;
10451012 
10461013 	if (!gpio->cf_copro_bankmap)
1047
-		gpio->cf_copro_bankmap = kzalloc(gpio->config->nr_gpios >> 3, GFP_KERNEL);
1014
+		gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
10481015 	if (!gpio->cf_copro_bankmap)
10491016 		return -ENOMEM;
1050
-	if (offset < 0 || offset > gpio->config->nr_gpios)
1017
+	if (offset < 0 || offset > gpio->chip.ngpio)
10511018 		return -EINVAL;
10521019 	bindex = offset >> 3;
10531020 
1054
-	spin_lock_irqsave(&gpio->lock, flags);
1021
+	raw_spin_lock_irqsave(&gpio->lock, flags);
10551022 
10561023 	/* Sanity check, this shouldn't happen */
10571024 	if (gpio->cf_copro_bankmap[bindex] == 0xff) {
....@@ -1072,7 +1039,7 @@
10721039 	if (bit)
10731040 		*bit = GPIO_OFFSET(offset);
10741041  bail:
1075
-	spin_unlock_irqrestore(&gpio->lock, flags);
1042
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
10761043 	return rc;
10771044 }
10781045 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
....@@ -1092,11 +1059,11 @@
10921059 	if (!gpio->cf_copro_bankmap)
10931060 		return -ENXIO;
10941061 
1095
-	if (offset < 0 || offset > gpio->config->nr_gpios)
1062
+	if (offset < 0 || offset > gpio->chip.ngpio)
10961063 		return -EINVAL;
10971064 	bindex = offset >> 3;
10981065 
1099
-	spin_lock_irqsave(&gpio->lock, flags);
1066
+	raw_spin_lock_irqsave(&gpio->lock, flags);
11001067 
11011068 	/* Sanity check, this shouldn't happen */
11021069 	if (gpio->cf_copro_bankmap[bindex] == 0) {
....@@ -1110,7 +1077,7 @@
11101077 		aspeed_gpio_change_cmd_source(gpio, bank, bindex,
11111078 					      GPIO_CMDSRC_ARM);
11121079  bail:
1113
-	spin_unlock_irqrestore(&gpio->lock, flags);
1080
+	raw_spin_unlock_irqrestore(&gpio->lock, flags);
11141081 	return rc;
11151082 }
11161083 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
....@@ -1145,9 +1112,26 @@
11451112 	/* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
11461113 	{ .nr_gpios = 232, .props = ast2500_bank_props, };
11471114 
1115
+static const struct aspeed_bank_props ast2600_bank_props[] = {
1116
+	/*     input	  output   */
1117
+	{4, 0xffffffff,  0x00ffffff}, /* Q/R/S/T */
1118
+	{5, 0xffffffff,  0xffffff00}, /* U/V/W/X */
1119
+	{6, 0x0000ffff,  0x0000ffff}, /* Y/Z */
1120
+	{ },
1121
+};
1122
+
1123
+static const struct aspeed_gpio_config ast2600_config =
1124
+	/*
1125
+	 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
1126
+	 * We expect ngpio being set in the device tree and this is a fallback
1127
+	 * option.
1128
+	 */
1129
+	{ .nr_gpios = 208, .props = ast2600_bank_props, };
1130
+
11481131 static const struct of_device_id aspeed_gpio_of_table[] = {
11491132 	{ .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
11501133 	{ .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1134
+	{ .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
11511135 	{}
11521136 };
11531137 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
....@@ -1156,19 +1140,18 @@
11561140 {
11571141 	const struct of_device_id *gpio_id;
11581142 	struct aspeed_gpio *gpio;
1159
-	struct resource *res;
1160
-	int rc, i, banks;
1143
+	int rc, i, banks, err;
1144
+	u32 ngpio;
11611145 
11621146 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
11631147 	if (!gpio)
11641148 		return -ENOMEM;
11651149 
1166
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1167
-	gpio->base = devm_ioremap_resource(&pdev->dev, res);
1150
+	gpio->base = devm_platform_ioremap_resource(pdev, 0);
11681151 	if (IS_ERR(gpio->base))
11691152 		return PTR_ERR(gpio->base);
11701153 
1171
-	spin_lock_init(&gpio->lock);
1154
+	raw_spin_lock_init(&gpio->lock);
11721155 
11731156 	gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
11741157 	if (!gpio_id)
....@@ -1184,8 +1167,10 @@
11841167 	gpio->config = gpio_id->data;
11851168 
11861169 	gpio->chip.parent = &pdev->dev;
1187
-	gpio->chip.ngpio = gpio->config->nr_gpios;
1188
-	gpio->chip.parent = &pdev->dev;
1170
+	err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
1171
+	gpio->chip.ngpio = (u16) ngpio;
1172
+	if (err)
1173
+		gpio->chip.ngpio = gpio->config->nr_gpios;
11891174 	gpio->chip.direction_input = aspeed_gpio_dir_in;
11901175 	gpio->chip.direction_output = aspeed_gpio_dir_out;
11911176 	gpio->chip.get_direction = aspeed_gpio_get_direction;
....@@ -1196,10 +1181,9 @@
11961181 	gpio->chip.set_config = aspeed_gpio_set_config;
11971182 	gpio->chip.label = dev_name(&pdev->dev);
11981183 	gpio->chip.base = -1;
1199
-	gpio->chip.irq.need_valid_mask = true;
12001184 
12011185 	/* Allocate a cache of the output registers */
1202
-	banks = DIV_ROUND_UP(gpio->config->nr_gpios, 32);
1186
+	banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
12031187 	gpio->dcache = devm_kcalloc(&pdev->dev,
12041188 				    banks, sizeof(u32), GFP_KERNEL);
12051189 	if (!gpio->dcache)
....@@ -1219,16 +1203,42 @@
12191203 		aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
12201204 	}
12211205 
1222
-	rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1223
-	if (rc < 0)
1224
-		return rc;
1206
+	/* Optionally set up an irqchip if there is an IRQ */
1207
+	rc = platform_get_irq(pdev, 0);
1208
+	if (rc > 0) {
1209
+		struct gpio_irq_chip *girq;
1210
+
1211
+		gpio->irq = rc;
1212
+		girq = &gpio->chip.irq;
1213
+		girq->chip = &gpio->irqc;
1214
+		girq->chip->name = dev_name(&pdev->dev);
1215
+		girq->chip->irq_ack = aspeed_gpio_irq_ack;
1216
+		girq->chip->irq_mask = aspeed_gpio_irq_mask;
1217
+		girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
1218
+		girq->chip->irq_set_type = aspeed_gpio_set_type;
1219
+		girq->parent_handler = aspeed_gpio_irq_handler;
1220
+		girq->num_parents = 1;
1221
+		girq->parents = devm_kcalloc(&pdev->dev, 1,
1222
+					     sizeof(*girq->parents),
1223
+					     GFP_KERNEL);
1224
+		if (!girq->parents)
1225
+			return -ENOMEM;
1226
+		girq->parents[0] = gpio->irq;
1227
+		girq->default_type = IRQ_TYPE_NONE;
1228
+		girq->handler = handle_bad_irq;
1229
+		girq->init_valid_mask = aspeed_init_irq_valid_mask;
1230
+	}
12251231 
12261232 	gpio->offset_timer =
12271233 		devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
12281234 	if (!gpio->offset_timer)
12291235 		return -ENOMEM;
12301236 
1231
-	return aspeed_gpio_setup_irqs(gpio, pdev);
1237
+	rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1238
+	if (rc < 0)
1239
+		return rc;
1240
+
1241
+	return 0;
12321242 }
12331243 
12341244 static struct platform_driver aspeed_gpio_driver = {